JP3599500B2 - Semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a structure of a single electronic memory using the semiconductor memory device and a method of manufacturing the same.
[0002]
[Prior art]
Although a single electronic device that can operate with only one electron is expected as the ultimate electronic device, there has been a major obstacle that it operates only at a very low temperature despite many studies. In 1993, Yano et al. Of Hitachi succeeded in operating a single-electron device (including a single-electron memory) using an ultra-thin polycrystalline Si transistor at room temperature for the first time in the world (IEEE International Electron Devices Meeting 1993, 541 (1993)). )). Hereinafter, the structure of a single-electron memory developed by Yano et al. And a manufacturing method thereof will be described with reference to the drawings.
[0003]
FIG. 24 shows a plan view (a) and an AA ′ cross-sectional view (b) and (c) of an ultra-thin polycrystalline Si transistor. First, the single crystal Si substrate 601 is thermally oxidized to form a 500 nm SiO ₂ After the film 602 is formed, 50 nm SiO 2 is formed by a low pressure chemical vapor deposition method (hereinafter, referred to as an LP-CVD method). ₂ A film 603 is deposited. Subsequently, monosilane (SiH ₄ ) And phosphine (PH ₃ ), A polycrystalline Si film 604 containing phosphorus is deposited to a thickness of 50 nm by an LP-CVD method, and the phosphorus-doped polycrystalline Si film 604 is processed into a desired shape by a well-known lithography and dry etching technique. 604 (a) and a drain wiring 604 (b) are formed.
[0004]
Subsequently, an amorphous Si film to be a channel layer 605 is deposited to a thickness of about 4 nm by an LP-CVD method using thermal decomposition of monosilane at a temperature of about 500 ° C. ₂ A film 606 is continuously deposited for about 10 nm. Here, the amorphous Si film is made of SiO ₂ At the temperature (750 ° C.) at which the film 606 is deposited, it is converted to a polycrystalline Si film 605. The above SiO ₂ The film 606 functions as a part of the gate insulating film, but also serves as a protective film when the channel layer 605 is processed later.
[0005]
The characteristics of the single-electron memory using the ultra-thin polycrystalline Si as the channel layer, that is, the threshold shift amount and the charge retention time, are more desirably as the thickness of the channel polycrystalline Si film 605 is smaller. It is preferably 5 nm or less. Next, the ultra-thin polycrystalline Si film 605 and SiO 2 are formed by electron beam (EB) lithography and dry etching. ₂ The film 606 is processed into a desired shape to form a channel layer 605 (FIG. 24B).
[0006]
Next, about 30 nm of SiO to be the gate insulating film 607 is formed by the CVD method. ₂ After depositing the film 607, a polycrystalline Si film 608 containing phosphorus is deposited for about 100 m. Finally, the phosphorus-doped polycrystalline Si film 608 is processed into a desired shape by lithography and dry etching to form a gate electrode wiring 608 (word line 608) (FIG. 24C).
[0007]
In a single-electron memory using an ultra-thin polycrystalline Si film, a memory element is formed by one transistor, so that the cell area can be extremely reduced. FIG. 24A is a plan view of a memory array of a single electronic memory. A common source line layout is used in which the source wiring 604 (a) of adjacent transistors is common. In the figure, the data lines (drain lines) of the respective memory cells are indicated by D1 to D5, the common source lines (source lines) are indicated by S1 to S4, and the word lines (gate electrodes) are indicated by W1 and W2. . As shown in the figure, when a memory cell was prototyped with a design rule of a minimum processing size of 0.2 μm, 0.96 μm with 4 bits ² (2.4 × 0.4 μm) projected area, ie 0.24 μm ² Can realize one bit.
[0008]
[Problems to be solved by the invention]
The current single-electron memory is about two to three orders of magnitude slower than an SRAM or DRAM in terms of operating speed, but is non-volatile, has a simple memory cell structure, can be applied to conventional processes as it is, and has been miniaturized to the limit. It has a great advantage over conventional semiconductor memories, such as being operable. Therefore, it can be said that it is the semiconductor memory most suitable for high integration among future semiconductor memories.
[0009]
However, since the current memory cell structure is a planar structure, that is, a process in which source and drain wirings are formed in the same layer, the cell size is limited by the minimum processing size as in DRAM and the like. That is, in the current structure, the integration degree of about 3 to 4 times that of the DRAM is the limit (when the same design rule is used), and the feature of the single electronic memory that can be operated even if it is miniaturized to the limit is fully utilized. I can't.
[0010]
On the other hand, if EB lithography is applied, further miniaturization, specifically processing of 0.05 to 0.1 μm is possible, but using EB lithography many times lacks feasibility in terms of mass productivity. Therefore, when mass-producing a single-electron memory with the current planar cell structure, the minimum processing size (approximately 0.15 μm) achievable by excimer laser lithography is expected to be one barrier to high integration. .
[0011]
That is, how to reduce the cell area by using photolithography with high mass productivity is one of the important issues when using a single-electron memory as a general-purpose memory.
[0012]
[Means for Solving the Problems]
The above object can be achieved by making the cell structure three-dimensional, that is, by overlapping the layout of the source and the drain two-dimensionally via the insulating film. Further, in the three-dimensional cell structure, an insulating film fills a gap between adjacent stacked source and drain wirings which are planarly overlapped with each other, flattens the surface, and then forms a hole pattern in which side walls of the source and drain wirings are exposed. By forming a cell, processing of a channel layer and a gate electrode over a high step can be facilitated.
[0013]
Specifically, a step of forming a source / drain stacked wiring which overlaps two-dimensionally via an insulating film having a thickness corresponding to the channel length, a step of embedding an adjacent stacked wiring with an insulating film, Forming a hole pattern that exposes the side wall portions of the source and drain stacked wiring overlapped with the above, and after depositing the channel layer and the protective insulating film, anisotropically dry etching the entire surface to form only the hole pattern side wall portions in a self-aligned manner. The step of leaving the channel layer in the first step and the step of forming the gate insulating film and the gate electrode make it possible to form a memory cell only in the hole pattern.
[0014]
In addition, the insulating film that insulates and separates the source wiring and the drain wiring in the hole pattern, that is, the side wall of the insulating film serving as the base of the channel layer is recessed by a desired length from the edge of the side wall of the source and drain wirings. After that, the channel layer can be formed only between the source and the drain by depositing the channel layer and performing anisotropic dry etching on the entire surface.
[0015]
As described above, by making the memory cell structure three-dimensional, it becomes possible to form a memory cell at the intersection of a data line (drain wiring) and a word line (gate wiring). % Of the cell area can be reduced. In addition, a structure in which two memory cells are formed at the intersection of a data line and a word line, that is, a drain line 1 / common source line / drain line 2 structure in the vertical direction can reduce the cell area by about 35% of the planar structure. Can be reduced to
[0016]
However, if the cell structure is simply made vertical, a problem arises in processing the channel layer and the gate electrode wiring on the high step. A specific example will be described with reference to FIG. FIGS. 25A and 25B are ideal diagrams when the channel layer 707 (polycrystalline Si) is etched using the resist 708 as a mask. A source wiring 703 and a drain wiring 705 are arranged so as to overlap in a plane with an insulating film 704 having a thickness corresponding to a channel length, and a channel polycrystalline Si film 707 is formed on one side wall of the stacked wiring. Then, the cell area can be greatly reduced. However, in such a shape, processing of the channel polycrystalline Si film 707 becomes very difficult. Since anisotropic dry etching, which is usually used for processing a Si film, hardly progresses in the lateral direction, overetching corresponding to the height of the step is required to completely remove the channel Si707. Become. However, even if the over-etching is performed, it is very difficult to process the thin polycrystalline Si film on the vertical step, and an etching residue is left as shown in FIG. On the other hand, according to the isotropic dry etching method in which the etching in the lateral direction also proceeds, a defect occurs in which the source 703 and the drain wiring 705 formed of the same material as the channel polycrystalline Si film 707 are largely etched (FIG. 25 (c)). Further, even in the formation of the gate electrode wiring performed after the channel processing, the processing on the high step is very difficult, and the remaining etch or the like is fatal such as a short circuit between gates.
[0017]
According to the present invention, since the channel can be formed only on the side wall portion of the hole pattern in a self-aligned manner by dry etching the entire surface of the channel layer, the above-described problem associated with the formation of the channel layer does not occur. Also, in the processing of the gate electrode wiring, processing on a high step can be avoided, so that problems such as remaining etch do not occur.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
(Example 1)
A first embodiment of the present invention will be described with reference to FIGS. First, in FIG. 2A, a P-type (100) single-crystal Si substrate 101 is first thermally oxidized in a steam atmosphere at 1000 ° C. to form a 500-nm thick SiO 2 substrate. ₂ After the film 102 is formed, a phosphorus-doped polycrystalline Si film 103 containing a high concentration of phosphorus (P) having a thickness of 50 nm and a SiO film having a thickness of 150 nm are formed by a chemical vapor deposition method (hereinafter referred to as a CVD method). ₂ Film 104, 80 nm phosphorus doped polycrystalline Si film 105, and 100 nm SiO ₂ Films 106 are sequentially deposited. The phosphorus concentration of the phosphorus-doped polycrystalline Si films 103 and 105 is 3 × 10 ²⁰ / Cm ³ And For deposition, monosilane (SiH ₄ ) And phosphine (PH ₃ ) Was deposited at a temperature of 620 ° C. In addition, SiO ₂ The films 104 and 106 are made of monosilane (SiH ₄ ) And nitrous oxide (N ₂ O) was used as a source gas, and deposition was performed at a temperature of 750 ° C.
[0019]
Next, using the krypton fluoride (KrF) excimer laser lithography and dry etching, the SiO 2 ₂ Film 106 / phosphorus-doped polycrystalline Si film 105 / SiO ₂ A layered film composed of the film 104 and the phosphorus-doped polycrystalline Si film 103 is patterned to form a line / space having a width of 0.2 μm and an interval of 0.3 μm (FIG. 2A). Here, the lowermost phosphorus-doped polycrystalline Si wiring 103 is a source wiring 103 of a single-electron memory, ₂ The upper layer phosphorus-doped polycrystalline Si wiring 105 formed via the film 104 becomes the drain wiring 105. Here, the lower layer is a source wiring and the upper layer is a drain wiring, but there is no particular problem even if the source and drain wirings are upside down. Hereinafter, the wiring of the source / drain laminated film is referred to as a laminated wiring 110.
[0020]
Next, a 250 nm thick Si ₃ N ₄ The film 107 is deposited (FIG. 2B). Si ₃ N ₄ The film 107 is deposited by using dichlorosilane (SiH ₂ Cl ₂ ) And ammonia (NH ₃ ) Was used as a source gas, and deposition was performed at a temperature of 770 ° C.
[0021]
Next, by dry etching, the uppermost layer of SiO ₂ The above Si is used until the surface of the film 106 is exposed. ₃ N ₄ The entire surface of the film 107 is etched back, and Si ₃ N ₄ The buried surface is flattened by the film 107 (FIG. 2C). In this embodiment, the dry etching method is applied to the etching of the buried insulating film 107. However, when the chemical mechanical polishing (CMP) method is used, even better flatness is obtained.
[0022]
Next, as shown in the plan view of FIG. 3A, a rectangular resist hole pattern 108 is formed so that one side surface of the laminated wiring 110 is exposed, and then the Si is formed by dry etching. ₃ N ₄ The film 107 is etched (FIG. 3B). In this embodiment, the resist hole pattern 108 was formed by using electron beam (EB) lithography, and the long side length was set to 0.25 μm and the short side length was set to 0.1 μm. As shown in FIG. 3B, the uppermost layer of the stacked wiring 110 is made of Si. ₃ N ₄ SiO serving as a mask for etching the film 107 ₂ Since the film 106 is present, Si ₃ N ₄ Only the film 107 is etched, and the source 103, the drain wiring 105, and the SiO ₂ The structure is such that the side wall of the 104 film is exposed.
[0023]
Next, after removing the resist pattern 108 and cleaning the substrate surface, a 3 nm amorphous Si film serving as the channel layer 111 and a 10 nm SiO serving as the channel protective film are formed by the CVD method. ₂ Films 112 are sequentially deposited. In the present embodiment, monosilane (SiH ₄ ) Deposition was performed using gas at 480 ° C. and 80 Pa. Note that the above-mentioned amorphous Si film is formed of SiO 2 serving as a protective film. ₂ At the temperature (750 ° C.) at which the film 112 is deposited, it is converted into a polycrystalline Si film 111 (FIG. 3C). What is important here is the thickness of the channel polycrystalline Si film 111. In order to obtain a sufficient threshold shift, the thinner the film thickness is, the better it is. According to our study, good characteristics are obtained in a region of 5 nm or less. Obtained.
[0024]
Next, the anisotropic dry etching method ₂ The film 112 and the channel polycrystalline Si film 111 are sequentially etched. According to the anisotropic dry etching, the etching in the lateral direction hardly proceeds, so that the channel polycrystalline Si film 111 is formed only on the side wall of the hole pattern 109 as shown in FIGS. SiO ₂ The structure in which the film 112 remains is obtained. As shown in FIG. 4B, the channel polycrystalline Si film 111 has an insulating film 104 (SiO 2 in this figure). ₂ It is connected to the side wall of the source wiring 103 and the side wall of the drain wiring 105 via the film 104).
[0025]
Next, a 15-nm SiO film serving as the gate insulating film 113 is formed. ₂ FIG. 4C in which the film 113 is deposited by the CVD method. In this embodiment, SiO 2 formed as a protective film for the channel polycrystalline Si film 111 is used. ₂ The film 112 also becomes a part of the gate insulating film, but before the gate insulating film 113 is formed, the above SiO 2 is formed with a diluted hydrofluoric acid aqueous solution. ₂ The film 112 may be removed.
[0026]
Next, a 150-nm phosphorus-doped polycrystalline Si film 114 serving as a gate electrode 114 is deposited by a CVD method, and the phosphorus-doped polycrystalline Si film 114 is processed into a predetermined shape by a KrF excimer laser lithography and a dry etching method. The wiring lines 114 (FIGS. 1A and 1B).
[0027]
In this embodiment, the phosphorus-doped polycrystalline Si film 114 containing phosphorus at a high concentration is used as the gate electrode wiring line 114. However, a stacked film in which tungsten (W), titanium (Ti), or the like is formed thereon, Silicide film or titanium tetrachloride (TiCl ₄ ) And ammonia (NH ₃ In the case of using titanium nitride (TiN) formed by a CVD method using) as a raw material, the resistance was further reduced.
[0028]
As shown in FIGS. 1A and 1B, the processing of the gate electrode wiring 114 according to the present invention covers the hole pattern 109 and is performed on a flat portion. There is no. Also, in the subsequent steps, since there is only a step of about the thickness of the gate electrode wiring, it is possible to prevent defects such as short-circuits in the step of forming word lines and data lines.
[0029]
FIG. 1C is an enlarged view of a portion A of FIG. 1A which is a plan view. The memory cell is formed on the side wall portion of the hole pattern 109. The channel is a portion where the distance between the source wiring 103 and the drain wiring 104 is the shortest, that is, the region where the stacked wiring 110 and the channel polycrystalline Si film 111 are in contact. (The portion described as the effective channel width in FIG. 1C).
[0030]
Next, a method for connecting a source / drain wiring of a single-electron memory cell and a peripheral circuit will be described. FIG. 5A is a plan view of two memory cells formed by the above-described method, and FIG. 5B is a cross-sectional view. The cross-sectional view in FIG. 5B shows that 100 nm of SiO ₂ FIG. 4 shows a cross-sectional view in which a film 115 has been deposited. Therefore, as shown in FIGS. 5C and 5D, both ends of the memory cell (bb 'and cc' in FIG. ₂ The structure is such that the film 115 is deposited. First, a hole pattern 116 for taking out the source wiring 103 is formed by excimer laser lithography, and then SiO 2 is formed by dry etching. ₂ Film 115 / SiO ₂ Film 106 / phosphorus-doped polycrystalline Si film 105 / SiO ₂ The film 104 is sequentially etched to expose the surface of the source wiring 103 (FIG. 6C). Subsequently, after removing the resist pattern, a hole pattern 117 for extracting the drain wiring 105 is formed. Next, the dry etching method ₂ Film 115 / SiO ₂ The film 106 is etched to expose the surface of the drain wiring 105 (FIG. 6D). In this example, the diameter of the hole pattern was 0.35 μm.
[0031]
Next, 80 nm of SiO is formed by CVD. ₂ After the film 118 is deposited, the SiO 2 is deposited by anisotropic dry etching. ₂ The film 118 is etched to form SiO on the side walls of the hole patterns 116 and 117. ₂ A sidewall of the film 118 is formed. By this etching, the surfaces of the source wiring 103 and the drain wiring 105 are exposed again. Next, after removing the natural oxide film on the surface of the source 103 / drain wiring 105 with a diluted hydrofluoric acid aqueous solution, a phosphorus-doped polycrystalline Si film 119 containing phosphorus at a high concentration is deposited to a thickness of 150 nm by a CVD method. Finally, the above-mentioned phosphorus-doped polycrystalline Si film is processed into a predetermined shape to form a source line 119 (a) and a data line 119 (b) (FIG. 7).
[0032]
In the present embodiment, a phosphorus-doped polycrystalline Si film 119 containing a high concentration of phosphorus is used as the source line 119 (a) and the data line 119 (b) connected to the memory cell, and tungsten (W) is formed thereon. , Titanium (Ti) or other laminated films or silicide films thereof, or titanium tetrachloride (TiCl ₄ ) And ammonia (NH ₃ The same result was obtained by using titanium nitride (TiN) formed by CVD method using ()) as a raw material.
[0033]
Although not shown in the present embodiment, if a contact hole is formed to connect to the gate electrode wiring 114 which is perpendicular to the drain wiring 105, the word line is formed simultaneously with the source line (a) and the data line 119 (b). Can be formed.
[0034]
(Example 2)
Next, a second embodiment of the present invention will be described with reference to FIGS. The single crystal Si substrate 201 is thermally oxidized to 500 nm SiO ₂ After the formation of the film 202, SiO 2 is formed by the method described in the first embodiment. ₂ Film 206 / drain wiring 205 / SiO ₂ A laminated wiring 210 composed of the film 204 and the source wiring 203, a buried insulating film 207, and a hole pattern 209 are formed. Next, a 5-nm amorphous Si film and a 5-nm SiO ₂ Films 212 are sequentially deposited. For deposition of an amorphous Si film, SiH diluted to 20% with nitrogen is used. ₄ Was formed under the conditions of temperature 480 ° C., pressure and 80 Pa. The amorphous Si film is made of SiO ₂ At a temperature (750 ° C.) at which the film 212 is deposited, the film 212 is converted into a polycrystalline Si film 211.
[0035]
Next, the above-mentioned SiO 2 was formed by anisotropic dry etching. ₂ The film 212 / polycrystalline Si film 211 is entirely etched by an amount corresponding to each film thickness, and SiO 2 is formed only on the side wall of the hole pattern 209. ₂ The film 212 / polycrystalline Si film 211 is left (FIG. 8B). Subsequently, the SiO 2 on the channel polycrystalline Si film 211 is diluted with a diluted hydrofluoric acid aqueous solution. ₂ The film 212 is thinned to 3 nm by etching 2 nm (FIG. 8B).
[0036]
Next, minute Si grains 213 are deposited on the entire surface by the CVD method. Here, SiH diluted to 10% with helium (He) is used. ₄ Was formed under the conditions of a temperature of 580 ° C., a pressure and 20 Pa. SiH ₄ Of the polycrystalline Si film according to (1), the growth starts around the nucleus of Si formed on the base surface. The nucleation density has a correlation with the deposition temperature and the deposition pressure, and low-temperature and high-pressure conditions are preferable for obtaining a thin continuous structure. On the other hand, in order to obtain fine Si grains, if the nucleation density is reduced, that is, if deposition is performed at a high temperature and a low pressure, a continuous film is not formed, and fine Si grains are formed. Also, GeH ₄ By adding a small amount of, the nucleation density is further reduced, and fine SiGe grains can be formed (FIG. 8C).
[0037]
Next, 20 nm of SiO to be the gate insulating film 214 by the CVD method. ₂ After sequentially depositing a film 214 and a phosphorus-doped polycrystalline Si film 215 to be a gate electrode 215, the phosphorus-doped polycrystalline Si film 215 is processed into a predetermined shape to form a gate electrode wiring 215 (FIG. 9B). . FIG. 9 (c) is an enlarged view of a section B in FIG. 9 (b). The channel polycrystalline Si film 211 is formed on the side wall of the insulating film 204 that vertically separates the source wiring 203 and the drain wiring 205 and is connected to the side wall of the source 203 and the drain wiring 205. The fine-grain Si 213 is made of 3 nm SiO 2 serving as the tunnel insulating film 212. ₂ SiO formed on the film 212 and further serving as the gate insulating film 214 ₂ Covered with film 214.
[0038]
In the single-electron element manufactured in this embodiment, as a voltage is applied to the gate electrode 215, a channel having a fine width is formed in the channel polycrystalline Si film 211. When a voltage is further applied, electrons are repelled from the channel and are captured in the fine Si 213. That is, the fine Si 213 functions as a carrier confinement region. When the electrons are captured by the fine Si213, current stops flowing through the channel due to Coulomb repulsion. Therefore, it is possible to store information depending on the presence or absence of the carrier in the fine Si213.
[0039]
What is important in the present invention is the thickness of the tunnel insulating film 212 separating the fine Si 213 and the channel polycrystalline Si film 211, the diameter of the fine Si 213, and the interval (area density) between the fine Si 213. When the thickness of the tunnel insulating film 212 is increased, the carrier injection time is increased and the threshold shift amount is reduced. In this example, good results were obtained in a region where the thickness of the tunnel insulating film 212 was 5 nm or less.
[0040]
On the other hand, the diameter of the fine Si 213 is preferably as small as possible in view of the charge retention time. Further, the interval between the fine Si 213 is preferably as small as possible in order to suppress the variation of the carrier injection time. In the present example, good characteristics were exhibited in the region where the diameter of the fine Si213 and the interval thereof were 10 nm or less.
[0041]
(Example 3)
Next, a third embodiment of the present invention will be described with reference to FIGS. As in the first embodiment, a P-type (100) single-crystal Si substrate 301 is thermally oxidized in a steam atmosphere to form a 500 nm SiO ₂ After forming the film 302, an 80 nm phosphorus-doped polycrystalline Si film 303 serving as a common source plate 303 is deposited by a CVD method. Next, the phosphorus-doped polycrystalline Si film 303 is patterned into a predetermined shape by lithography and dry etching. Subsequently, 150 nm SiO 2 was formed by CVD. ₂ A film 304, a 50 nm phosphorus-doped polycrystalline Si film 305 serving as a drain wiring 305, and a 50 nm Si ₃ N ₄ Films 306 are sequentially deposited. Next, the Si ₃ N ₄ After the film 306 and the phosphorus-doped polycrystalline Si film 305 are patterned into a predetermined shape by a known method to form a drain wiring 305, a 30 nm SiO 2 film is formed by a CVD method. ₂ The film 307 is deposited. In the present embodiment, the source line 303 is processed into a plate shape so that a plurality of memory cells share the source line 303, that is, a common source line structure (FIGS. 10A and 10B). ).
[0042]
Next, as shown in the plan view of FIG. 10A, a rectangular resist hole pattern 308 is formed so that only one side of the drain wiring 305 is exposed, and then SiO 2 is formed by dry etching. ₂ The film 304 and the common source plate 303 are etched. In the present embodiment, the resist hole pattern 308 was formed using electron beam (EB) lithography, and the long side length was set to 0.2 μm and the short side length was set to 0.1 μm (FIG. 10C).
[0043]
Next, the channel polycrystalline Si film 311 and the SiO film serving as the protective film 312 are formed by the method described in the first embodiment. ₂ A film 312 is formed (FIG. 11B). In this embodiment, the thickness of the channel polycrystalline Si film 311 is 2.5 nm, ₂ The thickness of the film 312 was 7 nm. Subsequently, the SiO 2 is removed by anisotropic dry etching. ₂ The film 312 and the polycrystalline Si film 311 are etched to form the channel polycrystalline Si film 311 only on the side wall of the hole pattern 309 (FIGS. 11A and 11C).
[0044]
Next, 15 nm of SiO to be the gate insulating film 313 by the CVD method. ₂ After depositing a film 313 and a 100-nm phosphorus-doped polycrystalline Si film 314 to be a gate electrode 314, the phosphorus-doped polycrystalline film 314 is processed into a predetermined shape to form a gate electrode wiring 314 (FIGS. 12A and 12B). b)). Thereafter, source lines, data lines, and word lines are formed by the method described in the first embodiment.
[0045]
According to the present embodiment, since the sources of a plurality of memory cells are shared by using the source plate 303, the number of source lines can be significantly reduced. In addition, since the common source plate structure eliminates the step of forming a buried insulating film, the step of flattening between memory cells can be greatly simplified.
[0046]
(Example 4)
Next, a fourth embodiment of the present invention will be described with reference to FIGS. In the first embodiment, the structure in which one memory cell is arranged in one hole pattern located at the intersection of the drain wiring and the gate electrode wiring is formed. In this embodiment, two memory cells are arranged in one hole pattern. It is to arrange. That is, a common source line is disposed in the middle, and two independent drain lines are disposed above and below the common source line via an insulating film. Therefore, a structure in which two drain wirings and one source wiring are overlapped in a plane is obtained, and a cell area which is half of the structure shown in the first embodiment can be realized.
[0047]
First, a P-type (100) single crystal Si substrate 401 is thermally oxidized to form a 500 nm SiO ₂ After the film 402 is formed, a 50 nm phosphorus-doped polycrystalline Si film 403 and a 100 nm SiO ₂ Film 404, 50 nm phosphorus-doped polycrystalline Si film 405, 100 nm SiO ₂ Film 406, 80 nm phosphorus-doped polycrystalline Si film 407 and 70 nm SiO ₂ Films 408 are sequentially deposited. Next, the laminated films 403, 404, 405, 406, 407, and 408 deposited by the CVD method are processed into a predetermined shape by KrF excimer laser lithography and dry etching. As shown in FIG. 13A, the phosphorus-doped polycrystalline Si film 405 located in the middle becomes the common source wiring 405, and insulating films 404 and 406 (in this figure, SiO 2 ₂ The phosphorus-doped polycrystalline Si films 403 and 407 arranged via the films 404 and 406 become two independent data lines 403 and 407 (drain wirings 403 and 407), respectively. Hereinafter, the laminated film is referred to as a laminated wiring 410.
[0048]
Next, Si for filling the space between the stacked wirings 410 by the CVD method is used. ₃ N ₄ A film 409 is deposited to a thickness of 250 nm (FIG. 13B). Subsequently, the uppermost layer of SiO 2 ₂ The above Si is used until the surface of the film 408 is exposed. ₃ N ₄ The entire surface of the film 409 is etched back to planarize the surface (FIG. 13C).
[0049]
Next, as shown in the first embodiment, after forming a hole resist pattern 411 such that one side wall portion of the laminated wiring 410 is exposed, Si as a buried insulating film is formed. ₃ N ₄ The film 409 is etched (FIG. 14A). Subsequently, after removing the resist pattern 411, a 2.5-nm channel polycrystalline Si film 413 and a 7-nm SiO ₂ A protective film 414 is deposited. Thereafter, the SiO 2 is removed by anisotropic dry etching. ₂ The film 414 / channel polycrystalline Si film 413 is etched to form a channel polycrystalline Si film 413 only on the side wall of the hole pattern 412 (FIG. 14C).
[0050]
Next, a 15-nm SiO film serving as a gate insulating film 415 is formed by CVD. ₂ After depositing the film 415 and the phosphorus-doped polycrystalline Si film 416 of 100 nm, the gate electrode wiring 416 is formed by processing the phosphorus-doped polycrystalline Si film 416 into a predetermined shape. Subsequently, 80 nm SiO 2 was formed by CVD. ₂ After the film 417 is deposited, the source wiring 405 and the two drain wirings 403 and 407 are taken out by the method described in the first embodiment. However, in this embodiment, three contact holes 418, 419, and 420 are required for one stacked wiring 410 because there are 4051 common source lines and two drain wirings 403 and 407 (FIG. 15).
[0051]
FIG. 15A is a plan view after forming source and drain wirings, and FIG. 15B is a cross-sectional view of a memory cell portion. FIGS. 16 (a), (b), and (c) are cross-sectional views taken along the lines bb ', cc', and dd 'of the plan view of FIG. FIG. 16B shows one drain wiring 403 (the lowermost drain wiring 403), FIG. 16D shows the other drain wiring 407 (the uppermost drain wiring 407), and FIG. , The extraction portion of the common source wiring 405 (intermediate layer). As described in the first embodiment, each of the wirings 403, 405, and 407 is made of SiO which is the sidewall insulating film 421. ₂ The films 421 are insulated from each other. The wirings 403, 405, and 407 are taken out by patterning them into a predetermined shape using a phosphorus-doped polycrystalline Si film 422 formed by a CVD method, and the common source line 422 (b) and the data line 422, respectively. (A) and (c) are formed.
[0052]
In this embodiment, the connection between the gate electrode wiring 416 and the word line is not shown, but as shown in the first embodiment, only one contact hole is added and the same process as the source line and the data line is performed. Word lines can be formed.
[0053]
(Example 5)
Next, a fifth embodiment of the present invention will be described with reference to FIGS. The single-crystal Si substrate 501 is thermally oxidized to 500 nm SiO ₂ After forming the film 502, a 50 nm phosphorus-doped polycrystalline Si film 503 and a 100 nm SiO ₂ Film 504, 50 nm phosphorus-doped polycrystalline Si film 505, 50 nm Si ₃ N ₄ A film 506 and a 50 nm polycrystalline Si film 507 are sequentially deposited. Next, the laminated film 510 (503 to 507) formed by the above-mentioned CVD method is patterned by a KrF excimer laser lithography technique using a phase shift together and a dry etching method, so that a line width is 0.15 μm and an interval is 0.15 μm. (FIGS. 17A and 17B). Next, a 200 nm Si ₃ N ₄ After the film 508 is deposited, the above-described Si ₃ N ₄ The film 508 is etched back to flatten the surface (FIGS. 17A and 17C).
[0054]
Next, as shown in FIG. 18A, a hole resist pattern 509 is formed at the center of one of the adjacent stacked wirings 510. At this time, it is important to form a resist pattern 509 at a position where only one side wall of each laminated wiring 510 is exposed. In this embodiment, the EB lithography technique was applied to the formation of the resist pattern 509, and a hole pattern 509 having a short side length of 0.1 μm and a long side length of 0.2 μm was formed.
[0055]
Next, using the hole resist pattern 509 as a mask, ₃ N ₄ The film 508 is etched. The uppermost polycrystalline Si film 507 of the laminated wiring 510 is made of Si ₃ N ₄ Since the hole pattern 511 serves as a mask at the time of etching the film 508, the hole pattern 511 is formed between adjacent stacked wirings 510. ₃ N ₄ Only the film 508 is etched, and the side wall of the laminated wiring is exposed (FIG. 18).
[0056]
Next, after removing the resist pattern 509, a 2.5% dilute hydrofluoric acid aqueous solution is used to remove the SiO 2 on the side walls of the laminated wiring. ₂ The film 504 is etched and SiO 2 is formed from the side wall edge 511. ₂ The surface of the side wall of the film 504 is receded by about 30 nm. Si ₃ N ₄ Since the films 506, 508 and the polycrystalline Si films 503, 505, 507 are hardly etched by the diluted hydrofluoric acid aqueous solution, the side wall of the hole pattern 511 is ₂ Only the film 504 is etched, resulting in an overhang shape as shown in FIG.
[0057]
Next, a 2.5 nm amorphous Si film to be a channel layer 512 is deposited by a CVD method. In the present embodiment, monosilane (SiH ₄ ) Was deposited at a temperature of 480 ° C. The step coverage of the Si film deposited by thermal decomposition of monosilane is very good, and a uniform film can be formed even on an overhang-shaped base as in this embodiment (FIG. 20).
[0058]
Next, the entire surfaces of the Si films 512 and 507 are etched by an anisotropic dry etching method to remove the polycrystalline Si 507 on the uppermost layer of the laminated wiring 510 and the amorphous Si film 512 on the side wall of the hole pattern. In the anisotropic dry etching, since the lateral etching hardly progresses, over-etching was performed until the amorphous Si film 512 on the side wall of the hole pattern was removed (FIG. 21).
[0059]
FIG. 23 is an enlarged view of a section C in FIG. 21. The polycrystalline Si film 507 on the uppermost layer of the stacked wiring 510 and the amorphous Si film 512 on the side wall of the hole pattern are removed by the over-etching, but the SiO 2 is recessed from the edge of the stacked wiring 510 by hydrofluoric acid etching. ₂ The amorphous Si film 512 on the side wall of the film 504 is not etched because the polycrystalline Si film 505 serving as the drain wiring 505 becomes the eaves of the etching. Therefore, the channel Si film 512 is formed between the source 503 and the drain 505 in a self-aligned manner. As shown in the figure, the ionic species of the anisotropic dry etching are incident at an angle of 2 to 5 ° with respect to the vertical plane of the wafer. Therefore, the insulating film 504 (in this figure, SiO 2 ₂ When the film thickness of the film 504) is d and the incident angle of ions is θ, the lateral etching amount ΔX from the side wall edge is ΔX = d · tan θ. That is, if the receding length X of the insulating film is X≫ΔX, the channel film can be formed in a self-aligned manner.
[0060]
In this embodiment, SiO 2 ₂ Since the thickness of the film 504 is d = 100 nm, ΔX = 8.75 nm (θ = 5 °). Therefore, if the trench is retracted from the pattern edge by about 10 nm or more, the channel Si film 512 is not etched even if over-etching is performed (X ≒ 30 nm in this embodiment).
[0061]
Next, 15 nm of SiO to be the gate insulating film 513 by the CVD method. ₂ A film 513 and a 100-nm phosphorus-doped polycrystalline Si film 514 to be a gate electrode 514 are deposited. The amorphous Si film 512 is formed of the SiO 2 ₂ When the film 513 is deposited, it becomes a polycrystalline Si film 512. Finally, the phosphorus-doped polycrystalline Si film 514 is processed into a predetermined shape by KrF excimer laser lithography by phase shift and dry etching to form a gate wiring (FIG. 22).
[0062]
Thereafter, the source line, the data line, and the word line are connected by the method described in the first embodiment, and the formation of the single electronic element is completed.
[0063]
【The invention's effect】
ADVANTAGE OF THE INVENTION According to this invention, a single electronic element suitable for high integration with a small area, and a semiconductor memory device can be provided with high yield.
[Brief description of the drawings]
FIG. 1 is a plan view and a sectional view showing a first embodiment of the present invention.
FIG. 2 is a sectional view showing the first embodiment of the present invention.
FIG. 3 is a plan view and a cross-sectional view showing a first embodiment of the present invention.
FIG. 4 is a plan view and a sectional view showing a first embodiment of the present invention.
FIG. 5 is a plan view and a sectional view showing the first embodiment of the present invention.
FIG. 6 is a plan view and a sectional view showing the first embodiment of the present invention.
FIG. 7 is a plan view and a sectional view showing the first embodiment of the present invention.
FIG. 8 is a plan view and a sectional view showing a second embodiment of the present invention.
FIG. 9 is a plan view and a sectional view showing a second embodiment of the present invention.
FIG. 10 is a plan view and a sectional view showing a third embodiment of the present invention.
FIG. 11 is a plan view and a sectional view showing a third embodiment of the present invention.
FIG. 12 is a plan view and a sectional view showing a third embodiment of the present invention.
FIG. 13 is a sectional view showing a fourth embodiment of the present invention.
FIG. 14 is a plan view and a sectional view showing a fourth embodiment of the present invention.
FIG. 15 is a plan view and a sectional view showing a fourth embodiment of the present invention.
FIG. 16 is a plan view and a sectional view showing a fourth embodiment of the present invention.
FIG. 17 is a plan view and a sectional view showing a fifth embodiment of the present invention.
FIG. 18 is a plan view and a sectional view showing a fifth embodiment of the present invention.
FIG. 19 is a plan view and a sectional view showing a fifth embodiment of the present invention.
FIG. 20 is a plan view and a sectional view showing a fifth embodiment of the present invention.
FIG. 21 is a plan view and a sectional view showing a fifth embodiment of the present invention.
FIG. 22 is a plan view and a sectional view showing a fifth embodiment of the present invention.
FIG. 23 is a sectional view showing a fifth embodiment of the present invention.
FIG. 24 is a plan view and a cross-sectional view showing a conventional structure.
FIG. 25 is a view showing a problem of forming a channel layer on a high step.
[Explanation of symbols]
101, 201, 301, 401, 501, 601 ---- Single-crystal Si substrate
102, 202, 302, 402, 502, 602 --------------- SiO ₂ Film (Si thermal oxide film)
103, 203, 303, 405, 503, 604 (a)----------source area (source wiring)
105, 205, 305, 403, 407, 505, 604 (b) Drain region (drain wiring)
111, 211, 311, 413, 512, 605------------------poly-Si film
112, 113, 214, 312, 313, 414, 415, 513, 606, 607 --- gate insulating film
114, 215, 314, 416, 514, 608 -------- Gate electrode
213-------Fine Si particles 214----------Tunnel insulating film.

Claims (8)

Channelization Le region connected to the first conductive layer and the second conductive layer is provided, having a carrier confinement region in a region which is integrated with the channel region, by holding the carrier in said carrier confinement region, teeth in an insulated gate field effect transistor to vary the threshold voltage, it is arranged above or below the second conductive layer through the thickness of the insulating material first conductive layer corresponds to the length of the channelization Le, At least a portion of the channel region is formed on a side wall of an insulating film that insulates and separates the first conductive layer and the second conductive layer region, and the first and second conductive layers have at least a portion thereof. A semiconductor device characterized by being planarly overlapped. The semiconductor device according to claim 1, wherein a said channelization Le region thickness as polycrystalline silicon is 5nm or less. 3. The semiconductor device according to claim 1, wherein said first conductive layer or said second conductive layer is formed integrally with an adjacent first conductive layer or second conductive layer, respectively. Connected channelization Le regions are formed in the first conductive layer and the second conductive layer, the tunnel insulating film in a channel region is formed, having a carrier confinement region formed in fine particles on the tunnel insulating film a gate oxide film on said carrier confinement region is formed by holding a carrier in the carrier confinement region, the insulated gate field effect transistor to vary the threshold voltage, the first conductive layer channelization Le The second conductive layer is disposed above or below the second conductive layer via an insulator having a thickness corresponding to the length of the first conductive layer and the second conductive layer region. A semiconductor device formed on a side wall of the insulating film, wherein at least a part of the first and second conductive layers overlaps in a plane. 5. The semiconductor device according to claim 4, wherein the diameter of the fine particles and the distance between the fine particles are 10 nm or less. 5. The semiconductor device according to claim 4, wherein the fine particles are formed of silicon fine particles or silicon-germanium fine particles. Channelization Le region connected to the first conductive layer and the second conductive layer is provided, having a carrier confinement region in the vicinity of the channel region, a gate insulating film covering the carrier confinement region, the gate insulating film in an insulated gate field effect transistor having a cylindrical gate electrode, said first and second conductive layers are at least partially overlap in plan view, the first conductive layer channelization Le length covering Is disposed above or below the second conductive layer with an insulator having a thickness corresponding to that of at least a portion of the channel region formed on a side wall of the insulating film, and a layer including the channel region is A semiconductor device formed so as to surround a cylindrical gate electrode. The semiconductor device according to claim 6, the semiconductor device carrier confinement region, characterized in that formed on the outside of or are made form to be in the channel layer, or channel layer.

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