JPH08330566A - Single electronic device, and semiconductor storage device and its manufacture - Google Patents

Abstract

PURPOSE: To enable controlling the width of a very thin polycrystalline Si film by the thickness of a base insulating film, by forming an insulating film which spans a source and a drain and a thickness corresponding to the width of a channel layer, and forming the channel layer on the side wall of the insulating film. CONSTITUTION: A single electronic device has an insulating film 405 which extends between a source 404(a) and a drain 404(b) and has a thickness corresponding to the width of a channel layer. The device is constituted in the structure wherein a channel layer 407(a) or 407(b) is formed on the side wall. It is preferable that the channel layer is 10nm thick or less and the channel layer is 100nm wide or less. In this case, the base insulating film is so formed that the channel layer has an U-shaped section. By this constitution, the width of a very thin polycrystalline silicon film can be controlled with the thickness of the base insulating film, so that a width of 100nm or less can be very easily formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure of a single electronic memory using a single electronic element and a manufacturing method thereof.

[0002]

2. Description of the Related Art Single-electron devices are expected to be the ultimate highly integrated low-power devices, but there has been a major obstacle so far that they operate only at extremely low temperatures. In 1993, Hitachi's Yano et al. Succeeded in operating the single-electron device (single-electron memory) at room temperature for the first time in the world by using an ultra-thin-film polycrystalline silicon (hereinafter referred to as Si) transistor (IEEE Int.
lectron Devices Meet. 1993, pp541-544). The structure of the single electronic memory developed by Yano et al. And the outline of its operating principle will be described below with reference to FIGS. FIG. 17 is a plan view (a) and a sectional view of an ultrathin film polycrystalline Si transistor.
(b) is shown. Here, the cross sectional view shows a cross section at aa 'in the plan view. First of all, single crystal Si substrate
801 is thermally oxidized to form a 500 nm SiO ₂ film 802, and then a polycrystalline Si film 803 containing phosphorus is deposited to 100 nm by a chemical vapor deposition method (CVD method). Next, the phosphorus-doped polycrystalline film 803 is processed into a desired shape by a well-known lithography and dry etching method to form a source 803.
(a) and drain 803 (b) are formed. Then, an amorphous Si film to be the channel layer 804 is deposited to a thickness of 4 nm by the CVD method, and then heat treatment is performed in a nitrogen atmosphere at 750 ° C. to convert the amorphous Si film into a polycrystalline Si film 804. One of the key points that determines the characteristics of the ultra-thin polysilicon transistor is the film thickness of the channel poly-Si film 804 and its local non-uniformity of film thickness. Larger film thickness non-uniformity is desirable. Then the electron beam
(EB) The channel poly-Si film 804 is processed by using lithography and dry etching techniques. At this time, it is desirable that the channel polycrystalline Si width W is as small as possible,
Specifically, it is preferably about 100 nm or less. Finally, the SiO ₂ film to be the gate insulating film 805 is formed by CVD method.
After depositing a film 805 with a thickness of about 50 nm and a phosphorus-doped poly-Si 806 as a gate electrode 806 with a thickness of 100 nm, the gate electrode 806 is formed by a well-known technique, and the formation of the ultra-thin poly-Si transistor is completed.

The channel polycrystalline Si film is extremely thin (about 2 to
10nm) Ultra-thin film polycrystalline Si transistor
It exhibits different characteristics from the polycrystalline Si transistor (30 to 40 nm) used as a load element of RAM. FIG.
As shown in FIG. 8 (a), when a voltage is applied to the gate electrode, the current path of the ultra-thin film polycrystalline Si transistor follows the path with the smallest resistance, that is, the location where the film thickness of the polycrystalline Si is thick.
(Channel) is formed. This channel width is
It is about the same size as the grain size of the i-film, about 5 to 1
An extremely thin channel of 0 nm is formed. When the gate bias is further applied, the electrons are ejected from the channel, and the electrons are injected into the grain (storage node) near the channel. The electrons eliminate the potential difference between the channel and the storage node, and the electrons are confined in the storage node. This corresponds to the writing of information. In such a state (FIG. 18B), the drain current decreases due to the Coulomb repulsive force with the trapped electrons. This means that the threshold value of the transistor shifts depending on the presence or absence of electrons in the storage node, and the information (1 or 0) can be determined by measuring the threshold value. The phenomenon described above is because the channel polycrystalline Si film is extremely thin (10 nm or less) and the channel width is about 100 nm.
The following occurs under limited conditions and SR
Such a phenomenon does not occur in the polycrystalline Si transistor used as the load element of AM.

[0004]

One of the technical problems of a single-electron memory using an ultra-thin film polycrystalline Si transistor is stable channel formation. As shown in FIG. 19, when the width W of the polycrystalline Si film in which a channel is formed is large, there is a high possibility that a plurality of channels will be formed in the same layer. If a plurality of channels are blocked at the same time, no particular problem will occur, but if there are channels that are not blocked, the amount of change in the current density becomes small, making determination difficult.
Further, the smaller the capacitance related to the channel, the larger the shift amount of the threshold value. Therefore, the width of the polycrystalline Si film is preferably as small as possible. Specifically, a width of 100 nm or less is required. However, with the current lithography technology, 100
The method of patterning a thin line of nm is based on an electron beam (E
B) There is only lithography or X-ray lithography. These methods not only require a great deal of time for processing, but also have many problems in terms of reproducibility and technology, which is a bottleneck in mass production of a large-capacity memory.

An object of the present invention is to provide a single electronic device having a structure capable of easily forming a channel layer of a polycrystalline Si film having a width of 100 nm or less, a semiconductor memory device using the same, and a method of manufacturing the same. It is in.

[0006]

To achieve the above object, the single-electron device of the present invention is an insulated gate field effect transistor having a channel layer of a thin polycrystalline silicon film connected to a source and a drain. In the single-electron device of, the source (404 (a)) and the drain (4
04 (b)) and an insulating film having a thickness corresponding to the width of the channel layer (for example, an insulating film 405 having a thickness of 70 nm in FIG. 8) is provided, and the channel layer (407) is provided on the side wall thereof.
(A) or 407 (b)) is formed.

The thickness of the channel layer is 10 nm.
In the following, the width of the channel layer is preferably 100 nm or less.

Further, in this case, one feature is that the underlying insulating film is formed so that the channel layer has a U-shaped cross section.

It is preferable that the surface of the insulating film underlying the channel layer, which is in contact with the channel layer, contains nitrogen atoms to form a thin and stable channel layer.

Further alternatively, it is desirable to provide an insulating film as a protective film on the surface of the channel layer so that a good quality channel layer free from damage or contamination can be obtained.

Further, in the semiconductor memory device of the present invention for achieving the above object, a semiconductor memory device having a memory array having a plurality of data lines, word lines intersecting with the data lines, and memory elements at the intersecting positions. , The storage element is the above-described single-electron element of the present invention, and the single-electron element is connected to its source and drain to the adjacent data lines and the gate to the word line as shown in FIG. 13, for example. It shall have a configuration connected to a wire.

Here, as shown in, for example, FIG. 13 or FIG. 14, a plurality of single electronic elements connect their sources to a common data line, and adjacent data lines sandwich the common data line. It is also possible to provide a structure in which each drain is connected to the gate and each gate is connected to a common word line.

Alternatively, as shown in, for example, FIG. 15 or FIG. 16, if a plurality of sets of the plurality of single electronic elements are further provided with a common word line, a plurality of elements can be formed with the same gate electrode. Can be controlled.

Further, in the method of manufacturing a single electronic device of the present invention for achieving the above object, as a step of forming a channel layer, for example, as shown in FIG. First, a first insulating film 102 for forming a surface layer of the substrate, a second insulating film 103 having a thickness corresponding to the width of the channel layer as a base film of the channel layer, and etching from the second insulating film. A step of sequentially forming a third insulating film 104 having a slow rate, a step of processing the second and third insulating films into a predetermined shape, a side wall of the second insulating film 103 is etched, and a third step A step of forming a U-shaped cross section by retreating from the edge portion of the insulating film 104, and a step of forming a polycrystalline silicon film 105 on the insulating film as shown in FIG. c) As shown in the figure, And etching the polycrystalline silicon film 105 by Lee etching, the side walls of the second insulating film polycrystalline silicon film 105 (a), and comprise at least a step of leaving a 105 (b).

Further, as a method of manufacturing a semiconductor memory device of the present invention to achieve the above object, a memory array structure having a plurality of data lines, word lines intersecting with the data lines, and memory elements at the intersecting positions is provided. In the method of manufacturing a semiconductor memory device, the step of forming the memory element includes the step of the method of manufacturing the single electronic element of the present invention as shown in FIGS. 8 and 14, for example.

[0016]

In the structure of the single-electron device of the present invention, the structure is such that the channel layer is formed on the side wall of the insulating film having the thickness corresponding to the width of the channel layer as the underlayer for forming the channel layer. Therefore, according to the present invention, the width of the ultra-thin polycrystalline silicon film can be controlled by the film thickness of the underlying insulating film. Therefore 1
Even with a width of 00 nm or less, it can be formed extremely easily. Also, since ordinary photolithography and excimer laser lithography techniques can be applied, mass productivity is dramatically improved. In this case, regarding the formation of the channel layer on the side wall of the insulating film, in the method for manufacturing a single electronic device of the present invention, the channel layer is formed on the second insulating film, which is the base of the formation of the channel layer, with a slower etching rate. By forming the third insulating film, the second insulating film is retreated from the edge portion of the third insulating film by etching after processing these insulating films into a predetermined shape, and the U-shaped cross-sectional shape is formed. Can be easily formed. As a result, the U-shaped channel layer remains on the side wall of the underlying insulating film due to the subsequent formation of a polycrystalline silicon film on these insulating film surfaces and anisotropic dry etching, which facilitates the formation of the channel layer. Will be formed. As described above, according to the present invention, a channel layer having a width of 100 nm or less can be easily formed. Therefore, not only a single electronic element but also a semiconductor memory device using the same can be easily configured.

[0017]

【Example】

(Embodiment 1) A first embodiment of channel formation according to the present invention will be described below with reference to FIG. First, in FIG. 1 (a),
First, a P-type (100) single crystal Si substrate 101 is thermally oxidized in a water vapor atmosphere at 1000 ° C. to form a 500 nm thick SiO ₂ film 102.
After forming the film, a 100 nm SiO ₂ film 10 is formed by the CVD method.
A _{3 and 30} nm Si ₃ N ₄ film 104 is sequentially deposited. In this embodiment, the SiO ₂ film 103 is composed of monosilane (SiH ₄ ) and nitrous oxide.
(N ₂ O) was used at a temperature of 750 ° C., and the Si ₃ N ₄ film 104 was deposited at a temperature of 770 ° C. using dichlorosilane (SiH ₂ Cl ₂ ) and ammonia (NH ₃ ). Next, by the well-known photolithography and dry etching methods, the Si ₃
After the N ₄ 104 / SiO ₂ 103 laminated film was sequentially etched, 1
% Of HF aqueous solution, the side wall of the SiO ₂ film 103 is etched so as to be recessed from the pattern edge of the Si ₃ N ₄ film 104. In this case, since the etching rate of Si ₃ N ₄ 104 is slower than that of SiO ₂ 103, the side wall of the SiO ₂ film recedes from the edge portion of the Si ₃ N ₄ film by etching. In this example, a recess of about 15 nm was performed by etching.
Subsequently, as shown in FIG. 1B, a thickness of 4 n is formed by the CVD method.
After depositing the amorphous Si film of m, a heat treatment is performed in a nitrogen atmosphere at 800 ° C. to convert the amorphous Si film into a polycrystalline Si film 105. In this embodiment, monosilane is used for depositing the amorphous Si film.
The deposition was performed at a temperature of 520 ° C. using (SiH ₄ ), but it is of course possible to use disilane (Si ₂ H ₆ ). next,
In FIG. 1C, the polycrystalline Si film 105 is etched by an anisotropic dry etching method. According to anisotropic dry etching, Si ₃ since N ₄ portions has a mask layer 104 is not etched, the SiO ₂ film 103 pattern side wall, substantially SiO ₂ film thickness worth the polycrystalline Si film pattern 1
05 (a) and 105 (b) are formed. What is important in this example is that
That is, the SiO ₂ film 103 is made to recede from the pattern edge of the Si ₃ N ₄ film 104 by more than the film thickness of the ultrathin film polycrystalline Si 105. Si
If the O ₂ film 103 is not set back, that is, if the Si ₃ N ₄ film 104 is not used as a mask, the polycrystalline Si film 105 on the side wall of the SiO ₂ film 103 is also etched, and the desired width cannot be secured. This method is characterized in that a width of 100 nm or less can be formed with good controllability and that the ultrathin polycrystalline Si film 105 has a U-shaped cross section.

(Embodiment 2) Next, an embodiment of the second channel formation of the present invention will be described with reference to FIG. In FIG. 2A, a 500 nm SiO ₂ film 202, a SiO ₂ film 203, and a Si ₃ film are formed on a single crystal Si substrate 201 by the same method as in the first embodiment.
After forming the N ₄ film 204, the Si ₃ N ₄ 204 / SiO ₂ 203 laminated film is patterned. Then, the exposed side wall portion of the SiO ₂ film 203 is etched by 15 nm using a 1% HF aqueous solution. Then, in FIG. 2B, 4n is formed by the CVD method.
An amorphous Si film of m and a SiO ₂ film 206 of 10 nm are sequentially deposited (FIG. 2B). The amorphous Si film is 10 nm S
When the iO ₂ film 206 is deposited, it is converted into a polycrystalline Si film 205 depending on the temperature (750 ° C.) in the furnace. Next, referring to FIG. 2C, the SiO ₂ film 20 is formed by an anisotropic dry etching method.
6, and the polycrystalline Si film 205 are sequentially etched to obtain SiO 2.
_The polycrystalline Si film 205 is left on the side wall of the pattern of the _two films 203. According to this method, since the 10 nm SiO ₂ film 206 serves as a protective film when the polycrystalline Si film 205 is etched, it is possible to obtain a high-quality polycrystalline Si film 205 without any plasma damage or contamination. I can.

(Third Embodiment) Next, a third embodiment of the channel formation of the present invention will be described with reference to FIG. In FIG. 3A, a P-type, (100) single crystal Si substrate 301 is thermally oxidized in a water vapor atmosphere at 1000 ° C. to form a 500 nm thick SiO ₂ film.
After forming the film 302, 50 nm Si ₃ N ₄ is formed by the CVD method.
Film 303, 50 nm SiO ₂ film 304, ₃₀ nm Si ₃ N ₄ film 3
05 are sequentially deposited. Next, by the well-known photolithography and dry etching methods, the above Si ₃ N ₄ 305 / SiO _{2 is used.}
After the 304 laminated film is sequentially etched, the side wall portion of the SiO ₂ film 304 is etched with a 1% HF aqueous solution to form Si ₃
It is set back from the N ₄ film 305. In this embodiment, about 1
0 nm etching was performed. Then, heat treatment is performed for 10 minutes in an ammonia (NH ₃ ) atmosphere at 800 ° C.
The side wall of the VD-SiO ₂ film 304 film is nitrided. Next, FIG.
In (b), an amorphous Si film having a thickness of 2.5 nm is deposited by the CVD method, and then heat treatment is performed in a nitrogen atmosphere at 900 ° C. for 30 seconds using a short-time lamp annealing method to perform the amorphous Si film deposition. The film is converted to a polycrystalline Si film 306. In this embodiment, disilane (Si ₂ H ₆ ) is used to deposit the amorphous Si film at 450 ° C.
Deposition was carried out at a temperature of. Thin S deposited by CVD method
The i film has a close relationship with the nucleation density of the underlying surface, and a thin continuous film cannot be obtained on a film with a low nucleation density. In general, since the thin continuous film who deposited the Si ₃ N ₄ film on than on the SiO ₂ film obtained, SiO ₂ film as a base film of the ultra-thin Si film is not preferable. However, if thermal nitridation is performed in an ammonia atmosphere before depositing the Si film, a thin continuous film can be obtained regardless of the type of the underlying film. In this embodiment, after the patterning of the _{Si 3 N 4 305 / SiO 2} 304, it was subjected to nitriding with ammonia, SiO ₂
Similar results can be obtained by nitriding immediately after 304 deposition. On the other hand, the grain size of the polycrystalline Si film greatly differs depending on the film thickness and the crystallization method. In order to obtain a smaller grain size, it is effective to reduce the Si film thickness and to crystallize at a high temperature in a short time. The grain size of the polycrystalline Si film 306 produced in this example was 3 to 8 nm, and very fine crystal grains were obtained. Next, as shown in FIG. 3C, a CVD-SiO ₂ film 307 serving as a protective film for etching the polycrystalline Si film 306 was deposited to a thickness of 10 nm by the same method as in Example 2, and then an anisotropic dry etching method was used. The above CVD
-The SiO ₂ 307 / polycrystalline Si film 306 is sequentially etched to leave the polycrystalline Si film 306 on the side wall of the nitrided SiO ₂ film 204 pattern.

(Embodiment 4) Next, as a fourth embodiment,
Examples of ultra-thin film polycrystalline Si transistors manufactured by the methods shown in Examples 1 and 3 are shown (FIGS. 4 to 8 and 13 to 13).
(Figure 14). The manufacturing process of this embodiment is shown in FIGS.
3 shows an equivalent circuit diagram of the memory array portion of the ultra-thin film polycrystalline Si transistor prototyped in this embodiment, and FIG. 14 shows a plan layout view of the memory array portion. Figure 4,
In FIG. 14, a P-type (100) single crystal Si substrate 401 is thermally oxidized to form a 500 nm SiO ₂ film 402, and then CV is used.
The Si ₃ N ₄ film 403 having a thickness of 50 nm and the phosphorus-doped polycrystalline Si film 404 having a thickness of 70 nm containing phosphorus at a high concentration are sequentially deposited by the D method. Subsequently, the phosphorus-doped polycrystalline Si film 404 is patterned by krypton fluoride (KrF) excimer laser lithography and dry etching to form a common source line 404 (a), 601 serving as a source and a drain of the polycrystalline Si transistor. , And data line 404 (b), 602
(a) and 602 (b) are formed. In this embodiment, monosilane (Si) is deposited on the phosphorus-doped polycrystalline Si films 404, 601, 602.
Deposition was performed at a temperature of 600 ° C. using H ₄ ) and phosphine (PH ₃ ) gas. After this, S of 70 nm is formed by the CVD method.
After sequentially depositing an iO ₂ film 405 and a ₃₀ nm Si ₃ N ₄ film 406, common source lines 404 (a) and 601 and data lines 404 (b), 602 and (a) are formed.
The Si ₃ N ₄ 406 / SiO ₂ 405 laminated film is patterned so as to be orthogonal to (b).

Next, referring to FIGS. 5 and 14, the side wall of the 70 nm SiO ₂ film 405 is etched by using a 1% hydrofluoric acid aqueous solution so that about 1 from the pattern edge of the Si ₃ N ₄ film 406.
After retreating by 5 nm, heat treatment is performed in an ammonia atmosphere at 750 ° C. to nitrid the side wall portion of the SiO ₂ film 405. Then, after depositing an amorphous Si film of about 3 nm by the CVD method, a heat treatment is performed at 900 ° C. for 30 seconds by a short-time annealing method to convert the amorphous Si film into polycrystalline Si films 407 and 603. . In this example, monosilane (SiH ₄ ) was used to deposit the amorphous Si film, and the amorphous Si film was deposited at a temperature of 500 ° C.

Next, referring to FIGS. 6 and 14, the polycrystalline Si films 407 and 603 are etched by the anisotropic dry etching method. Since the portion where the Si ₃ N ₄ film 406 serves as a mask is not etched, a pattern of the polycrystalline Si film 407 having a thickness of about 3 nm and a width of about 70 nm is formed around the Si ₃ N ₄ 406 / SiO ₂ 405 laminated film. To be done.

Next, referring to FIGS. 7 and 14, after forming a photoresist pattern 408 in a predetermined shape by an excimer lithography method, an unnecessary portion of the polycrystalline Si film 407 (FIG. 7 (b) is formed by an isotropic dry etching technique). ), The both ends of the common source line 404 (a) and the data line 404 (b), which are parallel to the wiring 405, and the channel layer removal portion of FIG. 14) are etched. In this process, the polycrystalline Si film patterns 407 (a), 40
7 (b) and 603 will be individually insulated. Next, an oxygen plasma asher process is performed to remove the photoresist pattern 40.
After removing 8, the wafer surface is washed with a dilute hydrofluoric acid solution.

Next, referring to FIGS. 8 and 14, the SiO ₂ film 409 serving as the gate insulating film 409 is formed to a thickness of 20 nm by the CVD method, and the phosphorus-doped polycrystalline Si films 410 and 604 serving as the gate electrodes 410 and 604.
Is deposited to 50 nm, and then the phosphorus-doped polycrystalline Si films 410 and 604 are patterned by excimer laser lithography and dry etching to form word lines (gate electrodes).
These are 410 (a), 410 (b), and 604.

13 and 14, the common source line 60
1. For patterning the data lines 602 (a), (b) and the word lines 604, KrF excimer laser lithography and phase shift technology are applied, and lines with a minimum processing dimension of 0.16 μm (pitch 0.32 μm) Realized the space. Also,
The line width of the ultra-thin polycrystalline Si film 603 in which the channel is formed is
An optical lithographic resolution of 70 nm, which is below the resolution limit, was achieved.

(Embodiment 5) Next, FIGS.
~ The fifth embodiment of the present invention will be described with reference to Figs. 9-
12 shows the manufacturing process of this embodiment, and FIG. 15 shows an equivalent circuit diagram of the memory array portion of the ultrathin film polycrystalline Si transistor prototyped in this embodiment, and FIG. 16 shows a plan layout diagram of the memory array portion. Show. In FIG. 9, a 500 nm SiO ₂ film was formed on the single crystal Si substrate 501 by the same method as in Example 3.
Film 502, 50 nm CVD-Si ₃ N ₄ film 503, and 50 n
After forming the phosphorus-doped polycrystalline Si film 504 of m, the phosphorus-doped polycrystalline Si film 504 is patterned to form common source lines 504 (a), 701 and data lines 504 (b), 702 (a), (b). And Next, 50 nm CVD-SiO ₂ film 505, 30 nm CVD
After sequentially depositing the -Si ₃ N ₄ film _{506, Si 3 N 4 506 /} SiO 2 50
5 / Si ₃ N ₄ 503 The laminated insulating film is processed into a predetermined shape. Subsequently, the side wall portion of the SiO ₂ film 505 of the laminated insulating film is etched with a 1% hydrofluoric acid aqueous solution so as to be set back by 20 nm from the pattern edge. After this, in an ammonia atmosphere at 750 ° C, 1
A heat treatment is performed for 0 minutes to nitride the side wall portion of the SiO ₂ film 505.

Next, referring to FIG. 10 and FIG.
After depositing an amorphous Si film of 6 nm by the CVD method using the thermal decomposition of (Si ₂ H ₆ ), the amorphous Si film is oxidized by a short-time oxidation method by lamp heating to form a polycrystalline Si film. 507,
While converting to 703, a 6 nm SiO ₂ film 508 is formed. In this embodiment, the SiO ₂ film 508 is made into
It was formed in a dry oxygen atmosphere at 0 ° C. This SiO ₂ film 508
As a result, the film thickness of the polycrystalline Si films 507 and 703 is 7 at the time of deposition.
nm to 3 nm, and at the same time, the polycrystalline Si film 5
It becomes a protective film against damage and contamination due to dry etching of 07,703. Next, the SiO ₂ 508 film serving as a protective film for etching the polycrystalline Si films 507 and 703, and the polycrystalline Si films 507 and 703.
Are sequentially etched to leave the polycrystalline Si films 507 and 703 on the side wall of the nitrided SiO ₂ film 505 pattern.

Next, referring to FIGS. 11 and 16, the SiO ₂ 508 on the polycrystalline Si film 507 is treated with a 1% dilute hydrofluoric acid aqueous solution.
After removing the film, a photoresist pattern is formed into a predetermined shape by the excimer lithography method as in the fourth embodiment, and the polycrystalline Si film 50 is formed by the isotropic dry etching technique.
The unnecessary portions of 7,703 (in FIG. 11, both end portions of the common source line 504 (a) and the data line 504 (b), which are parallel to the wiring 505, and the channel layer removed portion of FIG. 16) are etched. In this step, the polycrystalline Si film patterns 507 (a), 507 (b), 703 are individually insulated.

Next, referring to FIGS. 12 and 16, the SiO ₂ film 509 serving as the gate insulating film 509 is 20 nm and the phosphorus-doped polycrystalline Si films 510 and 704 serving as the gate electrodes 510 and 704 are formed by the CVD method.
Of 50 nm thick is deposited, and then the phosphorus-doped polycrystalline Si film 510,704 is patterned by excimer laser lithography and dry etching to form word lines (gate electrodes).
It is 510,704.

As shown in FIGS. 15 and 16, one gate electrode (word line) 704 operates two independent transistors in this embodiment. That is, since the drain current is controlled by the transistor having the lower threshold value, the variation in the threshold value between the elements can be reduced as compared with the case where only one transistor is used. Further, in this embodiment, two transistors are controlled by the same gate electrode, but it is also possible to control two or more transistors. In addition, an ultra-thin film polycrystalline Si in which a channel is formed
The line width of the film 703 is 5 below the optical lithography resolution limit.
Achieved 0 nm.

[0031]

According to the single-electron device of the present invention, the width of the ultra-thin polycrystalline Si film can be controlled by the film thickness of the underlying insulating film, so that the width of 100 nm or less can be controlled very easily. Also, since ordinary photolithography and excimer laser lithography techniques can be applied, mass productivity is dramatically improved. Therefore, a semiconductor memory element using a single electronic element can be easily constructed.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of the present invention.

FIG. 2 is a sectional view showing a second embodiment of the present invention.

FIG. 3 is a sectional view showing a third embodiment of the present invention.

FIG. 4 is a plan view and a sectional view showing a fourth embodiment of the present invention.

FIG. 5 is a plan view and a cross-sectional view showing a fourth embodiment of the present invention.

FIG. 6 is a plan view and a cross-sectional view showing a fourth embodiment of the present invention.

FIG. 7 is a plan view and a cross-sectional view showing a fourth embodiment of the present invention.

FIG. 8 is a plan view and a sectional view showing a fourth embodiment of the present invention.

FIG. 9 is a plan view and a sectional view showing a fifth embodiment of the present invention.

FIG. 10 is a plan view and a cross-sectional view showing a fifth embodiment of the present invention.

FIG. 11 is a plan view and a cross-sectional view showing a fifth embodiment of the present invention.

FIG. 12 is a plan view and a sectional view showing a fifth embodiment of the present invention.

FIG. 13 is an equivalent circuit diagram of a memory array unit showing a fourth embodiment of the present invention.

FIG. 14 is a plan layout view of a memory array portion showing a fourth embodiment of the present invention.

FIG. 15 is an equivalent circuit diagram of a memory array section showing a fifth embodiment of the present invention.

FIG. 16 is a plan layout view of a memory array portion showing a fifth embodiment of the present invention.

17A and 17B are a plan view and a cross-sectional view illustrating a conventional method.

FIG. 18 is a supplementary diagram illustrating a single electronic device.

FIG. 19 is a supplementary diagram illustrating a problem of a single electronic device.

[Explanation of symbols]

101,201,301,401,501,801 ……………… Crystalline Si substrate 102,202,302,402,502,802 ……………… Si thermal oxide film 103,203,304,405,505 …………………… CVD-SiO ₂ 104,204,303,305403,406,503,506 ……… CVD-Si ₃ N ₄ 105,205,306,407,507,804… …………… Ultra thin film polycrystalline Si
(Channel layer) 409,509,805 …………………………………… Gate oxide film 410,510,604,704,806 …………………… Gate electrode (word line) 404 (a), 504 (a), 601,701,803 (a)… ……… Source (common source line) 404 (b), 504 (b), 602,702,803 (b) ………… Drain (data line)

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/66 9276-4M H01L 27/10 681B 29/78 29/78 301J

Claims (10)

[Claims] 1. A single-electron element as an insulated gate field effect transistor having a channel layer of a thin polycrystalline silicon film connected to a source and a drain, the element straddling the source and the drain and corresponding to the width of the channel layer. A single-electron device having an insulating film having a thickness that is formed on the side wall of the channel layer. 2. The single-electron element according to claim 1, wherein the channel layer has a film thickness of 10 nm or less and the channel layer has a width of 100 nm or less. 3. The single-electron element according to claim 1, wherein the channel layer has a U-shaped cross section. 4. The single-electron device according to claim 1, wherein the surface of the insulating film underlying the channel layer in contact with the channel layer contains nitrogen atoms. And a single electronic device. 5. The single-electron element according to claim 1, wherein an insulating film as a protective film is provided on the surface of the channel layer. 6. A semiconductor memory device having a memory array having a plurality of data lines, word lines intersecting with the data lines, and memory elements at the intersecting positions, wherein the memory elements are any one of claims 1 to 5. The semiconductor memory device according to any one of items 1 to 5, wherein the source and the drain of the single electronic element are connected to adjacent data lines, and the gate is connected to a word line. 7. The semiconductor memory device according to claim 6,
A plurality of single electronic devices connect their sources to a common data line, connect their drains to adjacent data lines across the common data line, and further connect their gates to a common word line. A semiconductor memory device having a configuration for connection. 8. The semiconductor memory device according to claim 7,
A semiconductor memory device, wherein a plurality of sets of the plurality of single electronic elements further have a configuration in which a word line is shared. 9. A first insulating film for forming a surface layer of the substrate on a silicon substrate, a second insulating film having a thickness corresponding to the width of the channel layer as a base film of the channel layer, and the second insulating film. The step of sequentially forming a third insulating film having an etching rate slower than that of the second insulating film, the step of processing the second and third insulating films into a predetermined shape, and the etching of the side wall of the second insulating film. A step of forming a U-shaped cross section by retreating from the edge portion of the third insulating film, a step of forming a polycrystalline silicon film on the insulating film, and a step of forming the polycrystalline film by anisotropic dry etching. A method of manufacturing a single electronic device, comprising at least a step of etching a silicon film to leave a polycrystalline silicon film on a side wall of a second insulating film. 10. A method of manufacturing a semiconductor memory device having a memory array having a plurality of data lines, word lines intersecting with the data lines, and memory elements at the intersecting positions, wherein the step of forming the memory elements comprises: 9. A method of manufacturing a semiconductor memory device, comprising the steps of the method of manufacturing a single electronic device described in 9.