JPH11150261A - Electronic function element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress dispersion of characteristics by controlling the size and the position of a region under control represented by a quantum dot, by providing at least one step difference formed at the surface side of a substrate, the region under control formed at the sidewall part of the step difference, and a control electrode which controls the current flowing in the region under control. SOLUTION: On a silicon substrate 5, a silicon layer 2 which is to become a gate through an insulating film such as a silicon oxide film 6a is machined into the intended pattern, and a step difference 7 is formed. Furthermore, arsenic ions are implanted, and the silicon layer 2 is made to be an N-type. Then, after the surface of the silicon layer 2 is covered with a silicon oxide film 6a, a silicon particle 1 is formed along the sidewall of the step difference part 7. Furthermore, when only a source/drain region is covered with resist and anisotropic etching is performed when the silicon layer is formed at the sidewall part, the source/drain region can be formed automatically. Thus, the element, whose characteristic dispersion and the like are decrease and which is suitable for integration, is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electronic functional element, and more particularly to an element utilizing a single electron tunnel effect.

[0002]

2. Description of the Related Art Silicon LSIs achieve high performance by miniaturization of semiconductor elements. However, at an integration level of 1 G or more, the problem of power consumption becomes large, and it is required to lower the power supply voltage in order to avoid the problem. This means that the number of electrons handled during operation is reduced.

[0003] Originally, a conventional device represented by CMOS has its operating principle based on controlling a statistical average of electrons, and a deviation from the average is treated as noise.
However, as the number of electrons decreases, the fluctuations become relatively large, and uniform operation of the element cannot be guaranteed. This means a limitation of integration.

[0004] Recently, elements capable of controlling electrons one by one based on a new operation principle have attracted much attention.
This element is called a single-electron tunnel element, and uses a physical phenomenon called Coulomb blockade. See, for example, “Single Charge Tunneling edited by H. Grabert and MHDevoret (Plenum, New York, 1992)” for details.
Is described in the book.

[0005] Also, a memory element utilizing the single electron tunnel effect has been proposed as a future large-capacity, ultra-low power consumption memory. For details, see, for example, “L. Gu
o et al., Tech. Dig. IEDM, p. 955, 1996 ".

Hereinafter, a memory device using the single electron tunnel effect will be briefly described with reference to FIG.
FIGS. 19A and 19B schematically show a cross-sectional configuration and a planar configuration, respectively. The structure is similar to a conventional flash memory, but the feature is that the floating gate is a quantum dot. Using the single-electron tunnel effect, electrons are transferred into and out of the quantum dots while controlling them one by one. The point where reading is performed by the MOS current is the same as that of the conventional flash memory. In other words, the threshold value of the MOSFET changes while the charge of the quantum dot 21 serving as the memory node changes, so that
The current change between the current and the solein 24 may be sensed. The writing is controlled by the upper gate electrode 22 in the same manner as in the prior art.

[0007]

As described above, an element utilizing the single electron tunnel effect is very promising as a next-generation ultra-low power consumption device. However, in order to realize the single-electron tunneling effect at room temperature, the size of the quantum dot needs to be about 10 nm or less, and it is difficult to control the size and position of the quantum dot with the conventional technology. However, there was a problem that the characteristics varied.

The present invention has been made in response to the above-mentioned conventional problems, and provides an element which can control the size and position of a controlled region represented by a quantum dot and can suppress variations in characteristics. It is intended to be.

[0009]

An electronic functional device according to the present invention comprises at least one step formed on a substrate surface side, a controlled area formed on a side wall of the step, and a control area formed on a side wall of the step. And a control electrode for controlling the flowing current.

It is preferable that the current flowing in the controlled region is controlled based on a single electron tunnel effect. According to the invention, since the controlled region is formed on the side wall of the step, the size and position of the controlled region can be defined by the step. Therefore, it is possible to reduce the variation of the current flowing in the controlled region, and to realize a fine switching element suitable for integration.

The electronic function device according to the present invention is characterized in that at least one step formed on the substrate surface side, a controlled region formed on a side wall of the step, and a charge holding state of the controlled region. And a control electrode for controlling.

It is preferable that the charge holding state of the controlled region is controlled based on a single electron tunnel effect. According to the invention, since the controlled region is formed on the side wall of the step, the size and position of the controlled region can be defined by the step. Therefore, it is possible to reduce the variation in the charge retention characteristics of the controlled region, and to realize a nonvolatile memory element suitable for integration.

In each of the above inventions, the controlled region may be formed on the side wall portion of one step, or may be formed on the side wall portion of two steps, that is, the groove. In each of the above inventions,
The controlled region is preferably constituted by at least one quantum dot or quantum wire. In this case, a switching element or a nonvolatile memory element based on a single electron tunnel effect is constituted. As a constituent material of the quantum dots or the quantum wires, a semiconductor or a conductor can be used. It should be noted that a normal MIS type semiconductor element can be formed by simply using the controlled region as a semiconductor layer instead of quantum dots or quantum wires.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 and FIG. 2 are diagrams schematically showing a plane configuration of an embodiment of the present invention. A plurality of quantum dots 1 (silicon islands) are formed on a side wall portion (step portion provided on the substrate surface) of the gate 2, and a source 3 and a drain 4 are provided at both ends. Between quantum dots or between quantum dots and source / drain,
They may be connected by a fine silicon layer as shown in FIG. 1 or may be separated by a thin insulating film as shown in FIG. 2 (the insulating film is not particularly shown (the same applies to other drawings). ), An insulating film is usually formed in gaps between quantum dots, between quantum dots and source / drain, between quantum dots and gates, and the like.) The effective tunnel barrier is defined by the micro silicon connection in the former, and is defined by the insulator in the latter. A quantum dot has a size on the order of 10 nm, and electrons move from the source side to the drain side due to a single electron tunnel effect. Further, by controlling the voltage applied to the gate electrode, a tunnel current can be made to flow or not to flow.

FIG. 3 shows another embodiment of the present invention. FIG. 3A is a diagram schematically showing a cross-sectional configuration thereof, and FIG. 3B is a diagram schematically showing a planar configuration thereof. A quantum dot 1 is formed on a side wall of a step 7 formed on the surface of a silicon substrate 5 via a silicon oxide film 6, and a gate electrode 2 is formed so as to cover the quantum dot 1. The specific element operation and the like are the same as those in FIG.

FIG. 4 is a schematic view showing an example of a method for producing a quantum dot. Hereinafter, the steps will be described step by step. First, as shown in FIG. 4A, a step 7 is formed on the surface of the silicon substrate 5 in a desired pattern. The step is, for example, 10 nm. Thereafter, the entire surface of the silicon substrate 5 is oxidized to grow a silicon oxide film 6 having a thickness of, for example, 5 nm.

Next, as shown in FIG. 4 (b) (the upper side shows a cross-sectional configuration, and the lower side shows a region where amorphous silicon 1a is formed in a planar configuration). Silicon 1a is deposited on the entire surface. The film thickness is, for example, 10 nm. Thereafter, anisotropic etching is performed to leave the amorphous silicon 1a only on the side wall of the step 7. Amorphous silicon 1a
The introduction of impurities into the semiconductor is performed as appropriate depending on the situation.

Next, as shown in FIG. 4 (c), annealing is performed in an atmosphere from which oxygen has been removed, the amorphous silicon on the side walls is granulated, and quantum dots 1 are formed along the steps. For example, it is known that if the annealing temperature is set to 1000 ° C. in an ultra-high vacuum, the silicon grains become single-crystal.

According to this manufacturing method, it is possible to form quantum dots at desired positions by defining a pattern of steps. Further, by adjusting the thickness of the step and the thickness of the amorphous silicon to the same degree, it is possible to make the size of the quantum dots uniform.

In order to facilitate the granulation, for example, KOH treatment or TMAH (Tetra Methyl A
mmonium Hydroxide) treatment is effective to facilitate the aggregation of silicon. Alternatively, it is also effective to use a deposited silicon oxide film instead of the thermal silicon oxide film to reduce the wettability with silicon and to promote the grain formation. Further, an organic insulating film may be used instead of the silicon oxide film.

Although spherical silicon particles are used as quantum dots in the present embodiment, any shape may be used as long as they are physically small in size and realize the quantum dot effect. The quantum dot grains are not limited to silicon, but may be other semiconductors such as germanium and gallium arsenide. Furthermore, it is not limited to semiconductors, and titanium,
Metals such as nickel, cobalt, tungsten, platinum, aluminum, and copper may be used, or a reaction product thereof with silicon or the like. In short, what is necessary is just to be selected from a semiconductor or a conductor.

FIG. 5 is a diagram showing a cross-sectional structure of an example of a process for manufacturing the element as shown in FIG. In this example, a so-called SOI substrate in which a silicon layer 2 serving as a gate is formed on a silicon substrate 5 via an insulating film such as a silicon oxide film 6a is used.

First, as shown in FIG. 5A, the silicon layer 2 serving as a gate is processed into a desired pattern to form a step 7, and arsenic is ion-implanted to form the silicon layer 2 into N.
Type. For example, ion implantation is performed at an acceleration condition of 30 keV and a dose of 2 × 10 ¹⁵ cm ⁻² .

Next, silicon grains are formed according to the manufacturing method described with reference to FIG. That is, as shown in FIG. 5B, after the surface of the silicon layer 2 is covered with the silicon oxide film 6b, the silicon grains 1 are formed along the side wall of the stepped portion 7.
Note that when forming the silicon layer on the side wall portion, if only the source / drain portion is covered with a resist and then anisotropic etching is performed, the source / drain region can be formed automatically.

FIG. 6 is a diagram showing a cross-sectional structure of an example of a process for manufacturing the element as shown in FIG. First, as shown in FIG. 6A, after the surface of the silicon substrate 5 is oxidized to form a silicon oxide film 6, the silicon oxide film 6 is processed into a desired pattern to form a stepped portion 7. At this time, the etching time is adjusted so that the surface of the silicon substrate 5 is not exposed.

Next, as shown in FIG.
The silicon grains 1 are formed along. The production of the silicon particles 1 may be performed according to the method described with reference to FIG. At this time,
As described with reference to FIG. 5, when forming the silicon layer on the side wall portion, if only the source / drain portion is covered with the resist and then anisotropic etching is performed, the source / drain region can be formed automatically. it can.

Next, as shown in FIG. 6C, N-type polycrystalline silicon is deposited by an LPCVD method or the like via an insulating film such as a silicon oxide film, and processed into a desired pattern to form a gate electrode. Form 2

FIGS. 7 and 8 are diagrams schematically showing the plan configuration of another embodiment of the present invention. In this example, unlike the examples shown in FIG. 1 and the like, the silicon formed in the step is not granulated and is used as the quantum wires 8. The gate 2 may have a structure as shown in FIG. 7 (a structure corresponding to FIGS. 1 and 5) or a structure as shown in FIG. 8 (a structure corresponding to FIGS. 3 and 6). Is also good. The quantum wires 8 can be manufactured by performing the steps up to FIG. As a material of the quantum wire, a semiconductor or a conductor can be used as in the case of the quantum dots described above.

FIG. 9 is a diagram showing a modified example of the quantum wires 8. That is, a desired region of the silicon layer 8 (quantum fine wire) is removed, and the removed region functions as a tunnel barrier of a single electronic device. FIG. 3A shows a silicon layer 8 divided symmetrically in the source / drain direction, FIG. 3B shows an asymmetrical division, and FIG. 3C shows a plurality of silicon islands formed.

FIG. 10 is a view showing still another modification of the quantum wire 8. Unlike the structure of FIG. 9, the silicon layer 8 is not completely divided, and only a part thereof is removed. Adjusting the etching time enables such partial removal. This removed region also acts as a tunnel barrier for a single electronic device. FIG. 3A shows a configuration in which the silicon layer 8 is symmetrical, and FIGS. 3B and 3C show an asymmetric configuration.

FIG. 11 is a diagram schematically showing a plane configuration of another embodiment of the present invention. In this example, an auxiliary gate (side gate) 9 is further provided in the structure of FIG. For integration of a single electron tunneling device, phase variation of Coulomb oscillation is of great concern. By adjusting the auxiliary gate with the structure shown in FIG. 11, the phase of Coulomb oscillation can be controlled. As a result, there is no phase variation,
A single electronic device suitable for integration can be realized. Of course,
Needless to say, an auxiliary gate can be appropriately added to the various element structures described above.

FIG. 12A is a schematic diagram showing an example when an inverter is formed using a single electron tunnel element. Two single electron tunneling elements shown in FIG. 1 and the like are connected in series. For easy understanding of the structure, the gate region G and the source / drain regions S / D described above are shown separately. Quantum dots are formed on both side walls of the step defined by the central gate. Apart from the central main gate, each single-electron tunneling element is provided with an auxiliary gate, a terminal represented by Vss is connected to a ground line, and a terminal represented by Vdd is connected to a power supply line. FIG. 12B shows the characteristics of the inverter shown in FIG. 12A, and a voltage opposite to the input Vin is taken out as the output Vout. The inverter circuit is the basis of the logic circuit, and the basic circuit can be realized compactly as shown in FIG. Of course,
It goes without saying that an inverter circuit can be configured using the various element structures described above.

FIG. 13 is a schematic view showing an example of a method of manufacturing a quantum dot according to another embodiment of the present invention. Hereinafter, the steps will be described step by step. First, FIG.
As shown in FIG. 3A, after a groove having a step 7 is formed on the surface of the silicon substrate 5, the surface is oxidized to form a silicon oxide film 6.

Next, as shown in FIG. 13 (b) (the upper side shows a cross-sectional configuration, the lower side shows a region where the amorphous silicon 1a is formed in a planar configuration). Is filled with amorphous silicon 1a. For example, a resist etch back method is effective. Alternatively, the thickness of the amorphous silicon may be adjusted, and the trench may be filled with the amorphous silicon in the manner of leaving the side walls.

Next, as shown in FIG. 13C, the silicon is granulated by annealing in an ultrahigh vacuum to form quantum dots 1. In this way, quantum dots having a uniform size and the like are formed along the grooves.

FIG. 14 shows another embodiment of the present invention.
FIG. 1A schematically shows a cross-sectional configuration thereof, and FIG. 1B schematically shows a planar configuration thereof. Although quantum dots are provided on the side wall of the step as in the past, in the present embodiment, the quantum dot 1 formed on the step 7 via the silicon oxide film 6 is used as a floating gate. Further, a gate electrode 2 as a control gate is provided on a side portion thereof via an insulating film. That is, the device functions as a nonvolatile memory element using the single electron tunnel effect, and the memory state is represented by the presence or absence of the charge of the quantum dot 1. Note that the channel is formed between the source 3 and the drain 4 along the step of the semiconductor substrate 5. Quantum dot 1
May be manufactured in the same manner as the method shown in FIG. 4. The gate electrode 2 may be manufactured by depositing an electrode material and leaving it only on the side wall by anisotropic etching or the like.

FIG. 15 shows another example of a memory device utilizing the single electron tunnel effect. As in the example of FIG. 14, the quantum dot 1 is used as a floating gate. In this example, a quantum wire 10 formed on a side portion of a quantum dot 1 via a predetermined insulating film is used as a channel, and a source 3 and a drain 4 are provided at both ends of the quantum wire 10. The gate electrode 2 forming the step 7 is used as a control gate.

FIG. 16 shows still another example of the memory device utilizing the single electron tunnel effect. As in the example of FIG. 14, the quantum dot 1 is used as a floating gate. However, unlike the structure of FIG.
Are formed so as to cover the quantum dots. The function as a single electronic memory is the same as in the example of FIG.

FIG. 17 is a diagram for explaining the operation and the like of the nonvolatile memory element shown in FIG. 14 and the like.
Is a diagram schematically showing a planar configuration of the element, and FIG. 4B is a diagram showing a memory state of the ternary memory.

First, the binary memory operation will be described.
The state in which electrons are not occupied in the quantum dot 1 and the state in which electrons are occupied are used as a binary memory. Writing is performed by giving an appropriate voltage to the control gate 2 and exchanging electrons with the quantum dot 1, and reading is performed by sensing a current flowing through the channel.

Next, application to a ternary memory will be described. As shown in FIG. 17B (in the figure, the hatched dots are occupied by electrons), the state in which neither of the two quantum dots is occupied by electrons is “0”, and the drain side The state in which electrons are occupied only by the quantum dots is “1”, and the state in which electrons are occupied by both quantum dots is “2”. A memory operation is performed using these three values. Writing "1" is performed by hot electron injection. That is, an appropriate voltage is applied to the gate and the drain to cause impact ionization near the drain, and hot electrons generated near the drain are injected into the quantum dots. Under this condition, hot electron injection is not performed near the source. The writing of “0” and “2” is the same as in the case of the binary memory. The same applies to the case where reading is performed using a channel current.

Although two quantum dot systems have been described here for simplicity, the present invention can be applied to a larger number of quantum dot systems. In this case, hot electron injection is performed on a group of quantum dots around the drain.

FIG. 18 is a diagram showing an operation and the like when a higher-order multi-valued memory is configured by applying the operation principle described in FIG. The writing of “1” corresponds to 3 in FIG.
As in the case of the value, hot electrons generated near the drain are injected into the quantum dots. The writing of “2” is performed by repeating hot electron injection near the source and near the drain. The writing of “0” and “3” is the same as in the case of the binary memory.

Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and can be variously modified and implemented without departing from the gist thereof.

[0045]

According to the present invention, since the controlled region is formed on the side wall of the step, the size and position of the controlled region can be defined by the step. Therefore, it is possible to realize an element suitable for integration with reduced variation in characteristics and the like.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an embodiment of the present invention, and is a diagram illustrating a switching element using a single electron tunnel effect.

FIG. 2 is a diagram showing a modification example of FIG. 1;

FIG. 3 is a diagram showing another embodiment of the present invention, and is a diagram showing a switching element using a single electron tunnel effect.

FIG. 4 is a diagram illustrating an example of a manufacturing process of a quantum dot according to an embodiment of the present invention.

FIG. 5 is a diagram showing an example of a manufacturing process of an element structure corresponding to FIG.

FIG. 6 is a diagram showing an example of a manufacturing process of an element structure corresponding to FIG.

FIG. 7 is a diagram showing another embodiment of the present invention, and is a diagram showing a switching element using a single electron tunnel effect.

FIG. 8 is a diagram showing a modification of FIG. 7;

FIG. 9 is a diagram showing a modification example of FIG. 7;

FIG. 10 is a diagram showing a modification example of FIG. 7;

FIG. 11 is a view showing another embodiment of the present invention, and is a view showing a switching element using a single electron tunnel effect.

FIG. 12 is a diagram illustrating an example of a case where an inverter is configured by a switching element using a single electron tunnel effect.

FIG. 13 is a diagram showing another embodiment of the present invention, and is a diagram showing a switching element using a single electron tunnel effect.

FIG. 14 is a view showing another embodiment of the present invention, and is a view showing a nonvolatile memory element using a single electron tunnel effect.

FIG. 15 is a view showing another embodiment of the present invention, and is a view showing a nonvolatile memory element using a single electron tunnel effect.

FIG. 16 is a view showing another embodiment of the present invention, and is a view showing a nonvolatile memory element using a single electron tunnel effect.

FIG. 17 is a diagram showing a configuration and an operation of a nonvolatile memory element using a single electron tunnel effect in a case where there are two quantum dots.

FIG. 18 is a diagram showing a configuration and an operation of a nonvolatile memory element using a single electron tunnel effect in a case where there are three quantum dots.

FIG. 19 is a diagram showing an element using a single electron tunnel effect according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Quantum dot 2 ... Gate 3 ... Source 4 ... Drain 5 ... Silicon substrate 6 ... Insulating film 7 ... Step 8, 10 ... Quantum fine wire 9 ... Auxiliary gate

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (5)

[Claims] At least one step formed on a substrate surface side, a controlled region formed on a side wall of the step, and
An electronic function element comprising: a control electrode for controlling a current flowing through the controlled region. 2. The electronic functional device according to claim 1, wherein a current flowing through the controlled region is controlled based on a single electron tunnel effect. 3. At least one step formed on the substrate surface side, and a controlled region formed on a side wall of the step.
An electronic functional element comprising: a control electrode for controlling the state of charge retention in the controlled region. 4. The electronic function device according to claim 3, wherein the charge holding state of the controlled region is controlled based on a single electron tunnel effect. 5. The electronic function device according to claim 1, wherein the controlled region is constituted by at least one quantum dot or quantum wire.