JPH07307445A - Semiconductor storage device and its production - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage device which necessitates no refreshing and operates even at room temperature and low voltage by utilizing a Coulomb barrier. CONSTITUTION:A first electrode 3 formed with a gate oxide film 2 interposed and a capacity C having a fine tunnel joint row that is formed on the side wall of the first electrode by forming a tunnel oxide film 5, gate electrode 6, tunnel oxide film 7, and gate electrode 8 alternately are constructed on a semiconductor substrate 1. On the other hand, a fine gate capacity Cg is formed of the gate electrode 8, oxide film 9 and second electrode 10 on the side wall. Further, a source/drain 11 is formed in a manner to be self-aligned with the gate electrodes 6 and 8, so that the gate electrode 8 may operate as a memory node for connecting the C and Cg and at the same time a memory cell utilizing Coulomb barrier that can operate as a gate for reading MOS transistor can be constructed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a semiconductor memory device that does not require refresh and operates at room temperature utilizing the Coulomb shielding phenomenon.

[0002]

2. Description of the Related Art D, which is a typical conventional semiconductor memory device
In RAM and flash memory, if the memory cells are miniaturized in order to realize the integration degree of 1 gigabit or more on one chip, the statistical fluctuation of the number of electrons becomes a size that cannot be ignored, and the storage device Operation becomes difficult. In addition, since electric charge flows out from the storage capacitor portion in the DRAM, there is a problem that power consumption becomes large because an operation of periodically rewriting to hold the memory, that is, refreshing is required, and thus the flash memory cannot be refreshed. Although it is unnecessary, there is a drawback that random access is not possible because only batch deletion is possible.

On the other hand, in a memory utilizing Coulomb shielding, the number of electrons can be controlled in units of one, and in principle, the memory unit can be one electron,
It is possible to realize a semiconductor memory device that is much more highly integrated than a DRAM or a flash memory. For the basic concept of the memory using the Coulomb shield, see, for example, Single Charge Tunneling, Edited by H. Grabertand, Chapter 9, pp. 313 to 317 of "Single Charge Tunneling" by Graber and Debole.
MH Devoret, Plenum Press, New York, 1992, Chap
ter 9).

By utilizing this Coulomb shielding, it is possible to suppress fluctuations in the number of electrons, which is considered to be an indispensable condition in the case of further miniaturization of memory cells in the future. Moreover, the memory using Coulomb shielding can realize a single electronic memory that can be randomly accessed and in principle does not require refreshing, so it is a semiconductor memory that can achieve higher integration with lower power consumption than DRAM and flash memory. Expected as a device.

An example of experimental verification of a memory using Coulomb shielding, which is expected to have such advantages, is described in Electronics Letters Vol.
29, No. 4 (Electronics Letters, 18th Feb. 199
3, Vol.29, No.4,). In this verification example, a GaAs substrate of a delta-doped structure having a steep impurity concentration distribution is used to form a memory cell utilizing Coulomb shielding in a two-dimensional plane, and this semiconductor memory device operates as a memory at a cryogenic temperature of 30 mK. Was shown.

[0006]

However, according to the experimental verification example of the memory utilizing the Coulomb shielding described above, since the GaAs substrate of the delta-doped structure is used to form the memory cell in the two-dimensional plane. As a result, the electrode corresponding to the storage node of the memory cell is laid out in a two-dimensional plane, and it is difficult to reduce the capacity of the storage node. As a result, the operating temperature of the memory device is as low as 30 mK, and even if the miniaturization is advanced, the capacity of the memory node cannot be reduced, so that there is a problem that the operation at room temperature cannot be expected. Further, since it is a process using a special substrate such as a GaAs substrate having a delta-doped structure, there are problems in terms of manufacturing cost and mass productivity.

Therefore, an object of the present invention is to use a silicon LSI process which is advantageous in terms of manufacturing cost and mass productivity, is a low power consumption type that can operate at room temperature using Coulomb shielding, and does not require refreshing. A semiconductor memory device and a method for manufacturing the same are provided.

In addition, in order to achieve ultra-high integration density,
The challenge is to realize stable operation that is not affected by statistical fluctuations in the number of electrons even when forming extremely fine elements.

[0009]

In a semiconductor memory device according to the present invention, a tunnel junction string MTJ including at least one tunnel junction, a capacitor Cg connected in series with the tunnel junction string, and this capacitor and the tunnel junction. In a semiconductor memory device having a connection node with a column as a storage node MN, a semiconductor substrate of the first conductivity type, that is, a p-type substrate 1 in the first embodiment.
A first electrode 3 formed over the insulating film, a plurality of electrodes 6, 8 connected in series to the first electrode through the insulating film 5 and insulated from each other by an insulating film 7, The tunnel junction array MTJ composed of a plurality of electrodes and a second electrode 10 connected via an insulating film 9 and the capacitance Cg, and at least a storage node in the plurality of electrodes 6, 8. It is characterized in that it has a read transistor Q ₁ constituted by a pair of second conductivity type impurity layers 11 formed in the semiconductor substrate 1 in a self-aligning manner with respect to the electrode 8 to be formed.

In the above semiconductor memory device, at least one of the plurality of insulating films existing between the first electrode and the second electrode via the plurality of electrodes has a thickness capable of quantum mechanical tunneling of electrons. That is, it is preferable to use an insulating film having a thickness of at most 5 nm and at least one insulating film having a thickness that does not allow quantum mechanical tunneling of electrons.

It is preferable that the plurality of electrodes are located on the side wall side of the first electrode and the insulating film for insulating the plurality of electrodes from each other is a side wall insulating film formed on each electrode.

Further, if the areas of the electrodes facing each other of the first electrode and the plurality of electrodes are at most 1000 square nanometers, the charging energy determined by the capacity of the electrode serving as the storage node is determined by the thermal energy determined by the temperature. Can be greater than.

Further, the potential of the electrode serving as a storage node among the plurality of electrodes has hysteresis with respect to the potential applied between the first and second electrodes, whereby the first
And the potential applied between the second electrodes allows the potential of the electrode serving as the storage node to have two stable values,
Therefore, it is preferable to set the threshold voltage of the read transistor to a voltage value between two stable potentials that can be taken by the electrode serving as the storage node.

As described above, in the semiconductor memory device according to the present invention, the tunnels connected in series by controlling the thickness of the insulating film between the plurality of gate electrodes formed on the semiconductor substrate via the insulating film. By utilizing the fact that the junction array MTJ and the capacitance Cg are realized, and the electric potential of the portion sandwiched between the tunnel junction array and the capacitance has two stable values due to Coulomb shielding, a portion that can take these two values, that is, a memory Node M
N is used as the gate electrode of the data read transistor Q ₁ .

A method of manufacturing a semiconductor memory device according to the present invention comprises a step 1 of forming a gate oxide film 2 on a surface of a semiconductor substrate 1 of a first conductivity type including an element isolation oxide film 12, and a step 1 on the gate oxide film. Step 1 of forming a first conductive film, that is, phosphorus-doped polycrystalline silicon, Step 3 of forming an insulating film on the first conductive film, and patterning the first conductive film and the insulating film to form an upper surface of the insulating film. Step 4 of forming a first electrode 3 on the surface, and Step 5 of forming a first insulating film, ie, a tunnel oxide film 5 having a thickness capable of tunneling electrons, on the surface.
And a step 6 of forming a second conductive film, that is, phosphorus-doped polycrystalline silicon 6 on the side wall of the first electrode 3 through the first insulating film, and a second insulating film having a thickness capable of tunneling electrons, that is, Step 7 of forming a tunnel oxide film 7 on the surface, and further step of forming a third conductive film, that is, phosphorus-doped polycrystalline silicon 8 on the side wall side of the first electrode through the second insulating film formed in Step 7. 8, the step 7 and the step 8 are sequentially repeated a required number of times, and then a step 9 of forming on the surface a third insulating film, that is, an oxide film 9 having a thickness that makes electron tunneling impossible, and a step of forming a second electrode. 4, the step 10 of forming the conductive film, that is, the phosphorus-doped polycrystalline silicon 10 on the surface, and the insulating film and the conductive film formed in step 10, step 9, step 8, step 7, and step 6, leaving the required portions. Step 11 of removing and the second guide Characterized by a step 12 formed in a self-aligned manner a drain 11 types of impurities i.e. n-type impurity with respect to the predetermined position in the first conductivity type semiconductor substrate.

Alternatively, Step 1 of forming a gate oxide film on the surface of the first conductivity type semiconductor substrate including the element isolation oxide film,
Step 2 of forming a first conductive film on the gate oxide film, Step 3 of forming an insulating film on the first conductive film, and patterning the first conductive film and the insulating film to form an upper surface of the insulating film. Step 4 of forming a first electrode on the surface, step 5 of forming a first insulating film having a thickness capable of tunneling electrons on the surface, and forming a second conductive film through the first insulating film. Step 6 of forming on the side wall of one electrode, Step 7 of forming on the surface a second insulating film having a thickness capable of tunneling electrons, and further, the first electrode via the second insulating film formed in Step 7. 8 for forming a third conductive film on the side wall of the substrate, step 9 for forming a resist pattern at a required portion after repeating steps 7 and 8 a required number of times in sequence, and a mask for the resist pattern formed in step 9 The conductive film and the insulating film formed in steps 8, 7 and 6 are removed. And a step 11 of forming an impurity of the second conductivity type in the semiconductor substrate of the first conductivity type in a self-aligned manner with respect to the required portion using the resist pattern as a mask, and after removing the resist pattern, the surface Step 12 of forming a third insulating film having a thickness that makes it impossible to tunnel electrons, and Step 13 of further forming a fourth conductive film on the surface
And a step 14 of patterning the fourth conductive film formed in step 13 to form a second electrode.

[0017]

The first electrode formed on the semiconductor substrate of the first conductivity type via the insulating film, and the plurality of electrodes connected in series to the first electrode via the insulating film and insulated from each other by the insulating film. The electrode and the second electrode connected to the plurality of electrodes through the insulating film are composed of the tunnel junction array MTJ and the gate capacitance C.
g in series connection. The pair of second-conductivity-type impurity layers formed in the first-conductivity-type semiconductor substrate in a self-alignment manner with respect to at least the electrode serving as the storage node MN among the plurality of electrodes are the source / drain of the read transistor. Becomes Moreover, the gate of this read transistor functions as a storage node MN using Coulomb shielding.

The plurality of insulating films existing between the first electrode and the second electrode via the plurality of electrodes have a thickness of at least 5 nm, so that quantum tunneling of electrons can be achieved. It becomes possible, and by making the thickness of the insulating film thicker than this, quantum mechanical tunneling of electrons becomes impossible. Therefore, the portions insulated from each other by the tunnelable thin insulating film form the tunnel junction array MTJ, and the portions insulated by the thick insulating film form the gate capacitance Cg.

Further, the plurality of electrodes are located on the side wall side of the first electrode, and the insulating film for insulating the plurality of electrodes from each other is a side wall insulating film formed on each electrode. The area of the electrodes facing each other and the plurality of electrodes can be formed in a very small area of at most 1000 square nanometers, and as described later, the charging energy determined by the capacitance of the electrode serving as the storage node is Can be made larger than the heat energy determined by. As a result, it becomes possible to operate the memory at room temperature by utilizing the Coulomb shielding.

Furthermore, since the potential of the electrode serving as the storage node MN has hysteresis with respect to the potential applied between the first and second electrodes, the potential of the storage node can have two stable values. By setting the threshold voltage of the reading transistor to a voltage value between these two stable potentials, binary memory operation becomes possible.

Here, the operating principle of the Coulomb shield used in the semiconductor memory device according to the present invention will be described. Figure 3
3A and 3B are diagrams for explaining the principle of Coulomb shielding, and consider a tunnel junction connected to a constant current source I as shown in the equivalent circuit of FIG. FIG. 3B is a characteristic diagram showing the relationship between the accumulated charge Q of the capacitance C of this tunnel junction and the charging energy. Here, the tunnel junction means a junction in which electrons can move with a certain probability. Assuming that the accumulated charge Q of the tunnel junction is 0 in the initial state, as shown in (b) of FIG. 3, the accumulated charge increases as time passes by the constant current source I, and at the same time, the accumulated charge increases. The charging energy Q ² / 2C of the tunnel junction also increases. When the accumulated charge reaches the point b of 0.5e and tries to exceed it, one electron tunnels, the state moves from the point b to the point c, and the accumulated charge Q accumulated in the tunnel junction is −0.
5e. This is because the tunneling of one electron can reduce the charging energy of the entire system. The value of this accumulated charge Q ± 0.5e is
It is obtained as a point where there is no difference in charging energy before and after one electron tunnels, that is, a critical point where the charging energy is equal before and after the tunnel.

Again, the accumulated current Q increases with the passage of time due to the constant current source I, but electron tunneling does not occur until the point b is reached. This means that the accumulated charge Q is -0.5.
Between e and 0.5e, whichever direction the electron tunnels in, the charge energy after tunneling is greater than the charge energy before tunneling, which violates the law of nature and therefore The electron tunnel cannot occur until the point b is reached. That is, no electron tunnel occurs when the accumulated charge Q is between −0.5e and 0.5e. The state in which this electron tunnel is prohibited is called Coulomb shielding. Therefore, in the following range,
Even individual tunnels will be completely banned.

[0023]

[Equation 1]

Of course, when the temperature is high, fluctuations in electron energy occur due to thermal energy, and the Coulomb shielding state is broken, so that electrons can be tunneled. Therefore, for the Coulomb shielding to occur, the capacitance C of the tunnel junction is sufficiently small, that is, the charging energy Q ² /
The condition is that 2C is larger than thermal energy.

The above is when the external impedance seen from the tunnel junction is infinite. That is, the above equation (1) is the case shown in FIG. 4A, which is the range of Coulomb shielding obtained by comparing the charging energy due to the accumulated charge of the tunnel junction before and after the tunnel. Since the external impedance is finite in an actual system, redistribution of electrons occurs after one electron tunnels. If the external impedance is represented by the capacitance value C _ext , after one electron tunnels, the accumulated charge in the tunnel junction is Q−e · C as shown in FIG.
/ (C + C _ext ). Therefore, by comparing the charging energies before and after the tunnel, the Coulomb shielding range is as follows.

[0026]

[Equation 2]

On the other hand, in the case of a tunnel junction connected to a constant voltage source, the external impedance may be considered to be 0, that is, C _ext = ∞, and therefore, the range of Coulomb shielding does not exist from the equation (2), so the Coulomb shielding is It will not happen.

FIG. 5 shows a conceptual diagram of a memory using this Coulomb shield. In FIG. 5, reference numeral MTJ indicates a tunnel junction array, and the tunnel junction array MTJ is composed of N tunnel junctions. The tunnel junction string MTJ and the gate capacitance Cg are connected in series to form a tunnel junction string MTJ.
Between the gate and the gate capacitance Cg (this electrode is connected to the storage node M
Call it N. ) Is connected to the sense amplifier SA. The gate capacitance Cg is the capacitance between the storage node MN and the gate electrode, and is the capacitance Cs connected to the storage node MN.
Is the capacitance with the peripheral electrodes, so-called parasitic capacitance.

The operation principle of the memory using the Coulomb shield thus constructed will be described below. The operating principle is a detailed description of the contents described in the experimental verification example of the memory using the Coulomb shielding described above.
The capacity of a single tunnel junction NC, i.e. the total capacity of the tunnel junction sequence MTJ is C, when the external impedance viewed from one tunnel junctions connected to the storage node MN and C _ext relational expression as follows The equation (3) representing the critical charge amount Qc is established.

[0030]

[Equation 3]

Here, the critical charge amount Qc means the charge amount when the Coulomb shielding cannot be maintained and electron tunneling occurs. That is, the range of Coulomb shielding is represented by the critical charge amount Qc as follows.

[0032]

[Equation 4]

If the potential and the number of electrons at the storage node MN are V and n, and the gate potential is Vg, the charge ne
The following equation holds for.

[0034]

[Equation 5]

Therefore, the potential V at the storage node MN is expressed by the following equation.

[0036]

[Equation 6]

Using the equation (6) with the number of electrons n in the storage node MN as a parameter, the potential V in the storage node
Is plotted against Cg · Vg / e is a broken line in FIG. In the same figure, the range of Coulomb shielding shown by the equation (4) is also shown. The meaning of Coulomb shielding is that the number of electrons n in the storage node MN does not change even if the gate potential Vg changes in the range of Coulomb shielding.

Consider now how the potential V at the storage node MN changes when the gate voltage Vg is changed. When the gate voltage Vg is 0 volt, the storage node M
It is assumed that the potential V of N is 0 volt (a in FIG. 6).
point). When the gate voltage Vg is increased from this state, since it is within the Coulomb shielding range, the potential V of the storage node MN continuously increases while the number of electrons n remains 0. When reaching the point b, one electron tunnels, the potential V of the storage node MN becomes the point c on the broken line of n = 1, and the number of electrons n
With 1 remaining 1, the state of shielding Coulomb will be resumed. When the gate voltage Vg is further increased to reach point d, one electron tunnels again and the potential V of the storage node MN is n = 2.
The state becomes the point e on the broken line. When the gate voltage Vg is decreased from the state at the point e, the number V of electrons remains unchanged at 2 and the potential V of the storage node MN continuously decreases because it is within the Coulomb shielding range. When reaching the point f, one electron tunnels in the opposite direction, and the potential V of the storage node MN becomes n.
It is point g on the broken line of = 1.

As a result, when the gate voltage Vg is changed periodically, the potential V of the storage node MN has a hysteresis as shown by the thick solid line in FIG. For example, when the gate voltage Vg is 0 volt, the storage node MN
Potential V has two stable points indicated by white circles. Therefore, by setting the threshold voltage of the data reading transistor whose gate electrode is connected to the storage node MN between these two stable points, the data reading transistor when the potential of the storage node MN is “high”. A current flows through, while no current flows when it is "low", and data can be read. Thus, a memory using Coulomb shielding is possible in principle.

As can be seen from this principle, the storage node M
In order for the potential V of N to have hysteresis, at least two or more states must exist within the Coulomb shielding range when the gate voltage Vg is 0 volt as shown in FIG. More specifically, in equation (6),
The value Qc / C obtained from the equation (3) must be larger than the value (corresponding to the intersection with the vertical axis) when n = −1 and the gate voltage is 0 volt. Therefore, the condition of the following equation must be satisfied.

[0041]

[Equation 7]

The expression (7) is a condition for the memory operation. In addition, the most important thing when actually operating the memory using this principle is how Cg + C + Cs
Is to realize a small system. This is because, as already described under the condition where Coulomb shielding occurs, the larger the charging energy determined by the total capacitance Cg + C + Cs, the larger the thermal energy that can be operated. This is because the operating temperature can be raised.

When a memory using Coulomb shielding is realized by using silicon, there are two possible methods for forming the storage node MN. There are a case of using the inversion layer formed on the substrate surface by the gate electrode and a case of using the gate electrode itself. These will be described below.

FIG. 7 shows a conceptual diagram when the inversion layer is used as a storage node. (1) of FIG. 7 is a schematic (a) cross-sectional structure diagram and (b) equivalent circuit diagram of a storage node using an inversion layer, and (2) shows a configuration for extracting the potential of this storage node ( 3A is a cross-sectional structure diagram, and FIG. 3B is an equivalent circuit diagram. The inversion layer 23 formed on the surface of the substrate 20 by the gate voltage Vg applied to the gate electrode 22 and the diffusion layer 2
The area between 1 and 1 becomes the capacity C of the tunnel junction, and the portion sandwiched between the inversion layer 23 and the gate electrode 22 becomes the capacity Cg of the tunnel junction connected in series. Therefore, based on the operating principle of the memory using the Coulomb shield, the potential of the inversion layer 23 formed immediately below the gate electrode 22 has two stable values. As a structure for taking out this potential, it can be taken out by the wiring 25 via the diffusion layer 24 as shown in FIG. 7B. This wiring 25
For example, as shown in the broken line of the equivalent circuit, a normal MOS
Data can be read out by connecting to the gate electrode of, but this method has a drawback that the parasitic capacitance Cs becomes large as a result of routing the wiring 25.

FIG. 8 shows another conceptual diagram when the inversion layer is used as a storage node. 8A is a schematic cross-sectional structure diagram, and FIG. 8B is an equivalent circuit diagram thereof. When the inversion layer formed by the gate voltage applied to the gate electrode is used as a storage node, the tunnel junction is formed as shown in FIG.
Instead of the diffusion layer 21 shown in FIG. 8, the gate voltage Vg1 applied to the first gate electrode 32 as shown in FIG.
The inversion layer 34 formed on the surface of the substrate 30 can be used. In this case, the first gate electrode 32 and the second gate electrode 32
Respective gate voltages Vg1 and Vg2 of the gate electrode 33
The capacitance C of the tunnel junction is formed between the inversion layers 34 and 35 formed by the inversion layer 35 and the second gate electrode 33.
The portion sandwiched between the two becomes the gate capacitance Cg connected in series with the tunnel junction. Therefore, in this case, the capacitance C of the tunnel junction can be made smaller than that of the configuration shown in FIG. Since the reading from the storage node is performed in the same manner as in the case of (2) in FIG. 7, as a result of routing the wiring, the parasitic capacitance Cs is about the same.

On the other hand, when the gate electrode itself is used as a memory node, that is, in the case of the semiconductor memory device according to the present invention, a concrete sectional structure view and a bird's-eye view are shown in FIG.
(A) and (b), and its equivalent circuit is shown in FIG.
As shown in FIG. 1A, a first substrate is formed on the silicon substrate 1.
The first electrode 3 via the gate oxide film 2, the gate electrodes 6 and 8 insulated from each other on the side wall of the first electrode 3 by the oxide films 5 and 7, and the thick oxide film on the side wall of the gate electrode 8. The second electrode 10 is formed via 9. Source / drain diffusion is self-aligned as shown in FIG. 1B with respect to at least the electrode 8 serving as a storage node (with respect to the electrode 8 and the electrode 6 in this figure) among the plurality of electrodes. The layer 11 is formed. In FIG. 1B, only the source is shown, and the drain is not shown although it is on the back side with respect to the paper surface. Similarly, the oxide films 7 and 9, the gate electrodes 6 and 8, the second electrode 10 and the diffusion layer 11 are also present on the left side surface of the first electrode 3 on the paper, but they are omitted. The thickness of the oxide films 5 and 7 is such that tunneling is possible, and the oxide films 5 and 7 and the electrodes 3, 6 and 8 form the tunnel junction array MTJ shown in the equivalent circuit of FIG. Second
A gate capacitance Cg is formed between the electrode 10 and the gate electrode 8, and the gate capacitance Cg is connected in series with the capacitance C of the tunnel junction array MTJ via the gate electrode 8.
As a result, the potential of the gate electrode 8 forming the storage node MN takes two stable values based on the operation principle of the memory using the Coulomb shielding. Moreover, since the gate electrode 8 is used as the gate electrode of the read MOS transistor Q ₁ , the read operation is performed by the transistor Q.
_The current flowing between the terminals R _{2 and} R ₁ of the source / drain ₁ may be sensed. Since the gate electrode of the read transistor itself is used as the storage node in this way, it is not necessary to route the wiring from the storage node to the gate of the read transistor, and the parasitic capacitance is higher than that when the inversion layer is used as the storage node. Cs can be made much smaller.

Considering the conditions of room temperature operation when the gate electrode having the configuration of FIG. 1 is actually used as a storage node, the largest capacitance is obviously the tunnel junction array MTJ.
Which determines the operating temperature of the memory. When the tunnel oxide films 5 and 7 have a thickness of 3 nm and the facing area S of the tunnel junction for the charging energy of the tunnel junction to be larger than the thermal energy at room temperature, S is 300 square nanometers or less. Of course, the required area of the tunnel junction varies depending on the thickness of the oxide film, but it must be 1000 square nanometers or less in consideration of the limit of thinning the oxide film.

[0048]

Embodiments of a semiconductor memory device and a method of manufacturing the same according to the present invention will be described below in detail with reference to the drawings.

<Embodiment 1> An embodiment of a semiconductor memory device and a method of manufacturing the same according to the present invention will be described with reference to FIGS. 9 and 10 are cross-sectional views showing, in the order of main steps, a method of manufacturing a semiconductor memory device according to the present invention, which uses a gate electrode of a read MOS transistor as a memory node utilizing Coulomb shielding.
12A and 12B are a plan view and a cross-sectional view showing the next step of FIG. 10 in order.

In FIG. 9A, reference numeral 1 indicates a p-type silicon substrate, and the p-type silicon substrate 1 has a specific resistance of 10 Ω · cm as an example. An element isolation region (not shown) is formed on the p-type silicon substrate 1 by using a normal LOCOS method, and then an oxide film 2 having a thickness of 10 nm is formed by a wet oxidation method at 850 ° C. for 30 minutes.
The structure shown in FIG. 9A is obtained.

Next, polycrystalline silicon 3 is deposited to a thickness of 50 nm by an ordinary CVD method, and phosphorus is diffused at 875 ° C. for 20 minutes. Further, a silicon oxide film 4 is deposited to a thickness of 50 nm by the CVD method to obtain the structure shown in FIG.

After that, the silicon oxide film 4 is processed by photolithography and anisotropic dry etching, and the polycrystalline silicon 3 is etched by using the silicon oxide film 4 as a mask, as shown in FIG. 9C. It becomes a structure. The polycrystalline silicon 3, that is, the first electrode functions as a writing electrode described later.

Next, as shown in FIG. 9D, a 3 nm thick oxide film 5 is formed as an insulating film through a thermal oxide film forming step at 850 ° C. for 5 minutes in a steam atmosphere. This oxide film 5 functions as a tunnel oxide film because of its thickness. Of course, this insulating film may be an insulating film other than the silicon oxide film 5, such as a silicon nitride film.

Further, as shown in FIG. 9E, polycrystalline silicon 6 having a thickness of 50 nm is deposited on the oxide film 5 by the CVD method, and phosphorus is diffused at 875 ° C. for 20 minutes.
Then, as shown in FIG.
Is anisotropically dry-etched to leave the silicon film 6 only on the side wall. This sidewall silicon film 6 functions as a gate electrode. Further, a tunnel junction is formed by the first electrode 3 and the gate electrode 6 sandwiching the oxide film 5 having a thickness of 3 nm.

Next, as shown in FIG. 10A, a thermal oxide film forming step of 850 ° C. for 5 minutes is performed again in a steam atmosphere to form an oxide film 7 having a thickness of 3 nm as an insulating film.
To form. Due to its thickness, this oxide film 7 also functions as a tunnel oxide film like the oxide film 5. Of course, this insulating film may be an insulating film other than the silicon oxide film, such as a silicon nitride film.

Further, a polycrystalline silicon 8 having a thickness of 50 nm is deposited on the oxide film 7 by the CVD method, and the temperature is set to 875 ° C. for 20 minutes.
After the phosphorus is diffused for a minute, the polycrystalline silicon 8 is anisotropically dry-etched, and as shown in FIG.
The polycrystalline silicon 8 is left only on the side wall. This sidewall silicon film 8 also functions as a gate electrode. Therefore, thickness 3n
A tunnel junction is also formed by the gate electrode 6 and the gate electrode 8 sandwiching the oxide film 7 of m. As a result, the serially connected electrodes 3, 6 and 8 insulated from each other by the tunnel oxide films 5 and 7 form a tunnel junction array MTJ. Although not shown, the tunnel oxide film forming process of FIG. 10A and the sidewall gate electrode forming process of FIG. 10B may be sequentially repeated a required number of times to increase the number of tunnel junction rows. In that case, there is an effect that the leak current is reduced.

Next, as shown in FIG. 10C, an oxide film 9 having a thickness of 8 nm is formed as an insulating film by going through a thermal oxide film forming step at 850 ° C. for 20 minutes in a water vapor atmosphere. . This oxide film 9 is thick enough that electron tunneling is not allowed. Of course, this insulating film may be a silicon nitride film or the like other than the silicon oxide film.

Further, as shown in FIG. 10D, polycrystalline silicon 10 having a thickness of 50 nm is deposited on the oxide film 9 by the CVD method, and phosphorus is diffused at 875 ° C. for 20 minutes.

Subsequently, the polycrystalline silicon 10 is dry-etched by a photo-etching method using a resist having a thickness of 1.5 μm to form a second electrode. At this time, the resist is not removed yet. Furthermore, polycrystalline silicon with resist 1
Using 0 as a mask (not shown), the oxide film 9 is anisotropically dry-etched by 8 nm. Further, using the resist as it is, the polycrystalline silicon 8 is etched by 50 nm, and then the oxide film 7 is anisotropically dry-etched by 3 nm. Further, the polycrystalline silicon 6 is etched by 50 nm, the resist is removed by an asher, and thermal oxidation is performed at 800 ° C. for 10 minutes. As shown in FIG. 11, the arsenic ions 14 are removed at 20 keV.
For example, 3 × 10 ¹⁵ pieces / cm ^{2 is} implanted. Of course, these n
The type impurity region may be formed by using phosphorus ions. In FIG. 11A, reference numeral 12 is LOC.
11B shows an element isolation region formed by the OS method, that is, an element isolation oxide film, and FIG. 11B is a sectional structural view of a portion taken along line AA ′ in FIG. 11A.

Thus, as shown in FIG. 12, the source / drain regions 1 are self-aligned with the gate electrodes 6 and 8.
1 is formed. The gate electrode 8 becomes a storage node. Further, an annealing process at 800 ° C. for 10 minutes is performed in a nitrogen atmosphere to obtain the structure shown in FIG. Note that FIG.
2B is a cross-sectional structural view of a portion indicated by a line BB ′ in the plan view of FIG. Further, in FIG. 12A, the oxide films 2 and 5 on the source / drain regions 11 are omitted and are shown in a see-through form.

Then, the PSG (Phosp
LPC for silicon oxide film such as horous Silicate Glass)
If an interlayer insulating film is deposited by the VD method, a contact hole is further opened by the photo-etching method and anisotropic dry etching, a metal such as aluminum is vapor-deposited, and then a wiring pattern or the like is formed by the photo-etching method for integration. The semiconductor memory device can be obtained.

In this embodiment, the electrodes 3, 6, 8 form a tunnel junction string MTJ connected in series, and the electrodes 8, 10 form a gate capacitance Cg connected in series with the tunnel junction string. The equivalent circuit is shown in FIG. In the equivalent circuit of FIG. 2, the terminal W on the gate capacitance Cg side
That is, the second electrode 10 is grounded, a voltage that causes electron tunneling is applied to the terminal W ′ on the side of the capacitance C of the tunnel junction array, that is, the first electrode 3, and if the voltage is returned to 0 V, the electrons tunnel to the tunnel junction array. Storage node MN goes high,
If a reverse voltage is applied between the terminals W and W ', a tunnel occurs in the reverse direction and the storage node MN becomes low. Therefore, depending on whether the storage node MN is high or low, the MOS transistor Q
_{Since 1} is on or off, terminals R ₁ -R
The state of the storage node MN can be known by detecting the current flowing between the _two . That is, it can operate as a memory cell.

As described in the operation section, the feature of the semiconductor memory device according to the present invention is that the storage node of the semiconductor memory device utilizing Coulomb shielding is used as the read MOS transistor by utilizing the sidewall film forming technique. The point is that it is composed of a gate electrode. As a result, there is no need to lay out the electrodes of the storage node as in the conventional example, the capacity of the storage node can be made extremely small, and it is possible to operate not only at the temperature of 77K by liquid nitrogen but also at room temperature. Is. Further, since the semiconductor memory device using such Coulomb shielding controls the injection of one electron, a statistical fluctuation of the number of electrons, which is a problem when miniaturizing a so-called existing DRAM or the like, is caused. Can be suppressed, and low voltage operation with extremely fine dimensions, for example, 0.
Operation at 1V is possible.

In this embodiment, the p-type substrate is used for explanation, but if all polarities are changed, the p-type substrate is used.
It goes without saying that it is possible to realize a memory using Coulomb shielding by the channel MOSFET.

<Embodiment 2> Referring to FIGS. 13 to 15,
Another embodiment of the semiconductor memory device according to the present invention will be described. 13 to 15 are views for explaining an embodiment in which the semiconductor memory device shown in the embodiment 1 is used as a memory cell of a memory array.

By the way, there is a point to be noted when the semiconductor memory device using the Coulomb shield of the first embodiment is used as a memory array. As described in the operation section, when the storage node MN is high, the read MOS transistor Q ₁ is always on. Generally, in a storage array, multiple storage nodes are high,
These are in a state where current flows. In such a case, when an attempt is made to read a memory cell in an off state by the read line, a closed loop is formed through a plurality of memory cells in the on state, and the memory cell that should be in the off state is in the on state. It may be read as if. For this reason, it is necessary to insert another switching transistor in the read line so that even if the storage node MN is in the on state, the entire memory cell is in the off state and no current flows.

FIG. 13 is an explanatory diagram of a memory cell in which another switching transistor is included in the read line,
(A) is a plan view of the device, (b) is a cross-sectional view of a portion indicated by a line AA ′ in the plan view, and (c) is a cross-sectional view of a portion indicated by a line BB ′ in the plan view. 14 is an equivalent circuit diagram of the memory cell. Read MOS transistor Q ₁
And another gate electrode 10 of the switching MOS transistor Q ₂ to which led to series' is, MOS transistor Q ₁
It may be processed at the same time when the second electrode 10 is formed.
Although two memory cells MC1 and MC2 having the first electrode 3 in common are shown in FIG. 13, one memory cell is shown in the equivalent circuit of FIG. This is because, as can be seen from the manufacturing process of the first embodiment, when one memory cell is to be formed, two memory cells are simultaneously formed. As shown in the equivalent circuit of FIG. 14, the source of the MOS transistor Q ₁ of the memory cell is grounded, the gate capacitance Cg side terminal and the tunnel junction column MT are connected.
The J-side terminals are the writing terminals W and W ',
The drain terminal of the gate electrode side terminal and the transistor Q ₂ of the transistor Q ₂ respectively and terminals R and R 'for reading. Therefore, as shown in FIG. 13, W corresponds to the second electrode 10, the common terminal W ′ corresponds to the first electrode 3, and R corresponds to the gate electrode 10 ′.

Next, the memory cell M having the above structure
The operation of C1 and MC2 will be described. First, the case of writing data to the memory cell MC1 will be described with reference to FIGS. To write high (“1”) and low (“0”) to the storage node MN of the memory cell MC1, a voltage pulse applied between the write terminals W ₁ and W ′ is applied as shown in FIG. That is, when writing high, the terminal W ₁ is set low, and the common write terminal W ′ is set high, and then both are set low. This allows
Electrons are tunneled from the first electrode 3 side to the gate electrode 8 side, and the electrons are Coulomb-shielded. At this time, the common terminal W ′ is connected to the terminal W ₂ of the memory cell MC2 so that writing does not occur in the memory cell MC2 shown in FIG.
Apply the same voltage pulse as. In addition, the read terminal R
₁ , R ₂ , R ₁ ′ and R ₂ ′ are kept at low level.

Similarly, when writing a low, the write terminal W ₁ is set high and the common terminal W ′ is set low, and then both are set low. This causes an electron tunnel in the opposite direction from the gate electrode 8 side to the gate electrode 3 side. At this time, the terminal W ₂ of the memory cell MC2 and the read terminals R ₁ and R ₂ , so that writing does not occur in the memory cell MC2.
R ₁ 'and R ₂ ' are all kept at low level.

To read the written high and low states, it is sufficient to select the read terminals R and R ′ and perform current sensing. For example, To read the state of the memory node MN of the memory cell MC1, may be detected current flowing depending on the state of the memory node MN at terminal R ₁ 'giving high to terminal R _1. The terminal R ₂ of the memory cell MC2,
Both R ₂ 'is kept low.

Further, memory cells MC1 and MC2 which form a pair
As can be seen from the structure shown in FIG. 13, since the write common terminal W ′, that is, the first electrode 3 extends over the drain / source diffusion layers 11 via the gate oxide films 2 and 5, the parasitic Of the MOS transistor. However, the parasitic MOS transistor does not operate by holding the potential relationship in the write and read operations described above.

Therefore, using the memory cell according to the present invention,
By arranging them in an array to form a memory array, a desired storage capacity can be obtained. Although the memory cells MC1 and MC2 are operated separately in this embodiment, the write terminals W ₁ and W ₂ and the read terminals R ₁ and R ₂ ,
R ₁ 'and R ₂ ' are connected to each other, and the memory cell MC1,
It goes without saying that MC2 may be used as one memory cell. In that case, the driving capability of the memory cell is improved. Alternatively, when the drain / source layer 11 is formed by ion implantation, the memory cell MC2 side portion may be masked so that the ion implantation layer is not formed, and only one memory cell MC1 may be formed.

<Third Embodiment> With reference to FIGS. 16 to 22,
Another embodiment of the semiconductor memory device and the manufacturing method thereof according to the present invention will be described. 16A to 16C are cross-sectional structural views showing, in the order of main steps, a method of manufacturing a semiconductor memory device according to the present invention in which the gate electrode of a read MOS transistor is used as a memory node utilizing Coulomb shielding.
7 to 22 are a sectional structural view and a plan view sequentially showing the next step of FIG. The same components as those shown in FIGS. 9 to 12 in the first embodiment are designated by the same reference numerals and described below.

As shown in FIG. 16A, the specific resistance 10
Normal LOC for p-type silicon substrate 1 of Ω · cm
After forming an element isolation region (not shown) using the OS method,
A gate oxide film 2 of 10 nm is formed by a wet oxidation method at 850 ° C. for 30 minutes.

Next, polycrystal silicon 3 is deposited on the gate oxide film 2 to a thickness of 50 nm by, for example, the CVD method, and then 875
Diffusion of phosphorus is performed at 20 ° C. for 20 minutes. Further, a silicon oxide film 4 is deposited to a thickness of 50 nm by the CVD method to obtain the structure shown in FIG.

After that, the silicon oxide film 4 is processed by photolithography and anisotropic dry etching, and the polycrystalline silicon 3 is etched by using the silicon oxide film 4 as a mask, whereby the structure shown in FIG. Becomes The pattern interval x between the aligned polycrystalline silicon layers 3 is determined by the sidewall oxide film 5 formed on the sidewall polycrystalline silicon layer 6 which will be described later.
The distance that the comrades do not connect is assumed. Since the capacity cannot be made large enough to operate at room temperature sufficiently, the interval x is 0.1 μm.
The following are preferred.

Then, as shown in FIG. 16D, a thermal oxide film forming step of 850 ° C. for 5 minutes is performed again in a steam atmosphere to form an oxide film 5 having a thickness of 3 nm as an insulating film. This oxide film 5 functions as a tunnel oxide film because of its thickness. Of course, this insulating film may be an insulating film other than the silicon oxide film, such as a silicon nitride film.

Further, a side wall polycrystalline silicon film 6 having a thickness of 50 nm is formed, and the polycrystalline silicon film 6 is processed by photolithography and anisotropic dry etching to obtain a structure as shown in FIG. Here, FIG. 17A is a plan view at this time, and it can be seen that the sidewall polycrystalline silicon film 6 is formed only in a very narrow region. Incidentally, reference numeral 12 is an element isolation region, that is, an element isolation oxide film formed by the LOCOS method, and FIG. 17B shows A in FIG.
It is sectional drawing of the part shown by the A'line.

Next, a thermal oxide film forming step at 850 ° C. for 5 minutes in a water vapor atmosphere is performed to form an oxide film 7 having a thickness of 3 nm as an insulating film to obtain the structure shown in FIG. This oxide film 7 also functions as a tunnel oxide film like the oxide film 5. Of course, this insulating film may be a silicon nitride film or the like other than the silicon oxide film.

Further, polycrystal silicon 8 having a thickness of 50 nm is deposited on the oxide film 7 by the CVD method, and the temperature is set to 875.degree.
After phosphorus is diffused for one minute, polycrystalline silicon 8 is buried in the grooves between the polycrystalline silicon 3 arranged by a so-called etch back process, and then a photolithography method and a dry etching method using a resist having a thickness of 1.5 μm. Thus, the polycrystalline silicon 8 is processed to obtain a sectional structure as shown in FIG. Next, as shown in the same figure, arsenic ions 14 are implanted at 20 keV, for example, 3 × 10 ¹⁵ ions / cm ² .
Of course, these n-type impurity regions may be formed by using phosphorus ions. This n-type impurity region is for reading M
It becomes the source / drain diffusion layer of the OS transistor Q ₁ . Incidentally, FIG. 19B is a sectional view of a portion taken along the line AA ′ in FIG.

Then, by annealing in a nitrogen atmosphere at 850 ° C. for 10 minutes, as shown in FIG.
Source / drain regions 11 are formed in self-alignment with the gate electrode 8. In FIG. 20A, the oxide films 2, 5 and 7 on the source / drain regions 11 are omitted and are shown in a see-through form.

Further, through a thermal oxide film forming step at 850 ° C. for 5 minutes in a steam atmosphere, an oxide film 9 having a thickness of 8 nm is formed as an insulating film as shown in FIG. This oxide film 9
Is thick enough that electron tunnels are not allowed. Of course, this insulating film may be a silicon nitride film other than the silicon oxide film.

Next, after depositing 50 nm of polycrystalline silicon 10 on the oxide film 9 by the CVD method, phosphorus is diffused at 875 ° C. for 20 minutes, and a photolithography method using a resist having a thickness of 1.5 μm is used. 22, the polycrystalline silicon 10 is dry-etched to form a second electrode so as to cover the polycrystalline silicon 8 embedded in the groove between the aligned polycrystalline silicon 3 as shown in FIG. To form. 22A is a plan view, and FIG. 22B is a cross-sectional view of the portion indicated by the line AA ′ in FIG.

Then, a silicon oxide film such as a PSG film having a thickness of 200 nm is deposited by the LPCVD method to form an interlayer insulating film, and a contact hole is opened by the photoetching method and anisotropic dry etching, and a metal such as aluminum is used. After the vapor deposition, a wiring pattern or the like is formed by a photo-etching method, whereby an integrated semiconductor memory device can be obtained.

The difference from the first embodiment is that the gate electrodes 3 are arranged side by side.
That is, the tunnel junction array MTJ is formed in the narrow space between the first electrodes, and the capacitance C of the tunnel junction array MTJ can be made smaller than that of the structure shown in the first embodiment. Therefore, Coulomb shielding is used. Room temperature operation of the memory becomes even easier.

Further, although the present embodiment has been described using the p-type substrate, it goes without saying that a memory utilizing Coulomb shielding by a p-channel MOSFET using an n-type substrate can be realized if all polarities are changed.

<Embodiment 4> Referring to FIGS. 23 to 29,
Still another embodiment of the semiconductor memory device and the manufacturing method thereof according to the present invention will be described. 23 to 29 show a read MOS as a storage node utilizing Coulomb shielding.
6A to 6C are a plan view and a cross-sectional view showing, in the order of main steps, a method for manufacturing a semiconductor memory device according to the present invention using a gate electrode of a transistor. Incidentally, each sectional view (b) is a sectional view taken along the line AA ′ shown in each plan view (a). Further, the same components as those shown in FIGS. 9 to 12 in the first embodiment will be described with the same reference numerals. Here, the manufacturing method for obtaining the structure shown in FIG. 23 is the same as that of the first embodiment shown in FIG. 9A to FIG.
Since it is the same as the manufacturing method up to this point, the subsequent process will be described.

From the state shown in FIG. 10B, a resist 13 having a thickness of 1.5 μm is applied, exposed and developed, and the pattern of the resist 13 as shown in FIG. To get

Next, the sidewall silicon film 8 is etched by using the resist 13 as a mask to form the resist 13 in the region surrounded by the element isolation regions 12 as shown in FIG.
The tunnel oxide film 7 in a portion not covered with the mask is exposed.

Further, the tunnel oxide film 7 is etched using the resist 13 as a mask as it is, and as shown in FIG. 25, the tunnel oxide film 5 and the sidewall silicon film 6 are exposed in a portion not covered with the resist 13. And

After that, the sidewall silicon film 6 is etched using the resist 13 as a mask as it is, so that only the tunnel oxide film 5 is exposed in the region surrounded by the element isolation regions 12, as shown in FIG. . Then 20 ke
Arsenic ions 14 are implanted at V by, for example, 3 × 10 ¹⁵ ions / cm ² to form n-type impurity regions (not shown) in a self-aligned manner with the sidewall gate electrodes 6 and 8 covered with the resist 13. Of course, these n-type impurity regions may be formed by using phosphorus ions. The n-type impurity region serves as the source / drain of the read MOS transistor.

Next, the resist 13 is removed so that the tunnel oxide film 7 and the sidewall silicon film 8 covered with the resist 13 are exposed as shown in FIG. After that, through an annealing step in a nitrogen atmosphere at 850 ° C. for 10 minutes, an oxide film 9 is deposited to a thickness of 10 nm by the CVD method by the LPCVD method and covered with the oxide film 9 as shown in FIG.

Then, a polycrystalline silicon film 10 is deposited to a thickness of 50 nm by the LPCVD method, and the polycrystalline silicon 10 is etched by the photoetching method using a resist having a thickness of 1.5 μm to form a second electrode. Then, the structure shown in FIG. 29 is obtained. Incidentally, FIG. 29 (c) shows BB ′ in FIG. 29 (a).
It is sectional drawing of the part shown by the line. Source / drain 1 of a read MOS transistor in a self-aligned manner with respect to a sidewall silicon film 8 which constitutes a gate electrode to be a storage node.
It can be seen that 1 is formed.

In the case of forming the gate electrode of the read MOS transistor in the case of the first embodiment, after all the necessary films are deposited, they are sequentially etched from the top.
If the etching selection ratio is not sufficient, the substrate 1 may be scraped and the processing may become difficult. On the other hand, in the case of this embodiment, the gate electrodes 6 of the read MOS transistor 6 are formed after the second sidewall silicon film 8 is formed.
Since the etching of No. 8 is performed, the manufacturing method is effective even when the selection ratio of the dry etching material is not sufficient as compared with the case of the first embodiment.

Also in this embodiment, the p-type substrate is used for description, but if all polarities are changed, the p-type substrate is used.
It goes without saying that it is possible to realize a memory using Coulomb shielding by the channel MOSFET.

Although the preferred embodiments of the semiconductor memory device and the method of manufacturing the same according to the present invention have been described above, the present invention is not limited to the above embodiments. For example, a read MOS transistor may be used instead. It is needless to say that it is also possible to use the MIS transistor constituted by the gate insulator of the above, and various design changes can be made without departing from the spirit of the present invention.

[0097]

As is apparent from the above-mentioned embodiments, according to the present invention, in the memory utilizing the Coulomb shielding phenomenon, the gate capacitance C is obtained by using the silicon LSI process.
g, the capacitance C of the tunnel junction array MTJ, and the parasitic capacitance Cs
By using the gate electrode itself of the read MOS transistor as a storage node, the operating temperature of the memory using the conventional Coulomb shielding phenomenon is only 30 mK, while the Coulomb shielding according to the present invention is small. The semiconductor memory utilizing the phenomenon can operate not only at a temperature of 77K by liquid nitrogen but also at room temperature.

Therefore, it is possible to realize a semiconductor memory utilizing the Coulomb shielding phenomenon which is excellent in cost and ease of use as compared with the prior art and which does not require refreshing and which can be operated at room temperature and low voltage.

[Brief description of drawings]

1A and 1B are diagrams showing an embodiment of a semiconductor memory device according to the present invention, in which FIG. 1A is a sectional view and FIG. 1B is a bird's eye view.

FIG. 2 is an equivalent circuit diagram of the semiconductor memory device according to the present invention shown in FIG.

FIG. 3 is a diagram illustrating the principle of Coulomb shielding,
(A) is an equivalent circuit diagram in which a constant current source is connected to the tunnel junction, and (b) is a characteristic diagram showing a relationship between accumulated charge of the tunnel junction capacitance and charging energy.

FIG. 4 is a diagram for explaining the influence of external impedance on Coulomb shielding, where (a) shows the accumulated charge before and after the tunnel and the range of Coulomb shielding when the external impedance is infinite, and (b) shows the external impedance. FIG. 6 is a diagram showing accumulated charges before and after a tunnel and a range of Coulomb shielding in a finite case.

FIG. 5 is a conceptual diagram for explaining a memory using Coulomb shielding.

FIG. 6 is a diagram illustrating an operating principle of a memory using Coulomb shielding.

FIG. 7 is a conceptual diagram in which an inversion layer is used for a storage node of a memory using Coulomb shielding, (1) is a schematic (a) cross-sectional structural diagram and (b) equivalent circuit diagram of a memory cell, and (2).
3A is a cross-sectional structure diagram and FIG. 2B is an equivalent circuit diagram showing a configuration for extracting a potential of a storage node.

8A and 8B are another conceptual diagram in which an inversion layer is used for a storage node of a memory using Coulomb shielding, and FIG. 8A is a sectional structural view and FIG. 8B is an equivalent circuit diagram.

9A to 9C are cross-sectional views showing an embodiment of the method of manufacturing the semiconductor memory device according to the present invention shown in FIG.

10A to 10D are cross-sectional views sequentially showing main steps subsequent to the step shown in FIG. 9 of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 11 is a diagram for explaining the next step of the step shown in FIG. 10 of the method for manufacturing a semiconductor memory device according to the present invention,
(A) is a plan view, (b) is a cross-sectional view of a portion indicated by line AA 'in the plan view.

FIG. 12 is a diagram illustrating the next step of the step shown in FIG. 11 of the method for manufacturing a semiconductor memory device according to the present invention,
(A) is a plan view, (b) is a cross-sectional view of a portion indicated by the line BB 'in the plan view.

13A and 13B are views showing another embodiment of the semiconductor memory device according to the present invention, in which FIG. 13A is a plan view and FIG.
A sectional view taken along the line A ', (c) is a plan view showing B
It is sectional drawing of the part shown by the B'line.

FIG. 14 is an equivalent circuit diagram of the memory cell shown in FIG.

15 is a voltage waveform diagram for explaining a data write operation of the memory cell shown in FIG.

FIG. 16 is a diagram showing yet another embodiment of the semiconductor memory device according to the present invention, in which (a) to (d) are cross-sectional views shown in the order of main manufacturing steps.

FIG. 17 is a diagram illustrating the next step of the step shown in FIG. 16 of the method for manufacturing a semiconductor memory device according to the present invention,
(A) is a plan view, (b) is a cross-sectional view of a portion indicated by line AA 'in the plan view.

FIG. 18 is a cross-sectional view for explaining the next step of the step shown in FIG. 17 of the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 19 is a diagram for explaining the next step of the step shown in FIG. 18 of the method for manufacturing a semiconductor memory device according to the present invention,
(A) is a plan view, (b) is a cross-sectional view of a portion indicated by line AA 'in the plan view.

20 is a diagram illustrating the next step of the step shown in FIG. 19 of the method for manufacturing a semiconductor memory device according to the present invention,
(A) is a plan view, (b) is a cross-sectional view of a portion indicated by the line BB 'in the plan view.

FIG. 21 is a cross-sectional view for explaining the next step of the step shown in FIG. 20 of the method for manufacturing a semiconductor memory device according to the present invention.

22 is a diagram illustrating the next step of the step shown in FIG. 21 of the method for manufacturing a semiconductor memory device according to the present invention,
(A) is a plan view, (b) is a cross-sectional view of a portion indicated by line AA 'in the plan view.

23A and 23B are diagrams showing still another embodiment of the method of manufacturing a semiconductor memory device according to the present invention, in which FIG. 10A is a plan view showing a step subsequent to the step shown in FIG. A in the figure
It is a (b) sectional view of the portion shown by the A'line.

24 is a diagram illustrating the next step of the step shown in FIG. 23 of the method for manufacturing a semiconductor memory device according to the present invention,
(A) is a plan view, (b) is a cross-sectional view of a portion indicated by line AA 'in the plan view.

25 is a diagram illustrating the next step of the step shown in FIG. 24 of the method for manufacturing a semiconductor memory device according to the present invention,
(A) is a plan view, (b) is a cross-sectional view of a portion indicated by line AA 'in the plan view.

FIG. 26 is a diagram illustrating the next step of the step shown in FIG. 25 of the method for manufacturing a semiconductor memory device according to the present invention,
(A) is a plan view, (b) is a cross-sectional view of a portion indicated by line AA 'in the plan view.

FIG. 27 is a diagram illustrating the next step of the step shown in FIG. 26 of the method for manufacturing a semiconductor memory device according to the present invention,
(A) is a plan view, (b) is a cross-sectional view of a portion indicated by line AA 'in the plan view.

FIG. 28 is a diagram illustrating the next step of the step shown in FIG. 27 of the method for manufacturing a semiconductor memory device according to the present invention,
(A) is a plan view, (b) is a cross-sectional view of a portion indicated by line AA 'in the plan view.

29 is a diagram illustrating the next step of the step shown in FIG. 28 of the method for manufacturing a semiconductor memory device according to the present invention,
(A) is a plan view, (b) is a cross-sectional view of a portion indicated by a line AA ′ in the plan view, and (c) is a cross-sectional view of a portion indicated by a line BB ′ in the plan view.

[Explanation of symbols]

1 ... Silicon substrate 2 ... Silicon oxide film 3 ... Polycrystalline silicon (first electrode) 4 ... Silicon oxide film 5 ... Silicon oxide film (tunnel oxide film) 6 ... Polycrystalline silicon 7 ... Silicon oxide film (tunnel oxide film) 8 ... Polycrystalline silicon 9 ... Silicon oxide film 10 ... Polycrystalline silicon (second electrode) 10 '... Polycrystalline silicon 11 ... Impurity diffusion region 12 ... Element isolation region (element isolation oxide film) 13 ... Resist 14 ... Arsenic ion C ... capacity Cg ... gate capacitance Cs ... parasitic capacitance MC1 ... memory cell MC2 ... memory cell MN ... storage node Q ₁ ... MOS transistor Q ₂ ... switching MOS transistor for reading tunnel junction sequence

Claims (12)

[Claims] 1. A semiconductor memory device comprising: a tunnel junction string including at least one tunnel junction; a capacitor connected in series with the tunnel junction string; and a connection node between the capacitor and the tunnel junction string as a storage node. A first electrode formed on the first conductivity type semiconductor substrate via an insulating film, and a plurality of electrodes connected in series to the first electrode via the insulating film and insulated from each other by the insulating film, With respect to an electrode which has the tunnel junction array and the capacitance formed of the plurality of electrodes and a second electrode connected through an insulating film, and which is at least a storage node among the plurality of electrodes. A pair of second members formed in the semiconductor substrate in a self-aligned manner
A semiconductor memory device having a read transistor formed of a conductive type impurity layer. 2. The plurality of insulating films existing between the first electrode and the second electrode via the plurality of electrodes are at least one insulating film having a thickness capable of quantum mechanical tunneling of electrons. 2. The semiconductor memory device according to claim 1, wherein at least one is an insulating film having a thickness that does not allow quantum mechanical tunneling of electrons. 3. The electrode according to claim 1, wherein the plurality of electrodes are located on a side wall side of the first electrode, and the insulating film for insulating the plurality of electrodes from each other is a side wall insulating film formed on each electrode. The semiconductor memory device described. 4. The semiconductor memory device according to claim 1, wherein the areas of the electrodes facing each other of the first electrode and the plurality of electrodes are at most 1000 square nanometers. 5. The semiconductor memory device according to claim 1, wherein the charging energy determined by the capacitance of the electrode serving as the storage node is larger than the thermal energy determined by the temperature. 6. The electric potential of an electrode which is a storage node among the plurality of electrodes has a hysteresis with respect to the electric potential applied between the first and second electrodes. The semiconductor memory device described. 7. The electric potential of an electrode serving as a storage node among the plurality of electrodes has two stable values according to the electric potential applied between the first and second electrodes. The semiconductor memory device according to 1. 8. The semiconductor memory device according to claim 7, wherein the threshold voltage of the read transistor is a voltage value between two stable potentials that can be taken by the electrode serving as the storage node. 9. The semiconductor memory device according to claim 1, wherein a switching transistor that turns on / off a current of the reading transistor is connected in series with the reading transistor. 10. A memory array in which any one of the semiconductor memory devices according to claim 1 is arranged in an array. 11. A step 1 of forming a gate oxide film on a surface of a first conductivity type semiconductor substrate including an element isolation oxide film, a step 2 of forming a first conductive film on the gate oxide film, and a first step. Step 3 of forming an insulating film on the conductive film, Step 4 of patterning the first conductive film and the insulating film to form a first electrode having the insulating film on the upper surface, and a thickness capable of tunneling electrons. Of forming a first insulating film on the surface, forming a second conductive film on the side wall of the first electrode via the first insulating film, and Step 7 of forming the second insulating film on the surface, Step 8 of further forming a third conductive film on the side wall side of the first electrode via the second insulating film formed in Step 7, and Step 7 and After repeating Step 8 in sequence for the required number of times, a third insulating film having a thickness that prevents electron tunneling is formed on the surface. And the step 10 of forming a fourth conductive film to be the second electrode on the surface, and the insulating film and the conductive film formed in the above step 10, step 9, step 8, step 7, and step 6. A semiconductor comprising: a step 11 of removing the remaining portion and a step 12 of forming an impurity of the second conductivity type in the semiconductor substrate of the first conductivity type in a self-aligned manner with respect to the required portion. Storage device manufacturing method. 12. A step 1 of forming a gate oxide film on a surface of a first conductivity type semiconductor substrate including an element isolation oxide film, a step 2 of forming a first conductive film on the gate oxide film, and a first step. Step 3 of forming an insulating film on the conductive film, Step 4 of patterning the first conductive film and the insulating film to form a first electrode having the insulating film on the upper surface, and a thickness capable of tunneling electrons. Of forming a first insulating film on the surface, forming a second conductive film on the side wall of the first electrode via the first insulating film, and Step 7 of forming the second insulating film on the surface, Step 8 of further forming a third conductive film on the side wall side of the first electrode via the second insulating film formed in Step 7, and Step 7 and After repeating step 8 in sequence for a required number of times, a step 9 of forming a resist pattern at a required portion, and a step 9 of Step 10 of removing the conductive film and the insulating film formed in steps 8, 7 and 6 by using the formed resist pattern as a mask, and the second conductivity type impurities in the first conductivity type semiconductor substrate Step 1 of forming a pattern in a mask in a self-aligned manner with respect to the required portion
1 and the step 12 of forming a third insulating film having a thickness that prevents electron tunneling after removing the resist pattern.
And step 13 of forming a fourth conductive film on the surface, and patterning the fourth conductive film formed in step 13 to form a second conductive film.
And a step 14 of forming an electrode.