JP3280156B2 - Semiconductor memory device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device which operates at room temperature using a Coulomb shielding phenomenon and does not need to be refreshed, and a method of manufacturing the same.

[0002]

2. Description of the Related Art A conventional typical semiconductor memory device, D
In a RAM or a flash memory, as memory cells are miniaturized in order to realize an integration degree of 1 gigabit or more on a single chip, a statistical fluctuation in the number of electrons becomes a size that cannot be ignored. Operation becomes difficult. In addition, the DRAM has a drawback in that the charge flows out of the storage capacitor portion, so that an operation of periodically rewriting the data to retain the memory, that is, the refresh operation is required, and the power consumption is increased. Although it is unnecessary, there is a disadvantage that random access is not possible because only batch erasure can be performed.

On the other hand, in a memory using Coulomb shielding, the number of electrons can be controlled in units of one, and in principle, the storage unit can be one in number of electrons.
It is possible to realize a semiconductor memory device with much higher integration than a DRAM or a flash memory. For the basic concept of the memory using the Coulomb shield, for example, see “Single Charge Tunneling,” edited by H. Grabertand in Chapter 9, pp. 313 to 317 of “Single Charge Tunneling” edited by Grabber and Deboret.
MH Devoret, Plenum Press, New York, 1992, Chap
ter 9).

If this Coulomb shielding is used, the fluctuation of the number of electrons, which is considered to be an essential condition when memory cells are further miniaturized in the future, can be suppressed. In addition, since a memory using Coulomb shielding is capable of random access, and in principle can realize a single-electron memory that does not require refresh, a semiconductor memory that can achieve high integration with lower power consumption than a DRAM or a flash memory. It is expected as a device.

An example of an experimental verification of a memory utilizing Coulomb shielding, which is expected to have such advantages, is disclosed in Electronics Letters, Vol.
29, No. 4 (Electronics Letters, 18th Feb. 199
3, Vol.29, No.4,). In this verification example, a memory cell utilizing Coulomb shielding is formed in a two-dimensional plane using a GaAs substrate having a delta-doped structure having a steep impurity concentration distribution, and this semiconductor memory device performs a memory operation at an extremely low temperature of 30 mK. It was shown that.

[0006]

However, according to the experimental verification example of the memory utilizing the Coulomb shield described above, the memory cell is formed in a two-dimensional plane using a GaAs substrate having a delta-doped structure. As a result, the electrodes corresponding to the storage nodes of the memory cells are routed in a two-dimensional plane, and it is difficult to reduce the capacitance of the storage nodes. As a result, the operating temperature of the storage device is as low as 30 mK, and the operation at room temperature cannot be expected because the capacity of the storage node cannot be reduced even if the miniaturization is advanced. Further, since the process uses a special substrate such as a GaAs substrate having a delta-doped structure, there is a problem in terms of manufacturing cost and mass productivity.

Therefore, an object of the present invention is to use a silicon LSI process which is advantageous in terms of manufacturing cost and mass productivity, to operate at room temperature using Coulomb shielding, to operate at room temperature, and not to need refresh. An object of the present invention is to provide a semiconductor memory device and a method of manufacturing the same.

In addition, in order to achieve a very high integration density,
Even if an extremely fine element is formed, there has been an issue of realizing a stable operation which is not affected by a statistical fluctuation in the number of electrons.

[0009]

According to the present invention, there is provided a semiconductor memory device comprising: a tunnel junction array MTJ including at least one tunnel junction; a capacitor Cg connected in series with the tunnel junction array; In a semiconductor memory device in which a connection part with a column is a storage node MN, on a semiconductor substrate of the first conductivity type, that is, in the first embodiment, the p-type substrate 1
A first electrode 3 formed thereon with an insulating film interposed therebetween, a plurality of electrodes 6, 8 connected in series to the first electrode via an insulating film 5 and insulated from each other by an insulating film 7; A plurality of electrodes and a second electrode connected via an insulating film to the tunnel junction array and a capacitor; and at least a storage node in the plurality of electrodes and characterized in that it has a reading transistor Q ₁ constituting the impurity layer 11 of the pair of second conductivity type formed in a self-aligned manner with said semiconductor substrate 1 to the electrode 8 to be.

In the above-mentioned semiconductor memory device, at least one of the plurality of insulating films existing between the first electrode and the second electrode via the plurality of electrodes has a thickness that enables quantum mechanical tunneling of electrons. That is, it is preferable that the insulating film has a thickness of at most 5 nm, and at least one of the insulating films has a thickness that does not allow quantum mechanical tunneling of electrons.

Preferably, the plurality of electrodes are located on a side wall of the first electrode, and the insulating film for insulating the plurality of electrodes from each other is a side wall insulating film formed on each electrode.

Further, if the area of the electrode facing each of the first electrode and the plurality of electrodes is at most 1000 square nanometers, the charging energy determined by the capacitance of the electrode serving as the storage node is changed to the thermal energy determined by the temperature. Can be larger than

In addition, the potential of an electrode serving as a storage node among the plurality of electrodes has a hysteresis with respect to the potential applied between the first and second electrodes, so that the first
And the potential applied between the second electrodes, the potential of the electrode serving as the storage node can have two stable values,
Therefore, it is preferable that the threshold voltage of the reading transistor be a voltage value between two stable potentials of the electrode serving as the storage node.

As described above, according to the semiconductor memory device of the present invention, a tunnel connected in series between a plurality of gate electrodes formed on a semiconductor substrate via an insulating film by controlling the thickness of the insulating film. By realizing the junction array MTJ and the capacitance Cg and utilizing the fact that the electric potential of the portion sandwiched between the tunnel junction array and the capacitance has two stable values due to Coulomb shielding, a portion that can take these two values, that is, storage. Node M
The N, is characterized in that the gate electrode of the data read transistor Q _1.

In the method of manufacturing a semiconductor memory device according to the present invention, a step 1 of forming a gate oxide film 2 on a surface of a semiconductor substrate 1 of a first conductivity type including an element isolation oxide film 12 and a step of forming a gate oxide film Step 2 of forming a first conductive film, that is, phosphorus-doped polycrystalline silicon, Step 3 of forming an insulating film on the first conductive film, and patterning the first conductive film and the insulating film so that the insulating film is Step 4 of forming a first electrode 3 on the surface, and Step 5 of forming a first insulating film, ie, a tunnel oxide film 5, having a thickness capable of tunneling electrons on the surface.
Forming a second conductive film, that is, phosphorus-doped polycrystalline silicon 6 on the side wall of the first electrode 3 via the first insulating film; and forming a second insulating film having a thickness capable of tunneling electrons, Step 7 of forming a tunnel oxide film 7 on the surface, and further forming a third conductive film, that is, phosphorus-doped polycrystalline silicon 8 on the side wall of the first electrode via the second insulating film formed in Step 7 8, a step 9 of forming a third insulating film, that is, an oxide film 9 having a thickness that does not allow electron tunneling on the surface after repeating the steps 7 and 8 in order, a required number of times; Step 10 of forming a conductive film of No. 4, ie, phosphorus-doped polycrystalline silicon 10 on the surface, and the insulating film and the conductive film formed in Steps 10, 9, 8, 7, and 6 except for required portions. Removing step 11 Characterized by a step 12 formed in a self-aligned manner a drain 11 types of impurities i.e. n-type impurity with respect to the predetermined position in the first conductivity type semiconductor substrate.

Alternatively, a step 1 of forming a gate oxide film on the surface of the first conductivity type semiconductor substrate including the element isolation oxide film;
Step 2 of forming a first conductive film on the gate oxide film, Step 3 of forming an insulating film on the first conductive film, and patterning the first conductive film and the insulating film to cover the insulating film Step 4 of forming a first electrode on the surface, Step 5 of forming a first insulating film having a thickness capable of tunneling electrons on the surface, and forming a second conductive film through the first insulating film. A step 6 of forming on the side wall of one electrode, a step 7 of forming a second insulating film having a thickness capable of tunneling electrons on the surface, and a first electrode through the second insulating film formed in the step 7 Step 8 of forming a third conductive film on the side wall side of Step 5, Step 9 of forming a resist pattern at a required location after repeating Steps 7 and 8 in order, and Masking the resist pattern formed in Step 9 Then, the conductive film and the insulating film formed in the steps 8, 7, and 6 are removed. A step 10 of forming an impurity of the second conductivity type in a semiconductor substrate of the first conductivity type in a self-aligned manner with respect to the required portion using the resist pattern as a mask; Forming a third insulating film having a thickness that does not allow electron tunneling, and further forming a fourth conductive film on the surface 13
And a step 14 of patterning the fourth conductive film formed in the step 13 to form a second electrode.

[0017]

A first electrode formed on a semiconductor substrate of a first conductivity type via an insulating film, and a plurality of first electrodes connected in series to the first electrode via the insulating film and mutually insulated by the insulating film. The electrode and a second electrode connected to the plurality of electrodes via an insulating film are formed by a tunnel junction column MTJ and a gate capacitance C.
g is connected in series. A pair of second conductivity type impurity layers formed in the first conductivity type semiconductor substrate in a self-aligned manner with respect to at least an electrode serving as a storage node MN among the plurality of electrodes includes a source / drain of a read transistor. Becomes In addition, the gate of the read transistor functions as a storage node MN utilizing Coulomb shielding.

The plurality of insulating films existing between the first electrode and the second electrode via the plurality of electrodes are formed by making the thickness of the insulating film as thin as 5 nm at most. The quantum mechanical tunneling of electrons becomes impossible by making the insulating film thicker than this. Therefore, portions insulated from each other by a thin insulating film capable of tunneling constitute a tunnel junction row MTJ, and portions insulated by a thick insulating film constitute a gate capacitance Cg.

Further, the plurality of electrodes are located on the side wall side of the first electrode, and the insulating film for insulating the plurality of electrodes from each other is a side wall insulating film formed on each electrode. And the area of the electrodes facing each other of the plurality of electrodes can be formed as a very small area of at most 1000 square nanometers. As will be described later, the charging energy determined by the capacitance of the electrode serving as the storage node is determined by the temperature. Can be made larger than the heat energy determined by As a result, the memory can operate at room temperature using the coulomb shield.

Further, since the potential of the electrode serving as the storage node MN has hysteresis with respect to the potential applied between the first and second electrodes, the potential of the storage node can have two stable values. If the threshold voltage of the reading transistor is set to a voltage value between these two stable potentials, a binary memory operation becomes possible.

Here, the operation principle of Coulomb shielding used in the semiconductor memory device according to the present invention will be described. FIG.
FIG. 3 is a diagram for explaining the principle of Coulomb shielding, and considers a tunnel junction connected to a constant current source I as shown in an equivalent circuit of FIG. FIG. 3B is a characteristic diagram showing the relationship between the charge Q stored in the capacitance C of the tunnel junction and the charging energy. Here, a tunnel junction refers to a junction capable of moving electrons with a certain probability. Assuming that the accumulated charge Q of the tunnel junction is 0 in the initial state, as shown in FIG. 3B, the accumulated charge increases as time elapses by the constant current source I as shown at point a, and at the same time, The charging energy Q ² / 2C of the tunnel junction also increases. When the accumulated charge reaches the point b of 0.5e and tries to exceed it, one electron tunnels, the state shifts from the point b to the point c, and the accumulated charge Q accumulated at the tunnel junction becomes −0.0.
5e. This is because the tunneling of one electron can reduce the charging energy of the entire system. The value of ± 0.5e of the accumulated charge Q is:
It is determined as a point where there is no difference in charging energy before and after tunneling of one electron, that is, a critical point where charging energy is equal before and after tunneling.

Again, the accumulated charge Q increases with time by the constant current source I, but electron tunneling does not occur until the point b is reached. This is because the accumulated charge Q is -0.5
Between e and 0.5e, which is contrary to the law of nature, since the charge energy after tunneling is greater than the charge energy before tunneling, no matter which direction the electron tunnels in the tunnel junction, No electron tunneling can occur until point b is reached. That is, when the accumulated charge Q is between -0.5e and 0.5e, electron tunneling does not occur. This state in which electron tunneling is prohibited is called Coulomb shielding. Therefore, in the following range, electrons 1
Even individual tunnels would be completely banned.

[0023]

(Equation 1)

Of course, when the temperature is high, the fluctuation of the electron energy occurs due to the heat energy, and the Coulomb shielding state is broken, so that electron tunneling becomes possible. Therefore, in order for Coulomb shielding to occur, the capacitance C of the tunnel junction is sufficiently small, that is, the charging energy Q ² / of the tunnel junction.
The condition is that 2C is larger than the heat energy.

The above is when the external impedance seen from the tunnel junction is infinite. That is, the above equation (1) is the case shown in FIG. 4A, and is the range of Coulomb shielding obtained by comparing the charging energy due to the accumulated charge of the tunnel junction before and after the tunnel. In an actual system, since the external impedance is finite, redistribution of electrons occurs after one electron tunnels. If the external impedance is represented by a capacitance value C _ext , after one electron tunnels, the accumulated charge at the tunnel junction becomes Qe · C, as shown in FIG.
/ (C + C _ext ). Therefore, by comparing the charging energies before and after the tunnel, the range of Coulomb shielding is as follows.

[0026]

(Equation 2)

On the other hand, in the case of a tunnel junction connected to a constant voltage source, the external impedance may be considered to be 0, that is, C _ext = ∞. Therefore, according to the equation (2), there is no Coulomb shielding range. It will not happen.

FIG. 5 is a conceptual diagram of a memory using the Coulomb shield. In FIG. 5, reference numeral MTJ indicates a tunnel junction row, and the tunnel junction row MTJ is composed of N tunnel junctions. The tunnel junction array MTJ and the gate capacitance Cg are connected in series, and the tunnel junction array MTJ
Between the gate and the gate capacitance Cg (this electrode is connected to the storage node M
N. ) Is connected to the sense amplifier SA. Note that the gate capacitance Cg is a capacitance between the storage node MN and the gate electrode, and a capacitance Cs connected to the storage node MN.
Is a capacitance with a peripheral electrode, a so-called parasitic capacitance.

The operation principle of the memory using the Coulomb shield configured as described above will be described below. This operation principle is a detail of the contents described in the experimental verification example of the memory using the Coulomb shield described above.
Assuming that the capacitance of one tunnel junction is NC, that is, the entire capacitance of the tunnel junction row MTJ is C, and the external impedance seen from one tunnel junction connected to the storage node MN is _Cext , the following relational expression is obtained. Equation (3) representing the critical charge amount Qc is obtained.

[0030]

(Equation 3)

Here, the critical charge amount Qc refers to a charge amount when the Coulomb shielding cannot be maintained and electron tunneling occurs. That is, if the range of Coulomb shielding is represented by the critical charge Qc, the following is obtained.

[0032]

(Equation 4)

Assuming that the potential and the number of electrons at the storage node MN are V and n, and the gate potential is Vg, the charge ne
The following equation holds for.

[0034]

(Equation 5)

Therefore, potential V at storage node MN is represented by the following equation.

[0036]

(Equation 6)

Using this equation (6) as a parameter with the number of electrons n at the storage node MN as the potential V at the storage node
Is plotted against Cg · Vg / e as the dashed line in FIG. In the same figure, the range of Coulomb shielding shown by the equation (4) is also shown. Coulomb shielding means that the number of electrons n in the storage node MN does not change even if the gate potential Vg changes in the range of Coulomb shielding.

Now, consider how the potential V at the storage node MN changes when the gate voltage Vg is changed. When the gate voltage Vg is 0 volt, the storage node M
Assume that the potential V of N is 0 volt (a in FIG. 6).
point). When the gate voltage Vg is increased from this state, the potential V of the storage node MN continuously increases while the number of electrons n remains 0 because the gate voltage Vg is within the range of Coulomb shielding. At the point b, one electron tunnels, and the potential V of the storage node MN becomes the point c on the broken line of n = 1, and the number of electrons n
The state is still 1, and the state of the Coulomb shielding is returned again. When the gate voltage Vg further increases and reaches the point d, one electron tunnels again, and the potential V of the storage node MN becomes n = 2.
Point e on the dashed line. When the gate voltage Vg is decreased from the state at the point e, the number n of electrons remains at 2 and does not change and the potential V of the storage node MN continuously decreases because it is within the range of Coulomb shielding. At the point f, one electron tunnels in the reverse direction, and the potential V of the storage node MN becomes n
= 1 on the broken line.

As a result, when the gate voltage Vg is changed periodically, the potential V of the storage node MN has a hysteresis as shown by a thick solid line in FIG. For example, when the gate voltage Vg is 0 volt, the storage node MN
Takes two stable points indicated by white circles. Therefore, by setting the threshold voltage of the data read transistor whose gate electrode is connected to the storage node MN between these two stable points, the data read transistor is set to be high when the potential of the storage node MN is “high”. Current flows on the other hand, when "low", no current flows, and data can be read. In this way, a memory using Coulomb shielding is possible in principle.

As can be seen from this principle, the storage node M
In order for the potential V of N to have hysteresis, at least two or more states must exist within the range of Coulomb shielding when the gate voltage Vg is 0 volt as shown in FIG. Specifically, in equation (6),
The value Qc / C obtained from the expression (3) must be larger than the value when n = −1 and the gate voltage is 0 volt (corresponding to the intersection with the vertical axis). Therefore, the following condition must be satisfied.

[0041]

(Equation 7)

Equation (7) is a condition for operating the memory. The most important thing when actually performing a memory operation using this principle is how Cg + C + Cs
To realize a system with small This is because, as already described under the condition where Coulomb shielding occurs, the larger the charging energy determined by the total capacitance Cg + C + Cs, the larger the thermal energy can be operated, and therefore, the memory using the Coulomb shielding can be operated. This is because the operating temperature can be increased.

When a memory using Coulomb shielding is realized by using silicon, there are two possible methods for forming the storage node MN. There are a case where the inversion layer formed on the substrate surface by the gate electrode is used and a case where the gate electrode itself is used. These will be described below.

FIG. 7 shows a conceptual diagram when the inversion layer is used as a storage node. FIG. 7A is a schematic (a) sectional structural view of a storage node using an inversion layer, and FIG. 7B is an equivalent circuit diagram, and FIG. 7B shows a configuration for extracting the potential of the storage node ( 3A is a cross-sectional structural diagram, and FIG. 3B is an equivalent circuit diagram. The inversion layer 23 formed on the surface of the substrate 20 by the gate voltage Vg applied to the gate electrode 22;
1 is the capacitance C of the tunnel junction, and the portion sandwiched between the inversion layer 23 and the gate electrode 22 is the gate capacitance Cg connected in series with the tunnel junction. Therefore, based on the operation principle of the memory using the Coulomb shield, the potential of the inversion layer 23 formed immediately below the gate electrode 22 has two stable values. As a configuration for extracting the potential, the potential can be extracted by the wiring 25 via the diffusion layer 24 as shown in (2) of FIG. This wiring 25
For example, as shown in the broken line of the equivalent circuit, a normal MOS
Can be read out by connecting to the gate electrode, but this method has a drawback that the parasitic capacitance Cs increases as a result of routing the wiring 25.

FIG. 8 shows another conceptual diagram when the inversion layer is used as a storage node. FIG. 8A is a schematic cross-sectional structure diagram, and FIG. 8B is an equivalent circuit diagram thereof. When an inversion layer formed by a gate voltage applied to a gate electrode is used as a storage node, a tunnel junction is formed as shown in FIG.
8A, the gate voltage Vg1 applied to the first gate electrode 32 as shown in FIG.
Thus, the inversion layer 34 formed on the surface of the substrate 30 can be used. In this case, the first gate electrode 32 and the second
The respective gate voltages Vg1, Vg2 of the gate electrode 33
The capacitance C of the tunnel junction is formed between the inversion layers 34 and 35 formed by the inversion layer 35 and the second gate electrode 33.
Is a gate capacitance Cg connected in series with the tunnel junction. Therefore, in this case, the capacitance C of the tunnel junction can be made smaller than in the configuration shown in FIG. Since reading from the storage node is performed in the same manner as in the case of (2) in FIG. 7, as a result of routing the wiring, the parasitic capacitance Cs is substantially the same.

On the other hand, in the case where the gate electrode itself is used as a storage node, that is, in the case of the semiconductor memory device according to the present invention, a specific sectional structure diagram and a bird's-eye view are shown in FIG.
(A) and (b), and an equivalent circuit thereof is shown in FIG.
As shown in FIG. 1A, a first substrate is placed on a silicon substrate 1.
The first electrode 3 with the gate oxide film 2 interposed therebetween, the gate electrodes 6 and 8 insulated on the side walls of the first electrode 3 by the oxide films 5 and 7, and the thick oxide film on the side walls of the gate electrode 8. A second electrode 10 is formed via the first electrode 9. As shown in FIG. 1B, the source / drain diffusion is self-aligned with respect to at least the electrode 8 serving as a storage node (in this case, with respect to the electrode 8 and the electrode 6). A layer 11 is formed. In FIG. 1B, only the source is shown, and the drain is not shown although it is located on the back side of the drawing. Similarly, oxide films 7 and 9, gate electrodes 6 and 8, a second electrode 10, and a diffusion layer 11 exist on the left side of the first electrode 3 on the paper surface, but are omitted. The thickness of the oxide films 5 and 7 is a thickness that allows tunneling, and the oxide films 5 and 7 and the electrodes 3, 6, and 8 form the tunnel junction row MTJ shown in the equivalent circuit of FIG. Second
A gate capacitance Cg is formed between the electrode 10 and the gate electrode 8, and the gate capacitance Cg is connected in series with the capacitance C of the tunnel junction row MTJ via the gate electrode 8.
As a result, the potential of the gate electrode 8 forming the storage node MN takes two stable values based on the operation principle of the memory using the Coulomb shield. Moreover, since it uses as a gate electrode of the MOS transistor Q ₁ for reading the gate electrode 8, the read transistor Q
_The current flowing between the source / drain terminals R _{2 and} R ₁ may be sensed. As described above, since the gate electrode itself of the read transistor is used as the storage node, it is not necessary to route the wiring from the storage node to the gate of the read transistor, and the parasitic capacitance is smaller than when the inversion layer is used as the storage node. Cs can be made much smaller.

Considering the conditions of the room temperature operation when the gate electrode having the structure shown in FIG. 1 is actually used as a storage node, the largest capacitance is clearly the tunnel junction row MTJ.
Which determines the operating temperature of the memory. When the thickness of the tunnel oxide films 5 and 7 is set to 3 nm and the facing area S of the tunnel junction for making the charging energy of the tunnel junction larger than the thermal energy at room temperature is calculated, S becomes 300 square nanometers or less. Of course, the required area of the tunnel junction varies depending on the thickness of the oxide film. However, it is necessary that the area of the tunnel junction is not more than 1000 square nanometers in consideration of the limit of thinning the oxide film.

[0048]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a semiconductor memory device and a method of manufacturing the same according to the present invention will be described below in detail with reference to the drawings.

<Embodiment 1> One embodiment of a semiconductor memory device and a method of manufacturing the same according to the present invention will be described with reference to FIGS. 9 and 10 are cross-sectional views showing a method of manufacturing a semiconductor memory device according to the present invention using a gate electrode of a read MOS transistor as a storage node utilizing Coulomb shielding in the order of main steps.
And FIG. 12 are a plan view and a sectional view sequentially showing the next step of FIG.

In FIG. 9A, reference numeral 1 denotes a p-type silicon substrate, and the p-type silicon substrate 1 has a specific resistance of 10 Ω · cm as an example. After forming an element isolation region (not shown) on the p-type silicon substrate 1 by using a normal LOCOS method, an oxide film 2 having a thickness of 10 nm is formed by a wet oxidation method at 850 ° C. for 30 minutes.
The structure shown in FIG. 9A is obtained.

Next, after polycrystalline silicon 3 is deposited to a thickness of 50 nm by a normal CVD method, phosphorus is diffused at 875 ° C. for 20 minutes. Further, a silicon oxide film 4 is deposited to a thickness of 50 nm by the CVD method to obtain a structure shown in FIG.

Thereafter, the silicon oxide film 4 is processed by photolithography and anisotropic dry etching, and the polycrystalline silicon 3 is etched using the silicon oxide film 4 as a mask, as shown in FIG. Structure. The polycrystalline silicon 3, that is, the first electrode functions as a writing electrode described later.

Next, as shown in FIG. 9D, a 3 nm-thick oxide film 5 is formed as an insulating film through a thermal oxide film forming step at 850 ° C. for 5 minutes in a steam atmosphere. This oxide film 5 functions as a tunnel oxide film because of its thickness. Of course, this insulating film may be an insulating film other than the silicon oxide film 5, for example, a silicon nitride film.

Further, as shown in FIG. 9E, a 50 nm-thick polycrystalline silicon 6 is deposited on the oxide film 5 by a CVD method, and phosphorus is diffused at 875 ° C. for 20 minutes.
Next, as shown in FIG.
Is anisotropically dry etched to leave the silicon film 6 only on the side walls. This sidewall silicon film 6 functions as a gate electrode. Further, a tunnel junction is formed by the first electrode 3 and the gate electrode 6 sandwiching the oxide film 5 having a thickness of 3 nm.

Then, as shown in FIG. 10A, a thermal oxide film forming step is performed again at 850 ° C. for 5 minutes in a steam atmosphere, so that an oxide film 7 having a thickness of 3 nm is formed as an insulating film.
To form This oxide film 7 also functions as a tunnel oxide film similarly to oxide film 5 because of its thickness. Of course, this insulating film may be an insulating film other than the silicon oxide film, for example, a silicon nitride film.

Further, polycrystalline silicon 8 having a thickness of 50 nm is deposited on oxide film 7 by the CVD method.
After performing the phosphorus diffusion for a minute, the polycrystalline silicon 8 is anisotropically dry-etched, as shown in FIG.
The polycrystalline silicon 8 is left only on the side walls. This sidewall silicon film 8 also functions as a gate electrode. Therefore, the thickness 3n
A tunnel junction is also formed by gate electrode 6 and gate electrode 8 sandwiching oxide film 7 of m. As a result, the serially connected electrodes 3, 6, 8 insulated from each other by the tunnel oxide films 5, 7 form a tunnel junction row MTJ. Although not shown, the tunnel oxide film forming step of FIG. 10A and the side wall gate electrode forming step of FIG. 10B may be sequentially repeated a required number of times to increase the number of tunnel junction rows. In that case, there is an effect that the leak current decreases.

Next, as shown in FIG. 10C, an oxide film 9 having a thickness of 8 nm is formed as an insulating film through a thermal oxide film forming step at 850 ° C. for 20 minutes in a steam atmosphere. . Since oxide film 9 is sufficiently thick, electron tunneling is not allowed. Of course, this insulating film may be other than the silicon oxide film, such as a silicon nitride film.

Further, as shown in FIG. 10D, a polycrystalline silicon 10 having a thickness of 50 nm is deposited on the oxide film 9 by a CVD method, and phosphorus is diffused at 875 ° C. for 20 minutes.

Subsequently, the polycrystalline silicon 10 is dry-etched by photolithography using a resist having a thickness of 1.5 μm to form a second electrode. At this time, the resist is not yet removed. Furthermore, polycrystalline silicon 1 with resist
The oxide film 9 is subjected to anisotropic dry etching of 8 nm using 0 as a mask (not shown). Further, using the resist as a mask, the polycrystalline silicon 8 is etched by 50 nm, and then the oxide film 7 is anisotropically dry etched by 3 nm. Further, the polycrystalline silicon 6 is etched by 50 nm, the resist is removed by an asher, and thermal oxidation is performed at 800 ° C. for 10 minutes. As shown in FIG. 11, arsenic ions 14 are formed at 20 keV.
For example, 3 × 10 ¹⁵ pieces / cm ^{2 are} implanted. Of course, these n
The type impurity region may be formed using phosphorus ions. In FIG. 11A, reference numeral 12 is LOC.
FIG. 11B shows an element isolation region formed by the OS method, that is, an element isolation oxide film, and FIG. 11B is a sectional structural view of a portion indicated by line AA ′ in FIG.

Thus, as shown in FIG. 12, the source / drain regions 1 are self-aligned with the gate electrodes 6 and 8.
1 is formed. The gate electrode 8 becomes a storage node. Further, an annealing process is performed in a nitrogen atmosphere at 800 ° C. for 10 minutes to obtain a structure shown in FIG. FIG.
FIG. 2B is a cross-sectional structural view of a portion indicated by line BB ′ in the plan view of FIG. In FIG. 12A, the oxide films 2 and 5 on the source / drain regions 11 are omitted and shown in a see-through manner.

After that, PSG (Phosp
horous silicate glass)
Deposition by the VD method to form an interlayer insulating film, contact holes are opened by photolithography and anisotropic dry etching, a metal such as aluminum is deposited, and a wiring pattern or the like is formed by photolithography to achieve integration. Semiconductor memory device can be obtained.

In this embodiment, the electrodes 3, 6, and 8 form a tunnel junction line MTJ connected in series, and the electrodes 8, 10 form a gate capacitance Cg connected in series with the tunnel junction line. FIG. 2 shows an equivalent circuit. In the equivalent circuit of FIG. 2, the terminal W on the gate capacitance Cg side
That is, the second electrode 10 is grounded, and a voltage that causes electron tunneling is applied to the terminal W ′ on the side of the capacitor C of the tunnel junction row, that is, the first electrode 3. Storage node MN goes high,
If a reverse voltage is applied between the terminals WW ', a tunnel occurs in the reverse direction and the storage node MN goes low. Therefore, according to the high or low state of the storage node MN, the MOS transistor Q
₁ is in the on state or the off state, the terminals R ₁ -R
By detecting the current flowing between the _two, the state of the storage node MN can be known. That is, it can operate as a memory cell.

As described in the operation section, the feature of the semiconductor memory device according to the present invention is that the storage node of the semiconductor memory device utilizing the Coulomb shield is changed to the read MOS transistor by utilizing the side wall film forming technology. The point is that it is constituted by a gate electrode. As a result, there is no need to draw the electrodes of the storage node as in the conventional example, and the capacity of the storage node can be extremely reduced. The operation at room temperature as well as the operation at 77K using liquid nitrogen is possible. It is. In addition, since a semiconductor memory device using such Coulomb shielding controls injection of one electron, a statistical fluctuation in the number of electrons, which becomes a problem when miniaturizing a so-called existing DRAM or the like, becomes a problem. Can be suppressed, and low-voltage operation with extremely fine dimensions, for example, 0.
Operation at 1V is possible.

In this embodiment, the description has been made using the p-type substrate. However, if all the polarities are changed, the p-type substrate using the n-type substrate is used.
It goes without saying that a memory utilizing Coulomb shielding by a channel MOSFET can be realized.

<Embodiment 2> Referring to FIGS. 13 to 15,
Another embodiment of the semiconductor memory device according to the present invention will be described. FIGS. 13 to 15 are diagrams for explaining an embodiment in which the semiconductor memory device shown in the first embodiment is used as a memory cell of a memory array.

When the semiconductor memory device utilizing the Coulomb shield of the first embodiment is used as a memory array, there is a point to be noted. As explained in the section of the action, the storage node MN is in the always on the MOS transistor Q ₁ for reading when high. Generally, in a storage array, multiple storage nodes are high,
These are in a state where current flows. At this time, when an off-state memory cell is read by the read line, a closed loop is formed through a plurality of on-state memory cells, and the off-state memory cell is on. It may be read as if. For this reason, it is necessary to insert another switching transistor in the read line so that even when the storage node MN is in the on state, the current does not flow in the off state of the entire memory cell.

FIG. 13 is an explanatory view of a memory cell in which another switching transistor is inserted in the read line.
(A) is a plan view of the element, (b) is a cross-sectional view of a portion indicated by line AA 'in the plan view, and (c) is a cross-sectional view of a portion indicated by line BB' in the plan view. FIG. 14 is an equivalent circuit diagram of a memory cell. Read MOS transistor Q ₁
And another gate electrode 10 of the switching MOS transistor Q ₂ to which led to series' is, MOS transistor Q ₁
The processing may be performed at the same time when the second electrode 10 is formed.
Although two memory cells MC1 and MC2 sharing the first electrode 3 are shown in FIG. 13, one memory cell is shown in the equivalent circuit of FIG. This is because, as can be seen from the manufacturing process of the first embodiment, when one memory cell is to be formed, two memory cells are simultaneously formed. As shown in the equivalent circuit of FIG. 14, by grounding the source of the MOS transistor to Q ₁ memory cell, the gate capacitance Cg-side terminals and the tunnel junction sequence MT
The J-side terminals are write terminals W and W ′, respectively.
The drain terminal of the gate electrode side terminal and the transistor Q ₂ of the transistor Q ₂ respectively and terminals R and R 'for reading. Therefore, as shown in FIG. 13, W corresponds to the second electrode 10, the common terminal W 'corresponds to the first electrode 3, and R corresponds to the gate electrode 10'.

Next, the memory cell M thus configured
The operation of C1 and MC2 will be described. First, a case where data is written to the memory cell MC1 will be described with reference to FIGS. The storage node MN of the memory cell MC1, the write high ( "1") and low ( "0") applies a voltage pulse to be applied to between the write terminal W ₁ and W ', as shown in FIG. 15. That is, when writing high, after giving high to terminal W ₁ row, the common terminal W 'for writing to both low. This allows
Electron tunneling occurs from the first electrode 3 side to the gate electrode 8 side, and the electrons are Coulomb-shielded. Incidentally, as written into the memory cell MC2 shown in FIG. 13 (a) at this time does not occur, the terminal W ₂ of the memory cell MC2 common terminal W '
The same voltage pulse as above is applied. Also, the readout terminal R
₁ , R ₂ , R ₁ ′, R ₂ ′ are kept at low level.

[0069] Similarly, when writing a row, the high to the write terminal W _1, after giving low to common terminal W ', which are both low. As a result, a tunnel of electrons in the opposite direction occurs from the gate electrode 8 side to the gate electrode 3 side. At this time, the terminal W ₂ of the memory cell MC2 and the read terminals R ₁ , R ₂ ,.
R ₁ ′ and R ₂ ′ are all held at low level.

To read the written high and low states, it is sufficient to select the read terminals R and R 'and perform current sensing. For example, To read the state of the memory node MN of the memory cell MC1, may be detected current flowing depending on the state of the memory node MN at terminal R ₁ 'giving high to terminal R _1. Note that the terminals R ₂ ,
R ₂ 'are both held low.

The memory cells MC1 and MC2 forming a pair
As can be seen from the structure shown in FIG. 13, since the writing common terminal W ′, that is, the first electrode 3, extends over the respective drain / source diffusion layers 11 via the gate oxide films 2 and 5, Of the MOS transistor. However, the parasitic MOS transistor does not operate by maintaining the potential relationship in the above-described write and read operations.

Therefore, using the memory cell according to the present invention,
A desired storage capacity can be obtained by arranging the memory array in an array. In the present embodiment, the memory cells MC1 and MC2 are operated separately, but the write terminals W ₁ and W ₂ and the read terminals R ₁ , R ₂ ,
R ₁ ′ and R ₂ ′ are connected to each other,
Needless to say, MC2 may be used as one memory cell. In that case, the driving capability of the memory cell is improved. Alternatively, when forming the drain / source layer 11 by ion implantation, the memory cell MC2 side portion may be masked so that the ion implantation layer is not formed, and only one memory cell MC1 may be used.

<Embodiment 3> Referring to FIGS. 16 to 22,
Another embodiment of the semiconductor memory device and the method of manufacturing the same according to the present invention will be described. FIG. 16 is a sectional structural view showing a method of manufacturing a semiconductor memory device according to the present invention using a gate electrode of a read MOS transistor as a storage node utilizing Coulomb shielding, in the order of main steps.
7 to 22 are a sectional structural view and a plan view sequentially showing the next step of FIG. In the first embodiment, the same components as those shown in FIGS. 9 to 12 are denoted by the same reference numerals and will be described below.

As shown in FIG. 16A, the specific resistance 10
Normal LOC for p-type silicon substrate 1 of Ωcm
After forming an element isolation region (not shown) using the OS method,
A 10 nm gate oxide film 2 is formed by a wet oxidation method at 850 ° C. for 30 minutes.

Next, polycrystalline silicon 3 is deposited on gate oxide film 2 by, eg, CVD to a thickness of 50 nm, and then 875.
Diffusion of phosphorus at 20 ° C. for 20 minutes. Further, a silicon oxide film 4 is deposited to a thickness of 50 nm by the CVD method to obtain a structure shown in FIG.

Thereafter, the silicon oxide film 4 is processed by photolithography and anisotropic dry etching, and the polycrystalline silicon 3 is etched using the silicon oxide film 4 as a mask to obtain the structure shown in FIG. Becomes At this time, the pattern interval x between the aligned polycrystalline silicon 3 is the same as the sidewall oxide film 5 formed on the side wall polycrystalline silicon 6 described later.
It is a distance where comrades do not connect. Since the capacity cannot be increased for sufficient operation at room temperature, the interval x is 0.1 μm.
The following is preferred.

Next, as shown in FIG. 16D, a 3 nm-thick oxide film 5 is formed as an insulating film again through a thermal oxide film forming step at 850 ° C. for 5 minutes in a steam atmosphere. This oxide film 5 functions as a tunnel oxide film because of its thickness. Of course, this insulating film may be an insulating film other than the silicon oxide film, for example, a silicon nitride film.

Further, a side-wall polycrystalline silicon film 6 having a thickness of 50 nm is formed, and the polycrystalline silicon film 6 is processed by photolithography and anisotropic dry etching to obtain a structure as shown in FIG. Here, FIG. 17A is a plan view at this time, and it can be seen that the side wall polycrystalline silicon film 6 is formed only in a very narrow region. Reference numeral 12 denotes an element isolation region, that is, an element isolation oxide film formed by the LOCOS method, and FIG. 17B shows A in FIG.
It is sectional drawing of the part shown by A 'line.

Next, a 3 nm-thick oxide film 7 is formed as an insulating film through a thermal oxide film forming step at 850 ° C. for 5 minutes in a water vapor atmosphere to obtain the structure shown in FIG. This oxide film 7 also functions as a tunnel oxide film like oxide film 5. Of course, this insulating film may be other than the silicon oxide film, such as a silicon nitride film.

Further, polycrystalline silicon 8 having a thickness of 50 nm is deposited on oxide film 7 by the CVD method.
After the diffusion of phosphorus for one minute, the polycrystalline silicon 8 is buried in the grooves between the polycrystalline silicons 3 arranged by a so-called etch-back process, and then photolithography and dry etching using a 1.5 μm thick resist Thus, the polycrystalline silicon 8 is processed to obtain a cross-sectional structure as shown in FIG. Next, as shown in the figure, arsenic ions 14 are implanted at 20 keV, for example, at 3 × 10 ¹⁵ ions / cm ² .
Of course, these n-type impurity regions may be formed using phosphorus ions. This n-type impurity region is used for reading M
Become the source and drain diffusion layer of the OS transistor Q _1. FIG. 19B is a cross-sectional view of the portion indicated by the line AA ′ in FIG.

Next, by performing annealing in a nitrogen atmosphere at 850 ° C. for 10 minutes, as shown in FIG.
Source / drain regions 11 are formed in self-alignment with gate electrode 8. In FIG. 20A, the oxide films 2, 5, and 7 on the source / drain regions 11 are omitted and shown in a transparent manner.

Further, an oxide film 9 having a thickness of 8 nm is formed as an insulating film through a thermal oxide film forming step at 850 ° C. for 5 minutes in a steam atmosphere, as shown in FIG. This oxide film 9
Is thick enough that electron tunneling is not allowed. Of course, this insulating film may be a silicon nitride film other than the silicon oxide film.

Next, after polycrystalline silicon 10 is deposited on oxide film 9 by 50 nm by CVD, phosphorus is diffused at 875 ° C. for 20 minutes, and photolithography using a 1.5 μm thick resist is performed. Then, the polycrystalline silicon 10 is dry-etched, and as shown in FIG. 22, the polycrystalline silicon 10 serving as a second electrode is formed so as to cover the polycrystalline silicon 8 embedded in the groove between the aligned polycrystalline silicon 3. To form FIG. 22A is a plan view, and FIG. 22B is a cross-sectional view of a portion indicated by line AA ′ in FIG.

Thereafter, a silicon oxide film such as a PSG film is deposited to a thickness of 200 nm by an LPCVD method to form an interlayer insulating film. Further, a contact hole is opened by photolithography and anisotropic dry etching, and a metal such as aluminum is formed. After vapor deposition, a wiring pattern or the like is formed by photolithography, whereby an integrated semiconductor memory device can be obtained.

The difference from the first embodiment is that the gate electrodes 3
That is, the tunnel junction row MTJ is formed in a narrow space between the first electrodes, and the capacitance C of the tunnel junction row MTJ can be further reduced as compared with the structure shown in the first embodiment. Room temperature operation of the memory is further facilitated.

In this embodiment, the description has been made using the p-type substrate. However, it is needless to say that a memory using Coulomb shielding by a p-channel MOSFET using an n-type substrate can be realized if all polarities are changed.

<Embodiment 4> Referring to FIGS. 23 to 29,
Another embodiment of the semiconductor memory device and the method of manufacturing the same according to the present invention will be described. 23 to 29 show a read MOS as a storage node using Coulomb shielding.
4A and 4B are a plan view and a cross-sectional view illustrating a method for manufacturing a semiconductor memory device according to the present invention using a gate electrode of a transistor in the order of main processes. Each cross-sectional view (b) is a cross-section of a portion indicated by the line AA ′ shown in each plan view (a). In the first embodiment, the same components as those shown in FIGS. 9 to 12 will be described with the same reference numerals. Here, the manufacturing method until the structure shown in FIG. 23 is obtained is described in the first embodiment with reference to FIGS. 9 (a) to 10 (b).
Since the manufacturing method is the same as that described above, the subsequent processes will be described.

From the state shown in FIG. 10B, a resist 13 having a thickness of 1.5 μm is applied, exposed and developed, and the pattern of the resist 13 as shown in FIG. Get.

Next, using the resist 13 as a mask, the side wall silicon film 8 is etched to form the resist 13 in the region surrounded by the element isolation region 12 as shown in FIG.
In this state, the portion of the tunnel oxide film 7 not covered with is exposed.

Further, the tunnel oxide film 7 is etched by using the resist 13 as a mask as it is. As shown in FIG. 25, the portion not covered with the resist 13 has the tunnel oxide film 5 and the side wall silicon film 6 exposed. And

Thereafter, the side wall silicon film 6 is etched using the resist 13 as a mask to leave only the tunnel oxide film 5 exposed in the region surrounded by the element isolation region 12 as shown in FIG. . Then, 20ke
Arsenic ions 14 are implanted, for example, at 3 × 10 ¹⁵ / cm ² with V, and an n-type impurity region (not shown) is formed in a self-aligned manner with respect to the side wall gate electrodes 6 and 8 covered with the resist 13. Of course, these n-type impurity regions may be formed using phosphorus ions. This n-type impurity region becomes the source / drain of the read MOS transistor.

Next, the resist 13 is removed to leave the tunnel oxide film 7 and the side wall silicon film 8 exposed by the resist 13 as shown in FIG. Thereafter, an oxide film 9 is deposited to a thickness of 10 nm by an LPCVD method at 850 ° C. in a nitrogen atmosphere for 10 minutes by a LPCVD method, and is covered with the oxide film 9 as shown in FIG.

Subsequently, a polycrystalline silicon film 10 is deposited to a thickness of 50 nm by LPCVD, and the polycrystalline silicon 10 is etched by photolithography using a resist having a thickness of 1.5 μm to form a second electrode. Then, the structure shown in FIG. 29 is obtained. 29 (c) is the same as (a) in FIG.
It is sectional drawing of the part shown by the line. The source / drain 1 of the read MOS transistor is self-aligned with the side wall silicon film 8 forming the gate electrode serving as a storage node.
It can be seen that No. 1 is formed.

In the first embodiment, the gate electrode of the read MOS transistor is formed by depositing all necessary films and then etching them sequentially from the top.
If the etching selectivity is not sufficient, the processing may be difficult due to the substrate 1 being scraped. On the other hand, in the case of the present embodiment, the gate electrode 6 of the read MOS transistor is formed after the formation of the second side wall silicon film 8.
Since the etching of No. 8 is performed, it is an effective manufacturing method even when the selectivity by the material of the dry etching is not sufficient as compared with the case of the first embodiment.

Although the present embodiment has been described using the p-type substrate, if all the polarities are changed, the p-type substrate using the n-type substrate may be used.
It goes without saying that a memory utilizing Coulomb shielding by a channel MOSFET can be realized.

The preferred embodiments of the semiconductor memory device and the method of manufacturing the same according to the present invention have been described above. However, the present invention is not limited to the above embodiments. Of course, various design changes can be made without departing from the spirit of the present invention.

[0097]

As is clear from the above-described embodiment, according to the present invention, in a memory utilizing the Coulomb shielding phenomenon, the gate capacitance C is increased by using a silicon LSI process.
g, the capacitance C of the tunnel junction array MTJ, and the parasitic capacitance Cs
Is formed small and the gate electrode itself of the read MOS transistor is used as a storage node, so that the operating temperature of the memory using the conventional Coulomb shielding phenomenon is only 30 mK, whereas the operating temperature of the Coulomb shielding according to the present invention is only 30 mK. A semiconductor memory utilizing the phenomenon can operate satisfactorily not only at a temperature of 77 K using liquid nitrogen but also at room temperature.

Therefore, it is possible to realize a semiconductor memory utilizing the Coulomb shielding phenomenon which does not require refreshing and which can operate at room temperature and at a low voltage, which is superior in cost and ease of use as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a view showing one embodiment of a semiconductor memory device according to the present invention, wherein (a) is a sectional view and (b) is a bird's-eye view.

FIG. 2 is an equivalent circuit diagram of the semiconductor memory device according to the present invention shown in FIG.

FIG. 3 is a diagram illustrating the principle of Coulomb shielding;
(A) is an equivalent circuit diagram in which a constant current source is connected to the tunnel junction, and (b) is a characteristic diagram showing a relationship between accumulated charge of the tunnel junction capacitance and charging energy.

FIGS. 4A and 4B are diagrams illustrating the influence of external impedance on Coulomb shielding. FIG. 4A shows the accumulated charge before and after the tunnel and the range of Coulomb shielding when the external impedance is infinite, and FIG. It is a figure which shows the range of the accumulated electric charge before and behind a tunnel and Coulomb shielding in the case of a finite case.

FIG. 5 is a conceptual diagram illustrating a memory using Coulomb shielding.

FIG. 6 is a diagram illustrating an operation principle of a memory using Coulomb shielding.

FIGS. 7A and 7B are conceptual diagrams in which an inversion layer is used for a storage node of a memory using Coulomb shielding; FIG. 7A is a schematic cross-sectional structure diagram of a memory cell; FIG.
FIGS. 3A and 3B are a cross-sectional structure diagram and an equivalent circuit diagram illustrating a configuration for extracting a potential of a storage node. FIGS.

FIG. 8 is another conceptual diagram in which an inversion layer is used for a storage node of a memory using Coulomb shielding, in which (a) is a sectional structural diagram and (b) is an equivalent circuit diagram.

FIG. 9 is a view showing one embodiment of the method for manufacturing the semiconductor memory device according to the present invention shown in FIG. 1, and is a cross-sectional view in the order of main steps.

FIG. 10 is a cross-sectional view showing, in order, the main steps next to the steps shown in FIG. 9 in the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 11 is a diagram illustrating a step subsequent to the step shown in FIG. 10 in the method for manufacturing a semiconductor memory device according to the present invention;
(A) is a plan view, and (b) is a cross-sectional view of a portion indicated by an AA ′ line in the plan view.

FIG. 12 is a diagram illustrating a step subsequent to the step illustrated in FIG. 11 in the method for manufacturing a semiconductor memory device according to the present invention;
(A) is a plan view, and (b) is a cross-sectional view of a portion indicated by a line BB ′ in the plan view.

FIGS. 13A and 13B are diagrams showing another embodiment of the semiconductor memory device according to the present invention, wherein FIG. 13A is a plan view, and FIG.
A cross-sectional view of the portion indicated by the line A ′, FIG.
It is sectional drawing of the part shown by the B 'line.

14 is an equivalent circuit diagram of the memory cell shown in FIG.

FIG. 15 is a voltage waveform diagram for describing a data write operation of the memory cell shown in FIG.

FIG. 16 is a view showing another embodiment of the semiconductor memory device according to the present invention, wherein (a) to (d) are cross-sectional views shown in the order of main manufacturing steps.

FIG. 17 is a diagram illustrating a step subsequent to the step shown in FIG. 16 in the method for manufacturing a semiconductor memory device according to the present invention;
(A) is a plan view, and (b) is a cross-sectional view of a portion indicated by an AA ′ line in the plan view.

FIG. 18 is a cross-sectional view for explaining a step subsequent to the step shown in FIG. 17 in the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 19 is a diagram illustrating a step subsequent to the step shown in FIG. 18 in the method for manufacturing a semiconductor memory device according to the present invention;
(A) is a plan view, and (b) is a cross-sectional view of a portion indicated by an AA ′ line in the plan view.

20 is a view illustrating a step subsequent to the step shown in FIG. 19 in the method for manufacturing a semiconductor memory device according to the present invention;
(A) is a plan view, and (b) is a cross-sectional view of a portion indicated by a line BB ′ in the plan view.

FIG. 21 is a cross-sectional view for explaining a step subsequent to the step shown in FIG. 20 in the method for manufacturing a semiconductor memory device according to the present invention.

FIG. 22 is a diagram illustrating a step subsequent to the step shown in FIG. 21 in the method for manufacturing a semiconductor memory device according to the present invention;
(A) is a plan view, and (b) is a cross-sectional view of a portion indicated by an AA ′ line in the plan view.

FIG. 23 is a view showing still another embodiment of the method of manufacturing the semiconductor memory device according to the present invention, wherein FIG. 23 (a) is a plan view showing a step subsequent to the step shown in FIG. 10 (b), and FIG. A in the figure
FIG. 4B is a cross-sectional view of a portion indicated by line A ′.

FIG. 24 is a diagram illustrating a step subsequent to the step shown in FIG. 23 in the method for manufacturing a semiconductor memory device according to the present invention;
(A) is a plan view, and (b) is a cross-sectional view of a portion indicated by an AA ′ line in the plan view.

FIG. 25 is a diagram illustrating a step subsequent to the step shown in FIG. 24 in the method for manufacturing a semiconductor memory device according to the present invention;
(A) is a plan view, and (b) is a cross-sectional view of a portion indicated by an AA ′ line in the plan view.

FIG. 26 is a diagram illustrating a step subsequent to the step shown in FIG. 25 in the method for manufacturing a semiconductor memory device according to the present invention;
(A) is a plan view, and (b) is a cross-sectional view of a portion indicated by an AA ′ line in the plan view.

FIG. 27 is a view illustrating a step subsequent to the step shown in FIG. 26 in the method for manufacturing a semiconductor memory device according to the present invention;
(A) is a plan view, and (b) is a cross-sectional view of a portion indicated by an AA ′ line in the plan view.

FIG. 28 is a view illustrating a step subsequent to the step shown in FIG. 27 in the method for manufacturing a semiconductor memory device according to the present invention;
(A) is a plan view, and (b) is a cross-sectional view of a portion indicated by an AA ′ line in the plan view.

FIG. 29 is a view illustrating a step subsequent to the step shown in FIG. 28 in the method for manufacturing a semiconductor memory device according to the present invention;
(A) is a plan view, (b) is a cross-sectional view of a portion indicated by line AA 'in the plan view, and (c) is a cross-sectional view of a portion indicated by line BB' in the plan view.

[Explanation of symbols]

Reference Signs List 1 silicon substrate 2 silicon oxide film 3 polycrystalline silicon (first electrode) 4 silicon oxide film 5 silicon oxide film (tunnel oxide film) 6 polycrystalline silicon 7 silicon oxide film (tunnel oxide film) 8 ... polycrystalline silicon 9 ... silicon oxide film 10 ... polycrystalline silicon (second electrode) 10 '... polycrystalline silicon 11 ... impurity diffusion region 12 ... element isolation region (element isolation oxide film) 13 ... resist 14 ... arsenic ion C ... capacity Cg ... gate capacitance Cs ... parasitic capacitance MC1 ... memory cell MC2 ... memory cell MN ... storage node Q ₁ ... MOS transistor Q ₂ ... switching MOS transistor for reading tunnel junction sequence

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-58298 (JP, A) JP-A-7-86614 (JP, A) JP-A-7-273331 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) H01L 27/10 H01L 29/66 H01L 29/06

Claims (12)

(57) [Claims] 1. A semiconductor memory device having a tunnel junction row including at least one tunnel junction, a capacitor connected in series with the tunnel junction row, and a connection between the capacitor and the tunnel junction row as a storage node. A first electrode formed on a semiconductor substrate of the first conductivity type via an insulating film, a plurality of electrodes connected in series to the first electrode via the insulating film, and mutually insulated by the insulating film; The plurality of electrodes and a second electrode connected via an insulating film, the tunnel junction row, and the capacitor, and at least one of the plurality of electrodes that is to be a storage node A pair of second semiconductors formed in the semiconductor substrate in a self-aligned manner.
A semiconductor memory device including a reading transistor including a conductive impurity layer. 2. A method according to claim 1, wherein at least one of the plurality of insulating films interposed between the first electrode and the second electrode via the plurality of electrodes is an insulating film having a thickness capable of quantum mechanical tunneling of electrons. 2. The semiconductor memory device according to claim 1, wherein at least one is an insulating film having a thickness that does not allow quantum mechanical tunneling of electrons. 3. The method according to claim 1, wherein the plurality of electrodes are located on a side wall of the first electrode, and the insulating film insulating the plurality of electrodes from each other is a side wall insulating film formed on each electrode. 13. The semiconductor memory device according to claim 1. 4. The semiconductor memory device according to claim 1, wherein an area of each of the electrodes facing the first electrode and the plurality of electrodes is at most 1,000 square nanometers. 5. The semiconductor memory device according to claim 1, wherein the charging energy determined by the capacitance of the electrode serving as the storage node is larger than the thermal energy determined by the temperature. 6. The semiconductor device according to claim 1, wherein a potential of an electrode serving as a storage node among the plurality of electrodes has a hysteresis with respect to a potential applied between the first and second electrodes. 13. The semiconductor memory device according to claim 1. 7. The potential according to claim 1, wherein the potential of an electrode serving as a storage node among the plurality of electrodes has two stable values depending on the potential applied between the first and second electrodes. 3. The semiconductor memory device according to claim 1. 8. The semiconductor memory device according to claim 7, wherein the threshold voltage of the read transistor is a voltage value between two stable potentials of an electrode serving as the storage node. 9. The semiconductor memory device according to claim 1, wherein a switching transistor for turning on / off the current of said read transistor is connected in series with said read transistor. 10. A memory array in which any one of the semiconductor memory devices according to claim 1 is arranged in an array. 11. A step 1 for forming a gate oxide film on a surface of a semiconductor substrate of a first conductivity type including an element isolation oxide film, a step 2 for forming a first conductive film on the gate oxide film, A step 3 of forming an insulating film on the conductive film; a step 4 of patterning the first conductive film and the insulating film to form a first electrode having the insulating film on the upper surface; A step 5 of forming a first insulating film on the surface of the first electrode, a step 6 of forming a second conductive film on the side wall of the first electrode via the first insulating film, Step 7 of forming a second insulating film on the surface; and Step 8 of forming a third conductive film on the side wall of the first electrode via the second insulating film formed in Step 7; After repeating step 8 in the required number of times, a third insulating film having a thickness that does not allow electron tunneling is formed on the surface. Step 9, forming a fourth conductive film to be the second electrode on the surface, and forming the insulating film and conductive film formed in Step 10, Step 9, Step 8, Step 7, and Step 6 as required. A semiconductor comprising: a step of removing a portion while leaving the portion; and a step of forming an impurity of a second conductivity type in a semiconductor substrate of a first conductivity type in a self-aligned manner with respect to the required portion. A method for manufacturing a storage device. 12. A step 1 of forming a gate oxide film on a surface of a semiconductor substrate of a first conductivity type including an element isolation oxide film, a step 2 of forming a first conductive film on the gate oxide film, A step 3 of forming an insulating film on the conductive film; a step 4 of patterning the first conductive film and the insulating film to form a first electrode having the insulating film on the upper surface; A step 5 of forming a first insulating film on the surface of the first electrode, a step 6 of forming a second conductive film on the side wall of the first electrode via the first insulating film, Step 7 of forming a second insulating film on the surface; and Step 8 of forming a third conductive film on the side wall of the first electrode via the second insulating film formed in Step 7; A step 9 of forming a resist pattern at a required position after repeating the step 8 a required number of times, and Step 10 of removing the conductive film and the insulating film formed in Steps 8, 7 and 6 using the formed resist pattern as a mask, and removing the resist of the second conductivity type into the semiconductor substrate of the first conductivity type. Step 1 of forming a pattern in a self-aligned manner with respect to the required portion using a mask
Step 1 of forming a third insulating film having a thickness that does not allow electron tunneling on the surface after removing the resist pattern.
A step 13 of forming a fourth conductive film on the surface; and patterning the fourth conductive film formed in the step 13 to form a second conductive film.
A method for manufacturing a semiconductor memory device, comprising: a step 14 of forming an electrode.