JPH11195780A - Single electronic device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a metal-nano-crystal in a two-dimensional state to a specified depth at a uniform size in an insulating film of a mutually isolated pattern at the approximately constant interval, by aligning a plurality of conducting particles, which are formed in parallel with the boundary between a conducting substrate and an insulating film and have nanometer-size diameters on the same plane with the approximately same size. SOLUTION: In an SiO2 film 12 formed by a thermal oxidation process on the surface of an Si substrate 10, Sn ion is introduced at a specified energy and dose by ion implanting method. Self-organized nano-crystals 14 are aligned two-dimensionally, at an approximately constant height from an SiO2 /Si interface. Furthermore, the upper side of the SiO film 12 is covered sequentially with a first resist film 16 and a second resist film 18. An opening part 20A is formed on a resist film 18 of a formed photomask 20. An exposed part 22, corresponding to the opening part is developed and removed, and the resist film 16 under the part 22 is exposed. Resist patterns 16A and 18A are deposited, and an electronic pattern is obtained in the SiO2 film 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to the manufacture of electronic devices, and more particularly to a single electronic device including a so-called nanocrystal composed of conductive ultrafine particles arranged in an insulating film and a method of manufacturing the same. Wilkins et al. (R. Wilkins, E. Be
n-Jacob, RC Jaklevic, Phys. Rev. Lett. 63, 1989,
pp.801), since the discovery of a stepwise-quantized conductance in a system in which ultrafine metal particles are dispersed in an oxide film, research on single-electron devices applying so-called electron Coulomb blockade has been vigorous. It has been done. By using Coulomb blockade, an element that performs a switching operation using a quantum effect that appears in a tunnel current passing through a very small capacitance can be obtained. In addition, various logic circuits and memory circuits can be configured using these single electronic elements.

[0002]

2. Description of the Related Art FIGS. 1A and 1B show basic components of such a single electronic device. Referring to FIG. 1A, the charging energy E of a tunnel junction having a capacitance C is given by E = Q ² / 2C where Q is the amount of accumulated charge. When a single electron is tunneled, the accumulated charge is Q to Q-e
, So that the energy of the tunnel junction changes by ΔE = e (Q _c −Q) / C. Here, Q _c is a critical charge amount, and e /
2 (Q _c = e / 2).

[0003] Therefore, such tunneling when accumulated charge amount Q of bonding is less than the critical charge Q _c is would increase the bonding energy (ΔE> 0), the result electron tunneling is blocked Would. On the other hand, when a voltage (> e / 2C) is applied to the junction, Q becomes larger than Q _c and ΔE <0, so that tunneling of electrons becomes possible.

FIG. 1 (B) shows such a tunnel junction.
5 shows an operation characteristic curve (IV curve). Characteristics of FIG. 1 (B)
The curve shows the blockage due to this single electron effect.
An area appears. Such a single electron effect was observed
A single electron tunnels through a tunnel junction
Energy change ΔE (≒ e^Two/ 2C) is heat energy
Lugi k _BMust be much larger than T (e^Two/ 2
C @ k_BT) Therefore, the tunnel junction is
In this case, it is necessary to form the metal C so as to be very small.

[0005] It is difficult to produce such a minute capacitor by a conventional patterning method. For this reason, such a minute capacitor has conventionally been used in an insulating film such as a SiO ₂ film.
Attempts have been made to form so-called nanocrystal structures. In the nanocrystal structure, fine metal particles (metal nanocrystals) having a size of typically 10 nm or less are isolated from each other on substantially the same plane at substantially equal intervals in an insulating film such as the above-mentioned SiO ₂ . It is a structure arranged in a state.

Conventionally, attempts have been made to form a desired nanocrystal structure by depositing metal fine particles on an insulating film by sputtering or vapor deposition. However, in such a method, metal dots having a uniform size are mutually formed. It is very difficult to form them on the same plane in an isolated state.

[0007]

On the other hand, when a metal element is introduced into an insulating film by ion implantation,
It is relatively easy to form isolated nanometer-sized metal nanocrystals in an insulating film. For example, Hosono et al. (Hosono, H. et al., "Cross-sectional
TEM Observation of Copper-implanted SiO2 glass, "
J. Non-crystalline Solids, 143, 1992, pp.157-161)
See

[0008] The above known examples, the Cu atoms are ion-implanted at a dose of acceleration energy and 6 × 10 ¹⁶ cm ^-2 of 160keV into the SiO ₂ film, Cu further in the same SiO ₂ film
The atom is now converted to an acceleration energy of 35 keV and 2 × 10
By ion implantation at a dose of ¹⁶ cm ^-2 , the S
It reports that it is possible to form Cu ultrafine particles in an iO ₂ film in a state of being isolated from each other.

However, when ion implantation is performed with such a large acceleration energy, the distribution of the implanted metal ions, that is, the metal nanocrystals in the depth direction greatly varies in the insulating film, and a desired single ion is distributed. A structure suitable for an electronic device cannot be realized. For example, in such a structure in which the depth of metal nanocrystals varies, many layers of metal nanocrystals are formed, so that when an electric field is applied perpendicularly to the insulating film, electrons sequentially pass through the metal nanocrystals. It will pass by tunneling. Also,
The characteristics in FIG. 1B change depending on the depth in the insulating film, so that clear characteristics cannot be observed.

Therefore, the present invention has solved the above-mentioned problems,
It is a general object to provide a new and useful single electronic device and a method of manufacturing the same. A more specific object of the present invention is to form metal nanocrystals of nanometer size in a uniform size in an insulating film, isolated at substantially constant intervals from each other, and formed two-dimensionally at a predetermined depth. An object of the present invention is to provide a method for forming a nanocrystal, a single electronic device including the nanocrystal, and a method for manufacturing the same.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems.
And a conductive substrate as described in claim 1.
An insulating film formed on an electrically conductive substrate; and
Formed substantially parallel to the interface between the substrate and the insulating film.
A plurality of conductive particles having a diameter of nanometer size
And a single electron comprising an electrode formed on the insulating film
In the device, the plurality of conductive particles are substantially equal to each other
Having a size and substantially coplanar in the insulating film.
A single electronic device characterized by an array
Or the plurality of conductive particles as described in claim 2.
Is formed in the strain accumulation region in contact with the substrate in the insulating film.
The single electronic device according to claim 1, wherein the single electronic device is formed.
Or the conductive material according to claim 3.
2. The method of claim 1, wherein the particles are nanocrystals.
Or by a single electronic device according to claim 2 or according to claim 4
As described, the conductive substrate is formed of a degenerated Si substrate.
The insulating film is made of SiO_TwoFilm or SiN film
The method according to any one of claims 1 to 3, wherein
By a single electronic device or as described in claim 5
In addition, the conductive particles include Cu, Fe, Ag, Au, S
selected from the group consisting of n, Pt, In, Sb and Ga
5. The metal element according to claim 1, wherein
By a single electronic device according to any one of the above, or
As described in claim 6, further comprising the conductive particles and
And a gate electrode that is electrostatically coupled to the substrate.
One electronic device is characterized by forming a single electron transistor.
The single unit according to any one of claims 1 to 5, wherein
By electronic device or as described in claim 7
The insulating film and the electrode are defined by a pair of opposing side walls.
Forming a gate structure, wherein said single electronic device is further
Diffusion into the substrate corresponding to each of the pair of side walls
Area, comprising a memory device.
The single electronic device according to any one of claims 1 to 5,
Or the insulating film as described in claim 8.
Comprises a first insulating film and a second insulating film;
Conductive particles of the first insulating film and the second insulating film
8. The method according to claim 1, wherein the first electrode is formed near the interface.
By a single electronic device according to any one of the above, or
As described in claim 9, the first insulating film and the second insulating film
Insulating film is a film of the same composition formed at different temperatures
9. The single electronic device according to claim 8, comprising:
Or as described in claim 10, the first
The second insulating film has a different composition from that of the second insulating film.
9. The single electronic device according to claim 8, further comprising:
Or formed on a substrate as described in claim 11.
A doping step of introducing a metal element into the insulating film;
By diffusing the metal element introduced into the insulating film,
In the edge film, along the interface between the insulating film and the substrate,
Noble metal particles are isolated from each other
For manufacturing a single electronic device, including an annealing process
In the method, the doping step may be performed in the insulating film.
The concentration of the metal element in the substrate and at the interface
Is executed to be substantially zero.
A method of manufacturing a single electronic device, or according to claim 12
As described, the doping step includes the step of
Including an ion implantation step of introducing into the insulating film,
In the ion implantation step, the concentration of the metal element in the insulating film is
Is substantially zero in the substrate and at the interface
And the depth distribution of the metal element has a sharp maximum.
Characterized by being executed with acceleration energy having
The method of manufacturing a single electronic device according to claim 11, further comprising:
The substrate may be a Si substrate.
And the insulating film is made of SiO_TwoIs characterized by consisting of
A method of manufacturing a single electronic device according to claim 11 or claim 12.
By said method or as described in claim 14
The genus elements are Cu, Fe, Ag, Au, Sn, Pt, I
n, Sb and Ga.
The method according to any one of claims 11 to 13, wherein
According to a method of manufacturing a single electronic device or as claimed in claim 15.
As noted, the metal element is Sn and the ion
In the implantation step, the acceleration energy is set to about 20 keV or less.
13. The single electronic device according to claim 12, wherein
A method for manufacturing a slave device, or according to claim 16.
As described above, the metal element is Sb,
About Sb is about 1 × 10¹³cm ^-2With the above dose,
13. The unit according to claim 12, wherein the compound is introduced into a peripheral membrane.
18. A method for manufacturing an electronic device or according to claim 17.
As described above, in the ion implantation step, Sb is reduced to about 1 × 10
¹⁶cm^-2The introduction into the insulating film with the above dose is
17. The method of manufacturing a single electronic device according to claim 16, wherein
Or the ion as described in claim 18.
In the implantation step, the Sb is reduced to about 1 × 10¹⁷cm^-2More do
2. The semiconductor device according to claim 1, wherein the insulating film is introduced into the insulating film by a step.
A method for manufacturing a single electronic device according to claim 6, or claim
As described in 19, the annealing treatment is performed at about 400
2. The method according to claim 1, wherein the heating is performed at a temperature of not less than ° C.
Manufacturing of the single electronic device according to any one of 1 to 18
By a manufacturing method or as described in claim 20
The insulating film is composed of a first insulating film and a second insulating film thereon.
Wherein the doping step includes the step of:
Concentrates near the interface between the first insulating film and the second insulating film.
20. The method according to claim 11, wherein the steps are executed as follows.
That is, according to the method for manufacturing a single electronic device according to any one of the above,
Or the first absolute value, as described in claim 21.
The edge film and the second insulating film are formed at different temperatures.
21. The single electron of claim 20, wherein the single electron is formed.
According to the method of manufacturing the device or as described in claim 22.
As described above, the first insulating film and the second insulating film
21. The composition according to claim 20, which has different compositions.
A method for manufacturing a single electronic device according to claim 2, or claim 2.
As described in 3, the ion implantation step may include the step of:
13. The method is performed obliquely with respect to
23. Manufacture of a single electronic device according to any one of claims 22 to 22
Solve by the method. [Operation] FIG.⁺Heat on the mold, ie degenerate Si substrate
SiO formed about 15 nm thick by oxidation_Twofilm
Inside, Sn atoms were accelerated at an energy of 10 keV and a dose of 5 ×
10^Fifteencm^-2TEM cross-sectional photograph immediately after ion implantation
is there.

Referring to FIG. 2, in the ion implantation at such a low accelerating voltage, Sn atoms are concentrated at a substantially central portion A in the thickness direction in the thermal oxide film. The distribution of Sn atoms in the thermal oxide film shown in FIG. That is, almost no Sn atoms reach the inside of the Si substrate or the interface (SiO ₂ / Si) between the thermal oxide film and the Si substrate.

On the other hand, the TEM photograph of FIG.
In addition, it shows that there is a sharp concentration of Sn atoms at a position B adjacent to the SiO ₂ / Si interface in the thermal oxide film. This suggests that there is a region where strain is formed adjacent to the interface in the thermal oxide film, and Sn atoms are concentrated and captured in such a portion.

FIG. 4 shows a TEM cross-sectional photograph similar to FIG. 2 when the structure of FIG. 2 is annealed at 900 ° C. for 10 minutes. Referring to FIG. 4, the concentration of Sn atoms corresponding to the position A disappears, the Sn atoms aggregate at a position C near the position B, and the Sn nanocrystal having a size of about 5 nm is formed by the SiO _2. It can be seen that many are formed along the / Si interface. Further, each Sn nanocrystal has a spherical shape of substantially the same size, and the SiO ₂ /
It can be seen that they are two-dimensionally arranged at substantially the same height from the Si interface, that is, in a layered manner. Furthermore, lattice images have been confirmed for individual Sn nanocrystals.

At the position C, a strong compressive strain is formed in the thermal oxide film due to the thermal oxidation process of the Si substrate, and diffusion of Sn atoms is prevented in the strain accumulation region, and the diffusion of the Sn atom is prevented. The atoms are believed to aggregate to form Sn nanocrystals. FIG.
FIG. 3 is a diagram schematically showing the structure of FIG.

Referring to FIG. 5, an SiO ₂ film 12 is formed on an n ⁺ -type degenerated Si substrate 10 by thermal oxidation to a thickness of 5 to 40 nm.
The SiO ₂ film 12 has a thickness of
Sn ultrafine particles 14 having a diameter of about 5 nm corresponding to n nanocrystals are formed along the interface with the Si substrate 10 and at a substantially constant height from the interface and separated from each other. As can be seen from FIG. 5, the Sn ultrafine particles 14
The iO ₂ film 12 is arranged approximately two-dimensionally at a position closer to the interface than at the center in the depth direction and corresponding to position B in FIG. 2 or position C in FIG.

Accordingly, the present invention provides a single electronic device using a metal nanocrystal formed as a single layer along the interface between a substrate and an insulating film in such an insulating film as an active portion.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIGS.
FIG. 7J is a view illustrating the method for manufacturing the single electronic device according to the first embodiment of the present invention; However, in the figure, parts corresponding to the parts described above are denoted by the same reference numerals, and description thereof will be omitted.

Referring to FIG. 6A, the Si substrate 1
0 on the SiO 2 surface by a thermal oxidation process._TwoMembrane 12
Has a thickness of 5-20 nm, typically as described above
It is formed to a thickness of 15 nm. Next, FIG.
In the step, the SiO_TwoSn in film 12 by ion implantation
, Acceleration of 20 keV or less, preferably 10 keV
Energy and 5 × 10^Fifteencm^-2Introduce at the dose.
In this way, Sn ions can be introduced with low acceleration energy.
As described above with reference to FIG. 2 or FIG.
The n atom is SiO _TwoA central portion A in the film 12 and the S
iO_Two/ Si concentrated at interface B. In addition,
Using high acceleration energy (for example, 160 keV)
Unlike the above case, the implanted Sn atoms form the SiO 2_Two/ Si
Only a few reach the substrate 10 through the interface
is there.

Next, in the step of FIG.
The structure of (B) is N_TwoIn an atmosphere at 900 ° C for 10 minutes
Neal, resulting in the implanted Sn ions
Are aggregated, and the diameter of the Sn ultrafine particles is about 5 nm.
The nanocrystal 14 is made of SiO _TwoIn the film, the position shown in FIG.
It is spontaneously formed at a position corresponding to the position C. First, FIG.
As described in Section 2, the self-assembled nano-scale
The listal 14 is made of the SiO_Two/ Si almost constant from the interface
Arrange two-dimensionally in height.

Further, in the step of FIG.
_{The two} films 12 are sequentially covered with a first resist film 16 and a second resist film 18. The resist film 16 is made of, for example, PM
Made of MA (polymethylmethacrylate), about 500n
m. On the other hand, the resist film 18 is, for example, a microposit S1300-31 (SHIPLEY FAR).
EAST company name) and is formed to a thickness of about 300 nm.

Next, in the step of FIG.
Is formed on the resist film 18 of FIG. 6D, and a portion 22 of the resist film 18 corresponding to the opening 20A is exposed through the mask pattern 20. 7F, the exposed portion 22 of the resist film 18 is developed and removed.
In the step (G), the underlying resist film 16 is exposed to ultraviolet light.

Further, the region 24 of the resist film 16 is removed by the step of developing the resist film 16 shown in FIG. 7G, and a resist pattern 16A is formed by the resist film 16.
Further, in the step of FIG. 8 (I), a conductor film 26 typically made of Al or an Al alloy is deposited on the structure of FIG. 7 (G) using the resist patterns 16A and 18A as a mask. 8 (J), the conductor film 26 on the resist patterns 16A and 18A is lifted off,
A structure in which the electrode pattern 26 is formed on the SiO ₂ film 14 is obtained.

The single electronic device of FIG. 8J operates as a single electron tunnel diode. FIG. 9 shows an equivalent circuit diagram of the device of FIG. Referring to FIG. 9, the single-electron tunnel diode has a capacitance C _A between the Si substrate 10 and the Sn nanocrystal 14 and a capacitance C _B between the Sn nanocrystal 14 and the electrode pattern 26 in series. connect, further in parallel with the capacitance C _a and C _B, has a structure obtained by inserting each tunnel resistance R _a and R _B.

FIG. 10 shows the single electron tunnel shown in FIG.
In the structure of the diode, SiO _TwoAbout the thickness of the film 12
The operating characteristics when the thickness is 10 nm are shown. However, FIG.
The horizontal axis is the mark between the substrate 10 and the electrode pattern 26.
Applied voltage, the left vertical axis represents current, and the right vertical axis represents
Indicates the conductance. Referring to FIG.
FIG. 1 shows the current-voltage characteristics of the secondary tunnel diode.
The current blockade region described in (B) is observed.
You. In addition, a clear oscillation was observed in the conductance,
In particular, a clear blockade was observed near the driving voltage of 0 V.
It is.

By using such a single-electron tunnel diode or a single-electron transistor in which a gate electrode is combined with the single-electron tunnel diode, various logic circuits and memory circuits can be configured. The metal element introduced by ion implantation into the SiO ₂ film is not limited to Sn, but may be Cu, Fe, Ag, Au, Pt, In,
It is also possible to use a metal element such as Ga. Even when these other elements are used, the acceleration energy at the time of ion implantation needs to be set so that the distribution of the implanted metal element is limited in the SiO ₂ film.

In the present invention, another insulating film such as a SiN film can be used instead of the SiO ₂ film. In the step of FIG. 6 (C), the heat treatment step of spontaneously aggregating the Sn atoms takes about 90 as described above.
It is necessary to perform at a temperature of about 0 ° C., generally at least 400 ° C. or higher. [Second Embodiment] In the first embodiment of the present invention described above,
By ion-implanting a metal element such as Sn into the insulating film on the substrate, nanocrystals suitable for a single electronic device could be formed in the insulating film. However, these metal elements are generally used in semiconductor devices. It is not used in manufacturing. In other words, these metal elements may be used in a wiring process or the like in the manufacture of a semiconductor integrated circuit device, but are not used in a process before a high-temperature heat treatment. On the other hand, in the step of forming the metal nanocrystal, a heat treatment at a high temperature such as 900 ° C. is indispensable. Therefore, when these metals are used, the device manufacturing line may be contaminated. When comparing the cross-sectional photograph of FIG. 2 with the cross-sectional photograph of FIG. 4, the concentration of Sn observed at the position A disappears in the state of FIG. 4 after the heat treatment, but some of the Sn atoms become SiO 2 during the heat treatment. _It is possible that the _two films have detached from the free surface to the outside.

Under these circumstances, the inventor of the present invention
In general, an attempt was made to form a nanocrystal in an insulating film using an element used as a dopant in a semiconductor integrated circuit manufacturing process. Of these, attempts to form nanocrystals using As and P have already been made.
It is shown that when these elements are used, the ultrafine particles formed in the insulating film are in an amorphous state and do not become nanocrystals.

On the other hand, the inventor of the present invention has found that when Sb is used as the metal element, a metal nanocrystal having no defect in the insulating film can be formed. Hereinafter, an experiment performed by the inventor of the present invention will be described. In the experiment in the present embodiment, the Si
A SiO ₂ film is formed on the substrate by thermal oxidation to a thickness of 500 nm, and Sb ⁺ ions are prevented from reaching the Si substrate in the formed SiO ₂ film in the ion implantation step corresponding to FIG. 40 keV acceleration energy and 1 ×
Ion implantation was performed at a dose of 10 ¹⁶ cm ^-2 . Further, the structure thus formed was annealed at 900 ° C. for 10 minutes in an annealing step corresponding to FIG.

FIG. 11 (A) shows a cross-sectional TEM photograph of the Sb nanocrystal thus formed. FIG.
Referring to (A), it can be seen that substantially spherical Sb ultrafine particles having a diameter of about 5 to 15 nm are formed apart from each other in the SiO ₂ film on the Si substrate. Sb formed
The ultrafine particles show a lattice image and are nanocrystals.

FIG. 11B shows a cross section T of an Sb nanocrystal formed when the dose of Sb ⁺ ions is increased to 1 × 10 ¹⁷ cm ⁻² in the ion implantation step.
An EM photograph is shown. However, the acceleration voltage for the ion implantation is set to 40 keV as in the case of FIG. Referring to FIG. 11B, when the implantation dose of Sb is increased, the maximum diameter of the formed Sb nanocrystal increases to about 25 nm.

According to the present invention, a conventional semiconductor device is manufactured.
Sb commonly used as a dopant in the process
Can be used in the ion implantation process to produce a single electronic device.
The structure can be stably and inexpensively performed. Also, S
b dose 1 × 10¹³cm ^-2The above range, for example, 1 ×
10¹⁶cm^-2Or 1 × 10¹⁷cm^-2Changed in the range
The size of the Sb nanocrystal to the desired value
Can be controlled.

In the above embodiment, the metal element is introduced into the insulating film by the ion implantation method. However, the introduction of the metal element is not limited to the ion implantation method. In this case, a method of introducing the metal element as a dopant may be used. Third Embodiment FIGS. 12A and 12B show a third embodiment of the present invention in which two basic components of the single electronic device of FIG. 1A are connected in series and a gate electrode is provided. 2 shows an equivalent circuit diagram and operating characteristics of a single electron transistor 30 according to an example.

Referring to the equivalent circuit diagram of FIG.
In single-electron transistor 30, junction and tunnel junction tunnel resistance is R ₁ in capacity C _1, the Sn nanocrystals 14 and the Al electrode between the substrate 10 and the Sn nanocrystals 14 in the configuration of FIG. 8 (J) 26 is connected in series with a tunnel junction having a junction capacitance of C ₂ and a tunnel resistance of R ₂ , and a bias voltage V is applied to both ends. Further, the intermediate node, the voltage signal U _g is supplied via a capacitor C _g.

In such a single electron transistor, FIG.
Coulomb blockade is established in the diamond-shaped region shown in (B), defined by two pairs of parallel lines passing through points -e / 2 and e / 2, so that when the operating point is at A, the current flows through the transistor. Although the current does not flow, when the operating point moves to B, one electron sequentially passes through the series-connected resonant tunneling diodes.

FIG. 13 corresponds to the equivalent circuit of FIG.
1 shows a structure of a single electron transistor 30. However,
In FIG. 13, the parts described above are denoted by the same reference numerals.
And the description is omitted. Referring to FIG.
The transistor 30 is a single electron diode shown in FIG.
Has a configuration similar to that of the single electron shown in FIG.
Diode SiO_TwoThe Al electrode 2 is provided on a part of the film 12.
6 and Si substrate 10, and Sn nanocrystal 14
12 (A).
Signal U _gIs formed to form a gate electrode 27 to which is supplied.

In the structure of FIG. 13, the SiO ₂ film 12 is formed so as to fill a recess formed in a part of the substrate 10, and the gate electrode 27 is formed in the SiO ₂ film 12 in the recess. Correspondingly, although formed so as to be capacitively coupled to the nanocrystal 14 via the coupling capacitance _Cg , the single-electron transistor of the present invention is not limited to such a specific structure. as long as the electrode 27 forms a capacitive coupling of the Sn nanocrystals 14 and the capacitance C _g, it may be any structure. [Fourth Embodiment] FIG. 14 shows a configuration of a flash memory 40 according to a fourth embodiment of the present invention using the structure of FIG.

Referring to FIG. 14, the flash memory 4
0 is typically p-type doped, and in the example shown, LD
A gate electrode structure 4 formed on a Si substrate 41 formed with diffusion regions 41A and 41B having a D structure as a source region and a drain region, respectively, and formed on a portion of the Si substrate 41 corresponding to a channel region 41C.
2 inclusive.

The gate electrode structure 42 has a side wall surface covered with a pair of side wall oxide films 42A and 42B.
(J) A floating gate structure portion 42C in which Sn nanocrystals are two-dimensionally arranged in a layered manner in a SiO ₂ film, and a floating gate structure portion 4 similar to that shown in FIG.
And a control electrode 42D provided on 2C. In operation, by applying a write voltage to the control electrode 42D, electrons accelerated between the source electrode 41A and the drain electrode 41B are captured by each Sn nanocrystal in the floating gate structure 42C, It is kept stable. The electrons captured by the Sn nanocrystals change the threshold voltage of the MOS transistor constituting the flash memory 40. As a result, a read voltage is applied to the control
By detecting ON / OFF of the S transistor, accumulated information can be read. Further, by applying an erasing voltage between the control electrode 42D and the substrate 41 or the source region 41A, it becomes possible to erase the stored information.

In particular, the floating gate structure 42
By using Sn nanocrystals for C, it becomes possible to hold electrons one by one on the Sn nanocrystals. Thus, the flash memory 40 of FIG. 14 has low power consumption and is suitable for high integration. Also, multi-value storage is possible. Fifth Embodiment In the above embodiment, the nanocrystal 14 made of a metal element such as Sn or Sb is made of Si.
Although formed in the strain accumulation region formed near the interface between the substrate 10 and the thermal oxide film 12, in such a configuration, the distance between the metal nanocrystal 14 and the Si substrate 10 depends on the combination of the material type. And cannot be freely controlled according to desired design conditions.

On the other hand, FIGS. 15A to 16
In the fifth embodiment of the present invention described with reference to FIG.
The distance between the metal nanocrystal 14 and the Si substrate 10 is
Can be set to However, it was explained earlier in the figure.
Portions are given the same reference numerals, and description thereof is omitted. FIG.
5A, in this step, the Si substrate 10
After the organic cleaning and the chemical cleaning,
The surface is thermally oxidized by the thermal oxidation process. _TwoAbout membrane 12
It is formed to a thickness of 10 nm. Next, the step of FIG.
Then, another SiO 2 is formed on the thermal oxide film 12._TwoThe membrane 52 is
It is formed to a thickness of about 10 nm by a plasma CVD method. An example
For example, the thermal oxidation step is performed at a temperature of 900 to 1100 ° C.
And the SiO 2_TwoThe film 52 is made of TEOS
Plasma CV using traethoxysilane) and oxygen as raw materials
Formed at a temperature of 250 to 400 ° C. by Method D.
The thermal oxide film 12 and CVD-SiO_TwoThe temperature at which the film 52 is formed
Different degrees of density, resulting in different densities,
Oxide film 12 and CVD-SiO_TwoAlong the interface with the membrane 52
Therefore, a strong thermal strain is introduced.

Further, in the step of FIG.
The ion implantation of Sn atoms is performed with an acceleration voltage of about 15 keV and a dose of about 5 × 10 ¹⁵ cm ⁻² from an oblique direction with respect to the structure of FIG.
Sn atoms are introduced into the D-SiO film 52 along the interface with the thermal oxide film 12. At this time, the acceleration voltage is
The center of the distribution profile of the implanted Sn atoms is
It is set to be located near the interface. As shown in FIG. 15C, the ion implantation step is performed at an incident angle of typically about 60 ° from an oblique direction, so that the distribution width of the implanted Sn atoms or the width of the profile is reduced. It is possible to narrow it. In the example of FIG. 15C, the substrate 10 is positioned at 37 degrees with respect to the incident direction of Sn ions.
The Sn is incident on the substrate 10 at an incident angle of 63 °.

Further, the structure shown in FIG.
As shown in FIG. 15D, Sn nanocrystals having a diameter of about 4 ± 1 nm are formed in the CVD-SiO ₂ film 52 along the interface with the thermal oxide film 12 as shown in FIG. 56 are formed substantially aligned on a two-dimensional plane. In the configuration of the present embodiment, the CVD-SiO
_Since the thermal oxide film 12 having a thickness of about 10 nm exists under the _second film 52, in the ion implantation step of FIG.
Almost none of the n ions reach the Si substrate 10, so that the Si substrate 10 and the thermal oxide film 12
There is no problem such as the formation of a metal precipitate at the interface between them. Therefore, when the configuration of FIG. 16D is applied to the first embodiment of the present invention, it becomes possible to efficiently manufacture a single electronic device with a high yield. FIG.
By applying the configuration of (D) to the flash memory 40 of FIG. 14, it is possible to minimize the leakage of the charge accumulated in the Sn nanocrystal to the Si substrate 41.

In this embodiment, the method of forming the SiO ₂ films 12 and 52 is not limited to the combination of the thermal oxidation method and the plasma CVD method described above, but may be a combination of the photo CVD method or the thermal CVD method. It is also possible. Further, another insulating film is formed on the CVD-SiO ₂ film 52, Sn atoms are ion-implanted into the another insulating film, heat-treated, and another insulating film is formed along the interface with the SiO ₂ film 52. A two-dimensional array of Sn nanocrystals may be formed. Further, the nanocrystals are not limited to Sn nanocrystals, but include Cu, Fe, A
It may be a nanocrystal of a metal element selected from the group consisting of g, Au, Sn, Pt, In, Sb and Ga. Sixth Embodiment FIG. 17 shows the structure of a single electronic device 60 according to a sixth embodiment of the present invention. However, in FIG. 17, the same reference numerals are given to the parts described above, and the description will be omitted.

Referring to FIG. 17, in this embodiment, an SiN film 62 is formed on the thermal oxide film 12 to a thickness of about 5 nm by a plasma CVD method using ammonia and monosilane as raw materials. CVD-SiO ₂ film 52
Is typically formed to a thickness of 10 nm. Furthermore, the same steps as FIG. 15 (C), the CVD-SiO ₂
By introducing Sn atoms into the film 52 by oblique ion implantation and performing a heat treatment at 900 ° C. for 10 minutes, the SiN film 6 is formed in the CVD-SiO ₂ film 52.
2 along the interface with Sn,
It is deposited in the same manner as the n nanocrystal 56.

In this embodiment, the SiN film 62 is formed by CVD.
It acts as a diffusion barrier for Sn atoms introduced into -SiO ₂ film 52, and aggregated at the interface between the Sn atoms of the CVD-SiO ₂ film 52 and the SiN film 62 to form the Sn nanocrystals 66 However, the diffusion barrier 62 is made of SiN
It is not limited to a film, but may be a SiON film or GeO
₂ film, GeN film, GeON film, GeON film, (SiG
e) Si—Ge—O—N such as O ₂ film and (SiGe) N film
Any material may be used as long as it is a system-based film that forms strain at the interface when formed in contact with the SiO ₂ film.

Although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to such specific embodiments, and various modifications and changes may be made within the scope of the appended claims. It is.

[0048]

According to the features of the present invention, the metal element is introduced into the insulating film formed on the substrate so that the metal element does not enter the substrate. The introduced metal element concentrates in a region of the insulating film adjacent to the substrate where the strain is accumulated. By annealing such a structure at a high temperature, in the insulating film,
Along the interface with the substrate, uniform nanometer-sized metal nanocrystals are formed at a substantially constant height from the interface and spaced apart from each other. In particular, when the introduction of the metal element is performed by an ion implantation method, the acceleration energy is set to a low energy such that the metal element does not reach the substrate, so that the depth of the metal element in the insulating film before annealing is increased. The distribution in the vertical direction is improved, and the metal element can be concentrated at a predetermined depth.
Further, by forming such an insulating film into a multilayer structure, it is possible to form a desired metal nanocrystal at an arbitrary distance from the substrate.

[Brief description of the drawings]

1A and 1B are diagrams illustrating the principle of a single electronic device.

FIG. 2 is a diagram (part 1) for explaining the principle of the present invention;

FIG. 3 is a diagram (part 2) for explaining the principle of the present invention;

FIG. 4 is a diagram (part 3) for explaining the principle of the present invention;

FIG. 5 is a diagram (part 4) for explaining the principle of the present invention;

FIGS. 6A to 6D are diagrams (part 1) illustrating a manufacturing process of the single electronic device according to the first embodiment of the present invention;

FIGS. 7 (E) to 7 (H) are views (No. 2) showing the steps of manufacturing the single electronic device according to the first embodiment of the present invention. FIGS.

FIGS. 8 (I) and (J) are views (No. 3) showing a step of manufacturing the single electronic device according to the first embodiment of the present invention;

FIG. 9 is a diagram showing an equivalent circuit diagram of the single-electron tunnel diode according to the first embodiment of the present invention.

FIG. 10 is a graph showing operating characteristics of the single-electron tunnel diode according to the first embodiment of the present invention.

FIGS. 11A and 11B are views showing an Sb nanocrystal according to a second embodiment of the present invention.

FIGS. 12A and 12B are diagrams illustrating the configuration and operation of a single-electron transistor according to a third embodiment of the present invention.

FIG. 13 is a diagram showing a configuration of the single-electron transistor of FIG.

FIG. 14 is a diagram showing a configuration of a flash memory according to a fourth embodiment of the present invention.

FIGS. 15A to 15C are diagrams (part 1) illustrating manufacturing steps of a single electronic device according to a fifth embodiment of the present invention;

FIG. 16D is a view (part 2) showing a step of manufacturing the single electronic device according to the fifth embodiment of the present invention;

FIG. 17 is a view illustrating a single electronic device according to a sixth embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Substrate 12 Insulating film 14,56,66 Metal nanocrystal 16,18 Resist 16A Resist pattern 18A Resist pattern 20 Photomask 20A Opening 22,24 Exposure area 26 Electrode 30 Single electron transistor 40 Single electron flash memory 41 Substrate 41A , 41B Diffusion region 41C Channel region 42 Gate structure 42A, 42B Side wall oxide film 42C Floating gate structure 42D Control electrode 50, 60 Single electronic device 52, 62 Second insulating film

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (23)

[Claims] A conductive substrate; an insulating film formed on the conductive substrate; and a nanometer formed substantially parallel to an interface between the substrate and the insulating film in the insulating film. In a single electronic device including a plurality of conductive particles having a diameter of a size and an electrode formed on the insulating film, the plurality of conductive particles have substantially equal sizes,
A single electronic device characterized by being substantially coplanar in the insulating film. 2. The single electronic device according to claim 1, wherein the plurality of conductive particles are formed in a strain accumulation region in contact with the substrate in the insulating film. 3. The single electronic device according to claim 1, wherein the conductive particles are nanocrystals. 4. The single electron according to claim 1, wherein the conductive substrate is formed of a degenerated Si substrate, and the insulating film is a SiO ₂ film or a SiN film. apparatus. 5. The conductive particles include Cu, Fe, Ag,
The single electronic device according to claim 1, comprising a metal element selected from the group consisting of Au, Sn, Pt, In, Sb, and Ga. 6. The semiconductor device according to claim 1, further comprising a gate electrode electrostatically coupled to the conductive particles and the substrate, wherein the single-electron device forms a single-electron transistor. A single electronic device according to any one of the preceding claims. 7. The insulating film and the electrode form a gate structure defined by a pair of opposing side walls, and the single electronic device further includes a gate structure corresponding to each of the pair of side walls in the substrate. The single electronic device according to claim 1, wherein the single electronic device includes a diffusion region to form a memory device. 8. The insulating film includes a first insulating film and a second insulating film, and the plurality of conductive particles are provided near an interface between the first insulating film and the second insulating film. The single electronic device according to claim 1, wherein the single electronic device can be formed. 9. The first insulating film and the second insulating film,
9. The single electronic device according to claim 8, comprising films of the same composition formed at different temperatures. 10. The single electronic device according to claim 8, wherein the first insulating film has a different composition from that of the second insulating film. 11. A doping step of introducing a metal element into an insulating film formed on a substrate, and diffusing the metal element introduced into the insulating film, and forming the insulating film and the insulating film in the insulating film. An annealing step of precipitating nanometer-sized mutually isolated metal fine particles along the interface with the substrate, wherein the doping step is performed by the metal element in the insulating film. Is performed such that the concentration of is substantially zero in the substrate and at the interface. 12. The doping step includes an ion implantation step of introducing the metal element into the insulating film. The ion implantation step includes the step of controlling the concentration of the metal element in the insulating film within the substrate and the concentration of the metal element in the insulating film. The method of manufacturing a single electronic device according to claim 11, wherein the method is performed at an acceleration energy such that the interface substantially becomes zero and a depth distribution of the metal element has a sharp maximum. 13. The method for manufacturing a single electronic device according to claim 11, wherein said substrate is made of a Si substrate, and said insulating film is made of SiO ₂ . 14. The metal element may be Cu, Fe, Ag,
14. The method for manufacturing a single electronic device according to claim 11, wherein the method is selected from the group consisting of Au, Sn, Pt, In, Sb, and Ga. 15. The method according to claim 12, wherein the metal element is Sn, and the ion implantation step is performed by setting an acceleration energy to about 20 keV or less. 16. The method according to claim 12, wherein the metal element is Sb, and the ion implantation step introduces Sb into the insulating film at a dose of about 1 × 10 ¹³ cm ⁻² or more.
A method for manufacturing the single electronic device according to the above. 17. The method according to claim 17, wherein in the ion implantation step, Sb is reduced to about 1 ×.
17. The method for manufacturing a single electronic device according to claim 16, wherein the doping is performed at a dose of 10 ¹⁶ cm ^-2 or more into the insulating film. 18. The method according to claim 16, wherein in the ion implantation step, the Sb is introduced into the insulating film at a dose of about 1 × 10 ¹⁷ cm ⁻² or more. . 19. The method according to claim 11, wherein the annealing is performed at a temperature of about 400 ° C. or higher.
8. The method for manufacturing a single electronic device according to claim 8. 20. The insulating film comprises a first insulating film and a second insulating film thereon, and the doping step includes the step of: The method of manufacturing a single electronic device according to any one of claims 11 to 19, wherein the method is performed so as to concentrate near an interface between them. 21. The method according to claim 20, wherein the first insulating film and the second insulating film are formed at different temperatures. 22. The method according to claim 20, wherein the first insulating film and the second insulating film have different compositions. 23. The substrate according to claim 12, wherein the ion implantation is performed obliquely with respect to the substrate.
3. The method of manufacturing a single electronic device according to claim 2, wherein