CN101542700A - Room temperature-operating single-electron device and the fabrication method thereof - Google Patents
Room temperature-operating single-electron device and the fabrication method thereof Download PDFInfo
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- CN101542700A CN101542700A CNA2008800003271A CN200880000327A CN101542700A CN 101542700 A CN101542700 A CN 101542700A CN A2008800003271 A CNA2008800003271 A CN A2008800003271A CN 200880000327 A CN200880000327 A CN 200880000327A CN 101542700 A CN101542700 A CN 101542700A
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 56
- 239000002184 metal Substances 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 74
- 239000002096 quantum dot Substances 0.000 claims abstract description 59
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 50
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 50
- 230000003647 oxidation Effects 0.000 claims description 42
- 238000007254 oxidation reaction Methods 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 38
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 32
- 229910052710 silicon Inorganic materials 0.000 claims description 32
- 239000010703 silicon Substances 0.000 claims description 32
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 30
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 30
- 238000005530 etching Methods 0.000 claims description 20
- 238000000151 deposition Methods 0.000 claims description 17
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- 238000000609 electron-beam lithography Methods 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 8
- 238000001020 plasma etching Methods 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims description 6
- 229960002163 hydrogen peroxide Drugs 0.000 claims description 6
- 150000002500 ions Chemical class 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 5
- 229910017052 cobalt Inorganic materials 0.000 claims description 5
- 239000010941 cobalt Substances 0.000 claims description 5
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 5
- 230000008021 deposition Effects 0.000 claims description 5
- 238000001451 molecular beam epitaxy Methods 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 5
- 238000010894 electron beam technology Methods 0.000 claims description 4
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 239000011259 mixed solution Substances 0.000 claims description 3
- 238000005381 potential energy Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052691 Erbium Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
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- 238000010586 diagram Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
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- 229910044991 metal oxide Inorganic materials 0.000 description 1
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- 239000003870 refractory metal Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/7613—Single electron transistors; Coulomb blockade devices
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Abstract
The present invention relates to a room temperature-operating single-electron device and a fabrication method thereof, and more particularly, to a room temperature-operating single- electron device in which a plurality of metal silicide dots formed serially is used as multiple quantum dots, and a fabrication method thereof.
Description
Technical field
The present invention relates to a kind of single-electron device and manufacture method thereof of room temperature-operating, more specifically, the present invention relates to single-electron device and the manufacture method thereof of a kind of a plurality of metal silication object points that wherein form continuously as the room temperature-operating of many quantum dots.
Background technology
Compare with conventional device, single-electron device has low-down power consumption, and therefore can improve the integrated level of circuit relatively.Particularly, single-electron device has important special characteristics, and wherein drain current periodically increases according to grid voltage or reduces.
More specifically, when because when the induced charge (induced charge) in the increase quantum dot of grid voltage increases and therefore the amount of the induced charge in the quantum dot reaches the elementary charge amount, thereby an electronics is tunneling to quantum dot and causes that the amount of induced charge is cancelled the potential energy that minimizes quantum dot from source electrode.Similarly, inswept by grid voltage, thus the phenomenon that the amount of the induced charge of the successive value in the quantum dot that is increased by grid voltage is offset the potential energy minimum that makes quantum dot by the electronics from source electrode to the quantum dot tunnelling periodically repeats.This phenomenon is known as enclosed pasture vibration (coulomb oscillation).Just, observe the enclosed pasture vibration by change periodicity on/off drain current according to grid voltage.In the enclosed pasture vibration, coulomb obstruction (coulomb blockade) district and tunnel region are vibrated regularly and are made for each property regional cycle ground generation signal " 1 " and " 0 ".
Single-electron device is to add an electronics to electrode or deduct the device of an electronics from electrode by the enclosed pasture blocking effect.Single-electron device has low-power consumption and occurs to substitute complementary metal oxide semiconductors (CMOS) (CMOS) as device of future generation aspect integrated level.
At present, reduce the method for electric capacity, increased the operating temperature of device by the size that only reduces single quantum dot.But, if by utilizing metal dots to form many quantum dots, just then the electric capacity of single-electron device self can reduce and make the operating temperature of device be increased to room temperature.When many quantum dots bunchiness was provided with, the number with quantum dot of same capacitance increased and whole capacitor is reduced.
Usually, adopt the main purpose of silicide as follows.Along with the design rule of semiconductor device is more and more stricter, the high surface resistance of grid is the main cause that reduces the speed of service of device.Thereby,, be necessary to make low-resistance gate electrode in order to improve the speed of service of device.In order to reach the purpose of improving resistance, adopt the gate electrode that comprises refractory metal silicide with low-resistivity.
Though do not illustrate particularly, following two types aforementioned conventional single-electron device can be shown.One type is after raceway groove forms, by the shape formation quantum dot of thermal oxidation technology according to raceway groove.In order to make the device of the room temperature-operating that adopts this scheme, need very little quantum dot and be not easy to control the electric capacity of tunnel junction, this makes the manufacturing of the device difficulty that becomes.
Another kind of type is to form a plurality of quantum dots continuously to reduce the total capacitance of quantum dot on single substrate by electron beam lithography and reactive ion etching (RIE).In order to make the device of the room temperature-operating that adopts this scheme, it is big that the size of single quantum dot becomes, and therefore the length of active area is increased in the scope of μ m unit, and this makes the integrated level that is difficult to improve single-electron device.
Summary of the invention
Technical problem
Thereby, the present invention has done and has made great efforts to be intended to solve the problems referred to above that take place in this area, and one of target of the present invention provides the single-electron device and the manufacture method thereof of room temperature-operating, metal membrane-coating is deposited between source electrode and the drain electrode and thereby a plurality of metal silication object point is formed on the metal film can making up a plurality of quantum dots with very little electric capacity as quantum dot in single-electron device, and therefore improves device operation function at room temperature and low-power consumption and the high integration that realizes device.
Technical scheme
In order to realize above target, according to the present invention, the manufacture method of the single-electron device of room temperature-operating comprises:
First step: form the SOI substrates by on silicon substrate 12, piling up insulating barrier 11 and silicon layer 10 in turn, the silicon layer 10 of etching SOI substrate, thus be formed with source region 10a;
Second step: on the central channel of active area 10a part, form mask 20, foreign ion is injected into forms source area and drain region in the part of active area 10a;
Third step: on the whole top surface of SOI substrate, form silicon oxide film 30;
The 4th step: be etched with the channel part of source region 10a and form silicide groove 31;
The 5th step: deposition oxide film 40 on the whole top surface of SOI substrate;
The 6th step: depositing metallic films 42 on the whole top surface of oxidation film;
The 7th step: the part of metal film 42 is heat-treated realizing the silication of metal dots, thereby the metal film 42 of removing silicon oxide film 30 and not silication forms the silicide quantum dot 41 that bunchiness are arranged;
The 8th step: deposition oxidation film of grid 50a and 50b on the whole top surface of SOI substrate;
The 9th step: thus the part that etching oxidation film of grid 50a and 50b are positioned on the top of the source electrode 13 that is formed on active area 10a two ends and drain electrode 14 forms each contact hole, thus depositing metallic films forms source electrode weld pad 60 and drain electrode weld pad 61 to fill these contact holes; And
The tenth step: on silicide groove 31, form the resist pattern to form grid.
And according to present embodiment, active area 10a can have the width of 1nm to the length of 100nm and 10nm to 15nm.
In addition, according to present embodiment, active area 10a can utilize photoetching, electron beam lithography or reactive ion etching to form.
And according to present embodiment, silicon oxide film 30 can have the thickness of 2nm to 10nm.
And according to present embodiment, in third step, silicon layer 10 can have the width of 40nm to the thickness of 45nm and 6nm to 10nm.
In addition, according to present embodiment, in the 4th step, the channel part of active area 10a can utilize reactive ion etching to carry out etching, to have the thickness of 2nm to 10nm.
And according to present embodiment, in the 5th step, oxidation film 40 can form by this way: be placed in the hydrogenperoxide steam generator or in the air and form.
And according to present embodiment, in the 6th step, metal film 42 can be made by cobalt.
In addition, according to present embodiment, in the 6th step, can utilize electron-beam evaporator or molecular beam epitaxy (MBE) device depositing metallic films 42, depositional mode is that its thickness is in 0.1nm arrives the scope of 1nm.
And according to present embodiment, in the 7th step, thereby metal film 42 can form silicide quantum dot 41 by the heat treatment of electron beam lithography process quilt.
And according to present embodiment, silicon oxide film 30 can be removed by utilizing buffer oxide etching agent (BOE, buffered oxide etchant), and the metal film 42 of not silication is removed by the mixed solution that utilizes sulfuric acid and hydrogenperoxide steam generator.
In addition, according to present embodiment, each of silicide quantum dot 41 has the diameter of 2nm to 10nm, and the number of silicide quantum dot is 1 to 50.
And according to present embodiment, in the 8th step, the oxidation film of grid by chemical vapor deposition (CVD) forms has the thickness of 30nm to 50nm.
And according to present embodiment, in the 8th step, oxidation film of grid has the thickness of 100nm to 300nm, and utilizes the oxidation film of grid 31 of chemical vapor deposition (CVD) on silicide groove 31 to form to have the thickness of 30nm to 50nm.
In addition, according to present embodiment, grid can be control grid 62 or "T"-shaped grid 63.
And grid can have the thickness of 100nm to 500nm.
And the manufacture method that target of the present invention can be passed through the single-electron device of room temperature-operating realizes that this method comprises:
First step: form the SOI substrates by on silicon substrate 12, piling up insulating barrier 11 and silicon layer 10 in turn, the silicon layer 10 of etching SOI substrate, thus be formed with source region 10a;
Second step: on the central channel of active area 10a part, form mask 20, foreign ion is injected into forms source area and drain region in the part of active area 10a;
Third step: on the whole top surface of SOI substrate, form silicon oxide film 30;
The 4th step: thus the silicon oxide film 30 by utilizing channel part forms silicide groove 31 as the channel part of mask etching active area 10a;
The 5th step: depositing metallic films 42 on the whole top surface of SOI substrate makes this metal film silication;
The 6th step: thus the metal film 42 of removing silicon oxide film 30 and not silication forms the silicide quantum dot 41 that bunchiness is arranged;
The 7th step: on the whole top surface of SOI substrate, form diaphragm 70;
The 8th step: thus the diaphragm 70 that etching is positioned on the top of the source electrode at the two ends that are formed on active area 10a and drain electrode forms each contact hole, thus depositing metallic films forms source electrode weld pad 60 and drain electrode weld pad 61 to fill those contact holes; And
The 9th step: depositing metallic films at the downside of SOI substrate to form bottom gate.
In addition, the single-electron device of the room temperature-operating that above target of the present invention can be by utilizing manufacture method manufacturing described above is realized.
Beneficial effect
Thereby the present invention has such beneficial effect: because a plurality of metal silication object point bunchiness form the many quantum dots between source electrode and the drain electrode, thereby reduced the total capacitance of single-electron device, can increase the operational efficiency of device.
Particularly, "T"-shaped grid is formed on the raceway groove top and makes and only to control potential energy in the quantum dot region, thereby can avoid the generation of any electrical interference between source area and the drain region so that single-electron device even can at room temperature move.
In addition, utilizing cobalt to form in the process of metal silication object point, employing has the consistent size and the metal silicide quantum dot of density distribution, and described metal silicide quantum dot forms by the metal film that use is formed with oxidation film, thereby obtains more stable quantum dot.
Description of drawings
The perspective view of Fig. 1 is illustrated in the state that is formed with the source region in the manufacture method according to the single-electron device of the room temperature-operating of the first embodiment of the present invention;
The perspective view of Fig. 2 is illustrated in according to the state that forms mask in the manufacture method of the single-electron device of the room temperature-operating of the first embodiment of the present invention;
The perspective view of Fig. 3 is illustrated in according to the state that forms silicon oxide film in the manufacture method of the single-electron device of the room temperature-operating of the first embodiment of the present invention;
Fig. 4 is that the line A-A along Fig. 3 cuts open the sectional view of getting;
The perspective view of Fig. 5 is illustrated in according to the state that forms the silicide groove in the manufacture method of the single-electron device of the room temperature-operating of the first embodiment of the present invention;
Fig. 6 is that the line B-B along Fig. 5 cuts open the sectional view of getting;
The perspective view of Fig. 7 is illustrated in according to the state that forms oxidation film in the manufacture method of the single-electron device of the room temperature-operating of the first embodiment of the present invention;
Fig. 8 is that the line C-C along Fig. 7 cuts open the sectional view of getting;
The perspective view of Fig. 9 is illustrated in according to the state that forms metal film in the manufacture method of the single-electron device of the room temperature-operating of the first embodiment of the present invention;
Figure 10 is that the line D-D along Fig. 9 cuts open the sectional view of getting;
The perspective view of Figure 11 is illustrated in the state that forms the silicide quantum dot according to metal film by removing not silication and silicon oxide film in the manufacture method of the single-electron device of the room temperature-operating of the first embodiment of the present invention;
The perspective view of Figure 12 is illustrated in according to the state that forms oxidation film of grid in the manufacture method of the single-electron device of the room temperature-operating of the first embodiment of the present invention;
The line E-E along Figure 12 of Figure 13 cuts open the sectional view of getting and is illustrated in and has 30nm in the manufacture method according to the single-electron device of the room temperature-operating of the first embodiment of the present invention and be deposited the state that forms the control grid to the oxidation film of grid of 50nm thickness;
The line E-E along Figure 12 of Figure 14 cuts open the sectional view of getting and is illustrated in and has 100nm in the manufacture method according to the single-electron device of the room temperature-operating of the first embodiment of the present invention and be deposited the state that forms "T"-shaped grid to the oxidation film of grid of the thickness of 300nm;
The perspective view of Figure 15 is illustrated in the state that is formed according to source electrode weld pad in the manufacture method of the single-electron device of the room temperature-operating of the first embodiment of the present invention and drain electrode weld pad;
The perspective view of Figure 16 is illustrated in the state that is formed according to grid in the manufacture method of the single-electron device of the room temperature-operating of the first embodiment of the present invention;
The sectional view of Figure 17 is illustrated in according to the state that is formed of control grid in the manufacture method of the single-electron device of the room temperature-operating of the first embodiment of the present invention, and it is that line F-F along Figure 16 cuts open and gets;
The sectional view of Figure 18 is illustrated in the state that "T"-shaped grid is formed in the manufacture method according to the single-electron device of the room temperature-operating of the first embodiment of the present invention, and it is that line F-F along Figure 16 cuts open and gets;
The perspective view of Figure 19 is illustrated in the state that metal membrane-coating forms in the manufacture method of single-electron device of room temperature-operating according to a second embodiment of the present invention;
Figure 20 is that the line G-G along Figure 19 cuts open the sectional view of getting;
The perspective view of Figure 21 illustrates the single-electron device that the manufacture method of the single-electron device of utilization room temperature-operating is according to a second embodiment of the present invention made.
Embodiment
Now will be with reference to the accompanying drawings, the preferred embodiment according to the manufacture method of the single-electron device of room temperature-operating of the present invention is described in detail.
First embodiment
Fig. 1 to 18 illustrates according to the exemplary status in the manufacture method of the single-electron device of room temperature-operating of the present invention.
First step is that wherein active area 10a is formed on step on the SOI substrate.In this case, active area 10a comprises source electrode 13 described later and drain electrode 14 and is used to make source electrode and the interconnected raceway groove of drain electrode.The mode that is stacked in turn on the silicon substrate 12 with insulating barrier 11 and silicon layer 10 forms the SOI substrate.Active area 10a forms by the silicon layer 10 of etching SOI substrate.
The thickness of silicon layer 10 is about 50nm, adopts photoetching, electron beam lithography or reactive ion etching that silicon layer 10 is carried out etching and is used to form active area 10a.As shown in Fig. 1, the active area 10a that forms by etching silicon layer 10 preferably has the length and about 10nm width to 15nm of about 1nm to 100nm.
Second step is that impurity is injected into the active area 10a of part to form the step of source area and drain region.In order to realize the purpose of implanted dopant, mask 20 is formed on the top of active area 10a, as shown in Figure 2, preferably is formed on the central channel part, and the both sides that foreign ion are injected into channel part are to form source electrode 13 and drain electrode 14.At this moment, mask 20 preferably adopts the photoresist pattern as doping mask.After finishing the impurity injection, mask 20 is removed.Because it is well-known removing the method for mask 20 concerning those skilled in the art, so will ignore detailed description.
Third step is the step that forms silicon oxide film 30.As shown in Fig. 3 and Fig. 4, on the silicon layer 10 of SOI substrate, silicon oxide film 30 is formed the thickness of about 2nm to 10nm.Silicon oxide film 30 can form by utilizing thermal oxidation technology.The thickness of considering silicon layer 10 reduces along with the formation of silicon oxide film 30, has 40nm to the thickness of 45nm and 6 to 10nm width thereby silicon oxide film 30 is formed silicon layer 10.The thermal oxidation technology that is used to form silicon oxide film 30 also is intended to heat treatment and is injected into foreign ion in the channel part of active area 10a.
The 4th step is the step that forms silicide groove 31.At first, before silicide groove 31 formed, the silicon oxide film 30 that is formed on the channel part of active area 10a was etched.Subsequently, when when utilizing remaining silicon oxide film 30 as the silicon layer 10 of mask etching channel part, silicide groove 31 forms, as illustrated in Figures 5 and 6.The silicon layer 10 of channel part utilizes reactive ion etching to be etched to have the thickness of 2nm to 10nm.Silicide groove 31 is the zones that wherein will form the metal silicide quantum dot.
The 5th step is that oxidation film 40 is deposited on step on the whole top surface of SOI substrate.Having consistent size and highdensity silicide quantum dot 41 can form by the formation of oxidation film 40.Oxidation film 40 forms by this way: be placed on hydrogenperoxide steam generator (H
2O
2) in 10 minutes or be placed in the air and form.
The 6th step is that metal film 42 is deposited over the step on the whole top surface of the SOI substrate that is formed with oxidation film 40.Thereby metal film 42 is deposited and makes silicide groove 31 silication that are formed in the oxidation film 40.In this case,, can use any metal,, but be preferably cobalt (Co) as long as it is by silicon layer 10 silication as the material that is used for metal film 42.The deposition of metal film 42 is undertaken by Technology for Heating Processing.In this, metal film utilizes electron-beam evaporator or molecular beam epitaxy device (MBE) to be deposited, and generation type makes its thickness in 0.1nm arrives the scope of 1nm.
The 7th step is the step that forms silicide quantum dot 41.Metal film 42 is by the silication of electron beam lithography process quilt heat treatment with the realization metal dots.In this case, oxidation film 40 is formed on the below of metal film 42.With reference to figure 8, the silication of metal dots is only carried out at metal film 42 with as the part place that the active area 10a of silicon layer 10 contacts with each other, and promptly carries out at silicide groove 31 places.Because silicon oxide film 30 does not combine (couple) with metal film 42, so the metal film 42 at this part place is not by silication.The metal film 42 of silication and silicon oxide film 30 are not removed and form quantum dot 41.The metal film 42 of silication is not removed by the mixed solution that utilizes sulfuric acid and hydrogenperoxide steam generator, and silicon oxide film 30 is removed by utilizing buffer oxide etching agent (BOE, buffered oxide etchant).Figure 11 illustrates that silicide quantum dot 41 is formed on source electrode 13 and the state between 14 of draining.
Preferably, form silicide quantum dot 41 by this way: each metal dots has 2nm and forms bunchiness to the diameter of 10nm and about 1 to 50 metal dots and arrange (serial array).This is intended to reduce the total capacitance of single-electron device.
The 8th step is the step that forms oxidation film of grid 50a and 50b.As shown in figure 12, oxidation film of grid 50a and 50b are deposited on the whole top surface of SOI substrate.Oxidation film of grid 50a and 50b can utilize the chemical vapour deposition (CVD) device with low temperature depositing.Can be by considering to disturb oxidation film of grid 50a and 50b to form between source electrode 13, drain electrode 14 and the silicide quantum dot 41 by changing its thickness.
In an example, as shown in figure 13, oxidation film of grid 50a can become the thickness of about 30nm to 50nm by adequate relief.This be intended to utilize the control grid 62 that will be formed on the oxidation film of grid 50a avoid source electrode 13, the drain electrode 14 and silicide quantum dot 41 between any interference.
In another example, as shown in Figure 14, oxidation film of grid 50b forms the thickness of 100nm to 300nm, utilizes the oxidation film of grid 50b of electronic beam photetching process on silicide groove 31 zones can form thickness particularly and is about 30nm to 50nm.This is intended to the distortion that the heat treatment in the minimization of silicon metallization processes may cause.
The 9th step is the step that forms source electrode weld pad 60 and drain electrode weld pad 61.At first, oxidation film of grid 50a and 50b utilize photoetching method to be etched.In this case, outside first contact hole and the second contact hole (not shown) are formed source electrode 13 and drain electrode 14 are exposed to.Afterwards, fill first contact hole and second contact hole on first contact hole and second contact hole thereby metal film 42 is deposited over, photoresist is removed and forms source electrode weld pad 60 and the weld pad 61 that drains.Because it is well-known removing the method for photoresist to those skilled in the art, so omitted detailed description.
The tenth step is the step that forms grid.Grid preferably forms the thickness of 100nm to 500nm, and depends on oxidation film of grid 50a and 50b and form control grid 62 or "T"-shaped grid 63.
To describe the situation of control grid 62 below in detail.
On metal silicide quantum dot 41, utilize electron beam lithography or photoetching that the resist pattern is formed on oxidation film of grid 50a and the 50b.Afterwards, as shown in figure 17, metal film 42 is deposited to fill the top of quantum dot 41, forms control grid 62 thereby remove the resist pattern then.Control grid 62 changes the potential energy of the subregion of metal silicide quantum dot 41 zones and source electrode 13 and drain electrode 14, and can make the manufacturing of single-electron device easier.
"T"-shaped grid 63 forms in the mode identical with the generation type of control grid 62.As shown in Figure 18, "T"-shaped grid 63 utilizes the thickness difference between oxidation film of grid 50a and the 50b to form."T"-shaped grid 63 is positioned on the metal silicide quantum dot 41 only to change the potential energy of metal silicide quantum dot 41, therefore has the advantage that makes quantum dot 41, source electrode 13 and any minimum interference between 14 that drains.
In a preferred embodiment of the invention, situation about having formed behind the grid though described first formation source electrode weld pad 60 and drain electrode weld pad 61 also can form grid earlier and forms source electrode weld pad 60 and drain electrode weld pad 61 afterwards.
Second embodiment
The single-electron device that the method for the single-electron device of room temperature-operating is made is made in the perspective view diagram utilization of Figure 21 according to a second embodiment of the present invention.Because in the whole steps of the method for the single-electron device of making room temperature-operating according to a second embodiment of the present invention, step in the method for first to the 4th step and the single-electron device of making room temperature-operating according to the first embodiment of the present invention is identical, so will replace description of them among second embodiment with aforementioned description.
In the 5th step of present embodiment, thereby metal film 42 is deposited on the whole top surface of the SOI substrate that is formed with silicide groove 31 by silication.In this case,, can use any metal, as long as it is by silicon layer 10 silication as the material that is used for metal film 42.In a preferred embodiment of the invention, the example that is used for the material of metal film 42 can comprise cobalt (Co), erbium (Er), titanium (Ti) etc., and nickel (Ni) can be as the material of metal film.
Utilize Technology for Heating Processing to form metal film 42.In this case, utilize electron-beam evaporator or molecular beam epitaxy, metal film 42 forms the thickness of 0.1nm to 1nm.
Thereby the above formed metal film 42 of heat treatment is realized the silication of metal dots.As shown in Figure 20, the silication of metal dots is only carried out with the part place that active area 10a as silicon layer 10 contacts with each other at metal film 42, promptly only carries out at silicide groove 31 places.Because silicon oxide film 30 does not combine with metal film 42, so the remainder of metal film 42 is unsilicided.
The 6th step is the step that forms silicide quantum dot 41.Silicon oxide film 30 and unsilicided metal film 42 are removed to form quantum dot 41.The method of removing silicon oxide film 30 and metal silicide film 42 not and in first embodiment, adopted identical described above.
The 7th step is the step that forms diaphragm 70.Diaphragm 70 is intended to protect the active area 10a that comprises quantum dot 41, and forms predetermined thickness above silicon substrate 12.Diaphragm 70 is corresponding with oxidation film of grid 50a and 50b among first embodiment.
The 8th step is the step that forms source electrode weld pad 60 and drain electrode weld pad 61.In this step, first contact hole is formed in the diaphragm 70 corresponding with oxidation film of grid 50a and 50b with second contact hole.Then, metal film deposition forms source electrode weld pad 60 and drain electrode weld pad 61 on first contact hole and second contact hole.
At last, the 9th step is the step that forms grid.In this case, grid is a bottom gate 64, and it is formed the downside that is positioned at silicon substrate 12, is preferably located in the quantum dot below.Bottom gate 64 is used to control quantum dot, and can any additional technology manufacturing.Particularly, after the metal silicide quantum dot forms, when on the silicide quantum dot, heat-treating, can deform.For this reason, can greatly avoid distortion.In this case, to be manufactured to thickness be that 100nm is to 500nm to bottom gate.
When a plurality of metal silicide quantum dot 41 bunchiness are provided with, to compare with the single-electron device by the single quantum dot definition of routine, single-electron device of the present invention has low relatively electric capacity, thus it can at room temperature move.
Simultaneously, the present invention includes the single-electron device of the room temperature-operating that utilizes aforementioned manufacture method manufacturing.
Commercial Application
Though present invention is described in conjunction with aforementioned preferred embodiments, it should be understood that and to carry out various modifications and change to the present invention under the premise without departing from the spirit and scope of the present invention.Therefore appended claims will comprise within the spirit and scope of the present invention modification and change.
Claims (19)
1. the manufacture method of the single-electron device of a room temperature-operating, described manufacture method comprises:
First step: form the SOI substrate by on silicon substrate (12), piling up insulating barrier (11) and silicon layer (10) in turn, the described silicon layer (10) of the described SOI substrate of etching, thus be formed with source region (10a);
Second step: partly go up in the central channel of described active area (10a) and to form mask (20), foreign ion is injected into forms source area and drain region in the part of described active area (10a);
Third step: on the whole top surface of described SOI substrate, form silicon oxide film (30);
The 4th step: the described channel part of the described active area 10a of etching and form silicide groove (31);
The 5th step: deposition oxide film (40) on the whole top surface of described SOI substrate;
The 6th step: depositing metallic films (42) on the whole top surface of described oxidation film;
The 7th step: the part of described metal film (42) is heat-treated to realize the silication of metal dots, remove the described metal film (42) of described silicon oxide film (30) and not silication thereby the silicide quantum dot (41) that the formation bunchiness is arranged;
The 8th step: on the whole top surface of described SOI substrate, deposit oxidation film of grid (50a and 50b);
The 9th step: the described oxidation film of grid of etching (50a and 50b) be positioned at the source electrode (13) at the two ends that are formed on described active area (10a) and drain electrode (14) thus the top on a part form each contact hole, thereby depositing metallic films forms source electrode weld pad (60) and the weld pad (61) that drains to fill described contact hole; And
The tenth step: go up formation resist pattern to form grid at described silicide groove (31).
2. manufacture method according to claim 1, wherein said active area (10a) have the width of 1nm to the length of 100nm and 10nm to 15nm.
3. manufacture method according to claim 1, wherein said active area (10a) utilize photoetching, electron beam lithography or reactive ion etching to form.
4. manufacture method according to claim 1, wherein said silicon oxide film (30) has the thickness of 2nm to 10nm.
5. manufacture method according to claim 1, wherein in described third step, described silicon layer (10) has the width of 40nm to the thickness of 45nm and 6nm to 10nm.
6. manufacture method according to claim 1, wherein in described the 4th step, the described channel part of described active area (10a) utilizes reactive ion etching to carry out etching, to have the thickness of 2nm to 10nm.
7. manufacture method according to claim 1, wherein in described the 5th step, described oxidation film (40) forms by this way: be placed in the hydrogenperoxide steam generator or in the air and form.
8. manufacture method according to claim 1, wherein in described the 6th step, described metal film (42) is made by cobalt.
9. manufacture method according to claim 1 wherein in described the 6th step, utilizes electron-beam evaporator or molecular beam epitaxy device to deposit described metal film (42), make the thickness of described metal film (42) at 0.1nm in the scope of 1nm.
10. manufacture method according to claim 1, wherein in described the 7th step, described metal film (42) thus form described silicide quantum dot (41) by the heat treatment of electron beam lithography process quilt.
11. manufacture method according to claim 1, wherein said silicon oxide film (30) is removed by utilizing the buffer oxide etching agent, and the described metal film (42) of not silication is removed by the mixed solution that utilizes sulfuric acid and hydrogenperoxide steam generator.
12. manufacture method according to claim 11, each has the diameter of 2nm to 10nm in the wherein said silicide quantum dot (41), and the number of described silicide quantum dot is 1 to 50.
13. manufacture method according to claim 1, wherein in described the 8th step, described oxidation film of grid forms by chemical vapour deposition (CVD) has the thickness of 30nm to 50nm.
14. manufacture method according to claim 1, wherein in described the 8th step, described oxidation film of grid has the thickness of 100nm to 300nm, and described oxidation film of grid utilizes chemical vapour deposition (CVD) to form on described silicide groove (31) to have the thickness of 30nm to 50nm.
15. manufacture method according to claim 2, wherein in described the tenth step, described grid is control grid (62) or "T"-shaped grid (63).
16. manufacture method according to claim 1, wherein said grid have the thickness of 100nm to 500nm.
17. the manufacture method of the single-electron device of a room temperature-operating, described method comprises:
First step: form the SOI substrate by on silicon substrate (12), piling up insulating barrier (11) and silicon layer (10) in turn, the described silicon layer (10) of the described SOI substrate of etching, thus be formed with source region (10a);
Second step: partly go up in the central channel of described active area (10a) and to form mask (20), foreign ion is injected into forms source area and drain region in the part of described active area (10a);
Third step: on the whole top surface of described SOI substrate, form silicon oxide film (30);
The 4th step: the described silicon oxide film (30) by utilizing described channel part as the described active area of mask etching (10a) thus described channel part form silicide groove (31);
The 5th step: depositing metallic films (42) on the whole top surface of described SOI substrate, and make described metal film silication;
The 6th step: remove the described metal film (42) of described silicon oxide film (30) and not silication thereby the silicide quantum dot (41) that the formation bunchiness is arranged;
The 7th step: on the whole top surface of described SOI substrate, form diaphragm (70);
The 8th step: thereby etching is positioned at the described diaphragm (70) on the top of the source electrode that is formed on described active area (10a) two ends and drain electrode forms each contact hole, thereby depositing metallic films forms source electrode weld pad (60) and the weld pad (61) that drains to fill described contact hole; And
The 9th step: depositing metallic films at the downside of described SOI substrate to form bottom gate.
18. the single-electron device of the room temperature-operating of a manufacture method manufacturing according to claim 1.
19. the single-electron device of the room temperature-operating of a manufacture method manufacturing according to claim 17.
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| KR1020070093890 | 2007-09-14 | ||
| KR1020070093890A KR100966008B1 (en) | 2007-09-14 | 2007-09-14 | Room Temperature-operating Single-Electron Device and the Fabrication Method thereof |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102054871A (en) * | 2010-10-27 | 2011-05-11 | 清华大学 | High-speed semiconductor device structure and forming method thereof |
| CN102148250A (en) * | 2011-01-07 | 2011-08-10 | 清华大学 | High-speed low-noise semiconductor device structure and method for forming same |
| CN101800242B (en) * | 2009-02-11 | 2013-03-06 | 中国科学院微电子研究所 | Nano electronic device using nano crystal material as coulomb island and its making method |
| WO2013033875A1 (en) * | 2011-09-07 | 2013-03-14 | 中国科学院微电子研究所 | Method for manufacturing electrode and connection in back gate process |
| CN107492493A (en) * | 2016-06-12 | 2017-12-19 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100468834B1 (en) * | 1998-10-09 | 2005-04-06 | 삼성전자주식회사 | Single electron transistor using oxidation process and manufacturing method |
| KR100408520B1 (en) * | 2001-05-10 | 2003-12-06 | 삼성전자주식회사 | Single electron memory device comprising quantum dots between gate electrode and single electron storage element and method for manufacturing the same |
| KR100418182B1 (en) * | 2001-11-28 | 2004-02-11 | 학교법인 한국정보통신학원 | Method for manufacturing a silicon single electron transistor memory device |
-
2007
- 2007-09-14 KR KR1020070093890A patent/KR100966008B1/en active IP Right Grant
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101800242B (en) * | 2009-02-11 | 2013-03-06 | 中国科学院微电子研究所 | Nano electronic device using nano crystal material as coulomb island and its making method |
| CN102054871A (en) * | 2010-10-27 | 2011-05-11 | 清华大学 | High-speed semiconductor device structure and forming method thereof |
| CN102148250A (en) * | 2011-01-07 | 2011-08-10 | 清华大学 | High-speed low-noise semiconductor device structure and method for forming same |
| WO2013033875A1 (en) * | 2011-09-07 | 2013-03-14 | 中国科学院微电子研究所 | Method for manufacturing electrode and connection in back gate process |
| CN107492493A (en) * | 2016-06-12 | 2017-12-19 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN107492493B (en) * | 2016-06-12 | 2021-03-09 | 中芯国际集成电路制造(上海)有限公司 | Method for forming transistor |
Also Published As
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| KR100966008B1 (en) | 2010-06-24 |
| KR20090028360A (en) | 2009-03-18 |
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