CN110491940A - A kind of nano-wire transistor and preparation method thereof based on resonance tunnel-through - Google Patents
A kind of nano-wire transistor and preparation method thereof based on resonance tunnel-through Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66431—Unipolar field-effect transistors with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
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- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of nano-wire transistor based on resonance tunnel-through, the nano-wire transistor include: SOI substrate, tunneling barrier structure, source region, drain region, nano wire, grid, source electrode, drain electrode, gate electrode and insulating medium layer.Tunneling barrier structure is located in the buries oxide layer of SOI substrate, source region, drain region and nano wire are formed by etching the top layer silicon of SOI substrate, nano wire is between source region and drain region, it is not directly connected between source region, drain region and nano wire, is connected by tunneling barrier structure, insulating medium layer is formed in source region, drain region and nanowire surface, grid is formed on the insulating medium layer above nano wire, source electrode is formed in source region, and drain electrode is formed on drain region, and gate electrode is formed on grid.The structure of nano-wire transistor and preparation method thereof disclosed by the invention based on resonance tunnel-through reduces sub-threshold slope, biggish conducting electric current and lesser source-drain contact resistance may be implemented.
Description
Technical field
The present invention relates to semiconductor devices manufacture technology fields, and in particular to a kind of nanowire crystal based on resonance tunnel-through
Pipe and preparation method thereof.
Background technique
With being constantly progressive for ic manufacturing technology, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device
Part size persistently reduces, and MOSFET technology node has entered 7nm at present.If device size is maintained to further reduce, need to overcome
Device principle and technologic lot of challenges, e.g., short-channel effect, the production etc. of PN junction.
Without knot, silicon nano line transistor preparation process is simple, and source, leakage, the unified doping of channel region do not need the production of knot
To alleviate super steep knot intermediate ion injection and annealing bring pressure.Meanwhile no knot silicon nano line transistor is enclosing structure, energy
It is enough preferably to inhibit short-channel effect.And device preparation technology is compatible with conventional bulk silicon CMOS technology, therefore is increasingly becoming and grinds
Study carefully hot spot.However, transporting essential still consistent with conventional MOS FET, Asia without knot silicon nano line transistor for conventional
Threshold slope is greater than 60mV/decade, and nodeless mesh body pipe off-state current is bigger compared with conventional MOS FET off-state current, increases
Quiescent dissipation.
Tunneling transistor may be implemented the off-state current of very little and be less than because being transported by quantum tunneling
The sub-threshold slope of 60mV/decade, but tunneling transistor relies on structure design realization more, structure is complicated, it is difficult to meet more
The requirement of small technology node.Therefore, if the two advantage can be combined, better property can be prepared with simpler technique
The device of energy has researching value very much, but there is not been reported for the nano-wire transistor based on tunnelling.
Summary of the invention
(1) technical problems to be solved
The purpose of the present invention is to provide a kind of nano-wire transistor and preparation method thereof based on resonance tunnel-through, to realize
The new device of both tunneling transistor and nano-wire transistor advantage is taken into account, realizes and reduces sub-threshold slope, is had biggish
Conducting electric current and lesser source-drain contact resistance.
(2) technical solution
The present invention provides a kind of nano-wire transistors based on resonance tunnel-through, comprising: SOI substrate 1, tunneling barrier structure
2, source region 3, drain region 4, nano wire 5, grid 6, source electrode 7, drain electrode 8, gate electrode 9 and insulating medium layer 10；
Tunneling barrier structure 2 is located in the buries oxide layer of SOI substrate 1；
Source region 3, drain region 4 and nano wire 5 are formed by etching the top layer silicon of SOI substrate 1；
Nano wire 5 is not directly connected between source region 3, drain region 4 and nano wire 5 between source region 3 and drain region 4, passes through tunnel
Barrier structure 2 is worn to be connected；
Insulating medium layer 10 is formed in 5 surface of source region 3, drain region 4 and nano wire；
Grid 6 is formed on the insulating medium layer 10 of 5 top of nano wire；
Source electrode 7 is formed in source region 3；
Drain electrode 8 is formed on drain region 4；
Gate electrode 9 is formed on grid 6.
In order to achieve the above object, the present invention also provides a kind of preparation method of nano-wire transistor based on resonance tunnel-through,
Include:
Thermal oxide layer is made in SOI substrate 1, and the SOI substrate 1 under thermal oxide layer is doped；
Electron beam exposure, silica etching are successively carried out to thermal oxide layer, and then the SOI substrate 1 after doping is carried out
Silicon etching exposes the buried oxide layer of SOI substrate 1, obtains nanometer channel；
Nanometer channel side is corroded, realizes the smooth of side atom level；
Pass through atomic layer deposition ALD deposition SiO2Realization is filled up completely nanometer channel；
Remove the SiO of atomic layer deposition deposition2With the SiO of hot oxygen2Layer only retains the SiO in nanometer channel2, form double gesture
Build structure；
To the substrate after dual potential barrier structure is made by electron beam exposure and etching operation, nano wire 5,3 and of source region are made
Drain region 4；
In source region 3, drain region 4 and channel region Surface Creation insulating medium layer 10；
Conductive layer is covered on insulating medium layer 10；
Grid 6 is produced on the electrically conductive；
It makes source electrode 7, drain electrode 8 and gate electrode 9 respectively on source region 3, drain region 4 and grid 6, completes the system of device
It is standby.
(3) beneficial effect
1, the nano-wire transistor and preparation method thereof provided by the invention based on resonance tunnel-through, by introducing tunneling barrier
Structure and multi-panel grid structure effectively improve grid-control ability, and tunneling transmission may be implemented based on resonant tunneling structure, reduce
Sub-threshold slope.
2, the nano-wire transistor and preparation method thereof provided by the invention based on resonance tunnel-through, it is unified heavily doped by introducing
Miscellaneous nano wire and source-drain area, may be implemented biggish conducting electric current and lesser source-drain contact resistance.
3, the nano-wire transistor and preparation method thereof provided by the invention based on resonance tunnel-through, by using TMAH solution
Corroded, can while not introducing metallic pollution, to nano wire section carry out atom level it is smooth, later by ALD into
The filling of row dielectric realizes dual potential barrier structure preparation, enhances the consistency of tunneling barrier structure, ensure that resonance tunnel-through
Realization.
4, ion is infused in the nano-wire transistor and preparation method thereof provided by the invention based on resonance tunnel-through, device preparation
Enter technique and annealing process requirement is low, simple process is compatible with CMOS technology, easy to promote and utilize.
Detailed description of the invention
Fig. 1 is the schematic three dimensional views of the nano-wire transistor based on resonance tunnel-through of the embodiment of the present invention；
Fig. 2 be the embodiment of the present invention based on the nano-wire transistor of resonance tunnel-through in Fig. 1 along AB line section after cross
Sectional view；
Fig. 3 is the schematic three dimensional views that the SOI substrate after thermal oxide is carried out according to the embodiment of the present invention；
Fig. 4 is to pass through electron beam exposure (EBL) to the SOI substrate for carrying out overdoping according to the embodiment of the present invention, etch it
Nanometer channel structural schematic diagram afterwards；
Fig. 5 is to backfill the structural schematic diagram after nanometer channel by atomic layer deposition (ALD) according to the embodiment of the present invention；
Fig. 6 is to pass through back the oxide layer for etching away atomic layer deposition (ALD) deposition and hot oxygen according to the embodiment of the present invention
Oxide layer after structural schematic diagram；
Fig. 7 is to pass through on substrate according to the embodiment of the present invention after lithography and etching defines nanowire, source region and drain region
Structural schematic diagram；
Fig. 8 is that gate insulator dielectric layer is prepared according to the embodiment of the present invention, deposit polycrystalline silicon, and is defined by chemical wet etching
Structural schematic diagram after grid out.
Specific embodiment:
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
Attached drawing, the present invention is described in more detail.
As shown in FIG. 1, FIG. 1 is the three-dimensional signals for the nano-wire transistor based on resonance tunnel-through for being the embodiment of the present invention
Figure, which includes: SOI substrate 1, tunneling barrier structure 2, source region 3, drain region 4, nano wire 5, grid 6, source electrode
7, drain electrode 8, gate electrode 9 and insulating medium layer 10.
Source region 3, drain region 4 and nano wire 5 are formed by etching the top layer silicon of SOI substrate 1, and nano wire 5 is located at source region 3 and leakage
It between area 4, is not connected directly between source region 3, drain region 4 and nano wire 5, the tunnelling in buries oxide layer by being located at SOI substrate 1
Barrier structure 2 is connected；Insulating medium layer 10 is formed in 5 surface of source region 3, drain region 4 and nano wire；Grid 6 is formed on nano wire 5
On the insulating medium layer 10 of side；Drain electrode 8 is formed on drain region 4；Source electrode 7 is formed in source region 3；Gate electrode 9 is formed in grid
On pole 6.
Insulating medium layer 10 is SiO2, nitrogen oxides, TiO2、HfO2、Si3N4、ZrO2、Ta2O5, barium strontium titanate BST, zirconium titanium
Lead plumbate piezoelectric ceramics PZT or Al2O3, insulating medium layer 10 is with a thickness of 1 to 10 nanometer.Conductive layer is covered on insulating medium layer 10, is led
The conductive material of electric layer is polysilicon or aluminium, platinum, nickel, and conductive layer thickness is 50 to 400 nanometers.Dual potential barrier structure 2 is to pass through
Atomic layer deposition (ALD) deposits SiO2Realization is filled up completely nanometer channel, removes the silica of atomic layer deposition later
With the silicon dioxide layer of hot oxygen, only retain what the silica in nanometer channel was formed, the SiO of technique for atomic layer deposition deposition2
With a thickness of 2 to 30 nanometers.Source electrode 7, drain electrode 8 and gate electrode 9 are respectively by passing through on source region 3, drain region 4 and grid 6
Addition electrode material is made.Electrode material is aluminium, gold, nickel, titanium or platinum.
Based on the nano-wire transistor shown in FIG. 1 based on resonance tunnel-through, the present invention also provides one kind be based on resonance tunnel
The preparation method for the nano-wire transistor worn, method includes the following steps:
Step 1: making thermal oxide layer in SOI substrate 1；
Specifically, as shown in figure 3, carrying out thermal oxide, hot oxygen to the top layer silicon face of SOI substrate 1 at a temperature of 1000 DEG C
Time is 20 to 60 minutes, forms the thermal oxide layer of 10 to 30 nanometer thickness.SOI substrate 1 includes top layer silicon, buries oxide layer, backing
Bottom, buries oxide layer is between top layer silicon and backing bottom.
Step 2: the SOI substrate 1 under thermal oxide layer is doped；
As shown in figure 3, be doped to the SOI substrate 1 Jing Guo thermal oxide by ion implanting, after injection 900 to
Quick thermal annealing process 10 to 60 seconds at a temperature of 1100 DEG C, activator impurity atom.Wherein, doping type is N-type or p-type, is mixed
Miscellaneous concentration is 1016To 1019cm-3, Implantation Energy is 20 kilo electron volts to 50 kilo electron volts.
Step 3: thermal oxide layer is successively carried out electron beam exposure, silica etching, to the SOI substrate 1 after doping into
Row silicon etching exposes the buried oxide layer of SOI substrate 1, obtains nanometer channel；
As shown in figure 4, passing through electron beam exposure, silica etching, silicon etching, edge to the SOI substrate 1 for carrying out overdoping
Two nanometer channels are produced perpendicular to<111>direction, expose buried oxide layer at groove.Wherein, electron beam exposure and silica
Etching is handled thermal oxide layer, and silicon etching is the top layer silicon below the thermal oxide layer being directed to, and silicon etching needs etch into
Buried oxide layer is exposed.Nanometer channel is 2 to 10 nanometers along<111>direction width, and two nanometer channel width will be consistent.Two
2 to 50 nanometers of nanometer channel interval.
Step 4: nanometer channel side being corroded, realizes the smooth of side atom level；
As shown in figure 4, corroding nanometer channel side by tetramethylammonium hydroxide (TMAH), realize to nanometer channel side
It is smooth, realize side atom level it is smooth, thus enhancing two nanometer channels consistency.Wherein sideetching is with a thickness of 1
To 4 nanometers.
Step 5: SiO is deposited by atomic layer deposition (ALD)2Realization is filled up completely nanometer channel；
As shown in figure 5, depositing SiO by atomic layer deposition (ALD)2, nanometer channel is filled, guarantees that groove is complete
Filling, the SiO of technique for atomic layer deposition deposition2With a thickness of 2 to 30 nanometers.
Step 6: the silica of removal atomic layer deposition deposition and the silicon dioxide layer of hot oxygen only retain in nanometer channel
Silica, formed dual potential barrier structure；
As shown in fig. 6, by etching or chemically-mechanicapolish polishing (CMP), the silica of removal atomic layer deposition deposition
With the silicon dioxide layer of hot oxygen, only retains the silica in nanometer channel, form dual potential barrier structure.Expose large area
Silicon realizes the production of tunneling barrier structure 2.
Step 7: to the substrate after dual potential barrier structure is made by electron beam exposure and etching operation, making nano wire 5, source
Area 3 and drain region 4；
As shown in fig. 7, to the substrate after dual potential barrier structure is made by electron beam exposure (EBL) and etches, production cashier
Rice noodles 5, source region 3 and drain region 4, wherein etching is specifically to the silicon of large area and the thermal oxide layer of a part of resonant tunneling structure
Production nanowire 5 is performed etching, source region 3 and drain region 4, rest part etch into buries oxide layer, and wherein the silicon of large area is top
Layer silicon, nano wire 5 are 5 nanometers × 5 nanometers to 50 nanometers × 50 nanometers along<111>direction sectional dimension.Nano wire 5 is axial can be with
For<111>, there can also be non-90 degree angle with nano-channel.Nano wire 5 along<111>direction length be 2 to 50 nanometers, both ends with
Barrier structure 2 is connected.
Step 8: in source region 3, drain region 4 and channel region Surface Creation insulating medium layer 10；
As shown in Fig. 7, Fig. 8 and Fig. 2, by thermal oxide or atomic layer deposition on source region 3, drain region 4 and channel region surface
Generate insulating medium layer 10.Insulating medium layer 10 can be SiO2, nitrogen oxides, TiO2、HfO2、Si3N4、ZrO2、Ta2O5, metatitanic acid
Strontium barium BST, lead titanate piezoelectric ceramics PZT or Al2O3.Insulating medium layer 10 is with a thickness of 1 to 10 nanometer.Fig. 2 is thermal oxide SiO2
The case where as insulating medium layer 10.
Step 9: covering conductive layer on insulating medium layer 10；
Conductive layer is covered on insulating medium layer 10 by chemical vapor deposition or metal sputtering.Conductive material can be
The metals such as polysilicon or aluminium, platinum, nickel.Conductive layer thickness is 50 to 400 nanometers.
Step 10: producing grid 6 on the electrically conductive；
As shown in fig. 7, producing grid 6 on the electrically conductive by electron beam exposure and etching, grid length is 2 to 80nm.
Step 11: making source electrode 7, drain electrode 8 and gate electrode 9 respectively on source region 3, drain region 4 and grid 6, complete device
The preparation of part；
As shown in Figure 1, on source region 3, drain region 4 and grid 6 by addition electrode material realize respectively make source electrode 7,
Drain electrode 8 and gate electrode 9, complete the preparation of device.Electrode material can be the metals such as aluminium, gold, nickel, titanium, platinum.
Nano-wire transistor and preparation method thereof provided by the invention based on resonance tunnel-through, by nano-wire transistor
Middle extraction resonant tunneling structure, can be realized less than the sub-threshold slope of 60mV/decade and biggish on-state current；In addition,
This nano-wire transistor based on resonance tunnel-through provided by the invention, device preparation technology compared with conventional MOS FET simple process,
And it is compatible with CMOS technology.
Particular embodiments described above has carried out further in detail the purpose of the present invention, technical scheme and beneficial effects
It describes in detail bright, it should be understood that the above is only a specific embodiment of the present invention, is not intended to restrict the invention, it is all
Within the spirit and principles in the present invention, any modification, equivalent substitution, improvement and etc. done should be included in guarantor of the invention
Within the scope of shield.
Claims (14)
1. a kind of nano-wire transistor based on resonance tunnel-through, which is characterized in that the nano-wire transistor include SOI substrate (1),
Tunneling barrier structure (2), source region (3), drain region (4), nano wire (5), grid (6), source electrode (7), drain electrode (8), gate electrode
(9) and insulating medium layer (10), in which:
Tunneling barrier structure (2) is located in the buries oxide layer of SOI substrate (1)；
Source region (3), drain region (4) and nano wire (5) are formed by etching the top layer silicon of SOI substrate (1)；
Nano wire (5) is located between source region (3) and drain region (4), does not connect directly between source region (3), drain region (4) and nano wire (5)
It connects, is connected by tunneling barrier structure (2)；
Insulating medium layer (10) is formed in source region (3), drain region (4) and nano wire (5) surface；
Grid (6) is formed on the insulating medium layer (10) above nano wire (5)；
Source electrode (7) is formed on source region (3)；
Drain electrode (8) is formed on drain region (4)；
Gate electrode (9) is formed on grid (6).
2. the nano-wire transistor based on resonance tunnel-through according to weighing and require 1, which is characterized in that the insulating medium layer
It (10) is SiO2, nitrogen oxides, TiO2、HfO2、Si3N4、ZrO2、Ta2O5, barium strontium titanate BST, lead titanate piezoelectric ceramics PZT or
Al2O3, insulating medium layer (10) is with a thickness of 1 to 10 nanometer.
3. the nano-wire transistor based on resonance tunnel-through according to weighing and require 1, which is characterized in that the insulating medium layer
(10) conductive layer is covered on, the conductive material of conductive layer is polysilicon or aluminium, platinum, nickel, and conductive layer thickness is received for 50 to 400
Rice.
4. the nano-wire transistor based on resonance tunnel-through according to weighing and require 1, which is characterized in that the dual potential barrier structure
It (2) is that SiO is deposited by atomic layer deposition (ALD)2Realization is filled up completely nanometer channel, removes atomic layer deposition later
The silicon dioxide layer of silica and hot oxygen only retains what the silica in nanometer channel was formed, and technique for atomic layer deposition is heavy
Long-pending SiO2With a thickness of 2 to 30 nanometers.
5. the nano-wire transistor according to claim 1 based on resonance tunnel-through, which is characterized in that the source electrode (7),
Drain electrode (8) and gate electrode (9) are respectively by passing through addition electrode material system on source region (3), drain region (4) and grid (6)
At.
6. the nano-wire transistor according to claim 5 based on resonance tunnel-through, which is characterized in that the electrode material is
Aluminium, gold, nickel, titanium or platinum.
7. a kind of preparation method of the nano-wire transistor based on resonance tunnel-through, which comprises the following steps:
Thermal oxide layer is made on SOI substrate (1), and the SOI substrate (1) under thermal oxide layer is doped；
Electron beam exposure, silica etching are successively carried out to thermal oxide layer, and silicon etching is carried out to the SOI substrate (1) after doping,
The buried oxide layer for exposing SOI substrate (1), obtains nanometer channel；
Nanometer channel side is corroded, realizes the smooth of side atom level；
SiO is deposited by atomic layer deposition (ALD)2Realization is filled up completely nanometer channel；
Remove the SiO of atomic layer deposition deposition2With the SiO of hot oxygen2Layer only retains the SiO in nanometer channel2, form double potential barrier knot
Structure；
Electron beam exposure and etching operation are carried out to the SOI substrate (1) after dual potential barrier structure is made, makes nano wire (5), source region
(3) and drain region (4)；
In source region (3), drain region (4) and channel region Surface Creation insulating medium layer (10)；
Conductive layer is covered on insulating medium layer (10)；
Grid (6) are produced on the electrically conductive；
It makes source electrode (7), drain electrode (8) and gate electrode (9) respectively on source region (3), drain region (4) and grid (6), completes device
The preparation of part.
8. the preparation method of the nano-wire transistor according to claim 7 based on resonance tunnel-through, which is characterized in that described
Thermal oxide layer is made on SOI substrate (1) includes:
Thermal oxide is carried out to the top layer silicon face of SOI substrate (1) at a temperature of 1000 DEG C, the hot oxygen time is 20 to 60 minutes, shape
At the thermal oxide layer of 10 to 30 nanometer thickness.
9. the preparation method of the nano-wire transistor according to claim 7 based on resonance tunnel-through, which is characterized in that described
SOI substrate (1) under thermal oxide layer is doped, comprising:
The SOI substrate (1) under thermal oxide layer is doped by ion implanting, doping type is N-type or p-type, doping
Concentration is 1016To 1019cm-3, Implantation Energy is 20 kilo electron volts to 50 kilo electron volts；
After ion implanting quick thermal annealing process 10 to 60 seconds at a temperature of 900 to 1100 DEG C, activator impurity atom.
10. the preparation method of the nano-wire transistor according to claim 7 based on resonance tunnel-through, which is characterized in that institute
In the step of stating and carry out silicon etching to the SOI substrate (1) after doping, exposing the buried oxide layer of SOI substrate (1), obtain nanometer channel,
Silicon etching is handled the top layer silicon below thermal oxide layer, and silicon etching needs to etch into exposing buried oxide layer, by silicon etching
Two nanometer channels are produced, nanometer channel is 2 to 10 nanometers along width, and two nanometer channel equivalent widths, two nanometers
2 to 50 nanometers of groove interval.
11. the preparation method of the nano-wire transistor according to claim 7 based on resonance tunnel-through, which is characterized in that institute
It states and nanometer channel side is corroded, comprising:
Nanometer channel side is corroded using tetramethylammonium hydroxide (TMAH), sideetching is with a thickness of 1 to 4 nanometer.
12. the preparation method of the nano-wire transistor according to claim 7 based on resonance tunnel-through, which is characterized in that institute
It states to the SOI substrate (1) after dual potential barrier structure is made by electron beam exposure and etching operation, makes nano wire (5), source region
(3) and drain region (4), comprising:
To the SOI substrate (1) after dual potential barrier structure is made by electron beam exposure and etching, make nanowire (5), source region
(3) and drain region (4), wherein etching is specifically to carve to the silicon of large area and the thermal oxide layer of a part of resonant tunneling structure
Erosion production nanowire (5), source region (3) and drain region (4), rest part etch into buries oxide layer, and wherein the silicon of large area is top
Layer silicon, nano wire (5) sectional dimension are 5 nanometers × 5 nanometers to 50 nanometers × 50 nanometers, and nano wire (5) is received along length for 2 to 50
Rice, both ends are connected with tunneling barrier structure (2).
13. the preparation method of the nano-wire transistor according to claim 7 based on resonance tunnel-through, which is characterized in that institute
It states in source region (3), drain region (4) and channel region Surface Creation insulating medium layer (10), comprising:
By thermal oxide or atomic layer deposition in source region (3), drain region (4) and channel region Surface Creation insulating medium layer (10).
14. the preparation method of the nano-wire transistor according to claim 7 based on resonance tunnel-through, which is characterized in that institute
It states and produces grid (6) on the electrically conductive, comprising:
It is produced on the electrically conductive grid (6) by electron beam exposure and etching, grid length is 2 to 80nm.
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| CN112614865A (en) * | 2020-12-15 | 2021-04-06 | 中国科学院半导体研究所 | Non-junction silicon nanowire transistor based on phase change material storage gate and preparation method |
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| CN101123274A (en) * | 2006-08-09 | 2008-02-13 | 中国科学院微电子研究所 | SOI-based top gate single-electron transistor and preparation method thereof |
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