CN104867834A - Single-impurity atom junction-free silicon nano wire transistor based on SOI substrate, and preparation method thereof - Google Patents
Single-impurity atom junction-free silicon nano wire transistor based on SOI substrate, and preparation method thereof Download PDFInfo
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- CN104867834A CN104867834A CN201510192461.8A CN201510192461A CN104867834A CN 104867834 A CN104867834 A CN 104867834A CN 201510192461 A CN201510192461 A CN 201510192461A CN 104867834 A CN104867834 A CN 104867834A
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- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 105
- 239000010703 silicon Substances 0.000 title claims abstract description 105
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 96
- 239000002070 nanowire Substances 0.000 title claims abstract description 68
- 239000000758 substrate Substances 0.000 title claims abstract description 58
- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 239000012535 impurity Substances 0.000 title abstract 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 238000009413 insulation Methods 0.000 claims abstract description 5
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 11
- 238000000576 coating method Methods 0.000 claims description 11
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 9
- 238000005530 etching Methods 0.000 claims description 9
- 238000010884 ion-beam technique Methods 0.000 claims description 9
- 150000003376 silicon Chemical class 0.000 claims description 9
- 241000216843 Ursus arctos horribilis Species 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 6
- 238000002347 injection Methods 0.000 claims description 6
- 239000007924 injection Substances 0.000 claims description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 4
- 229910004140 HfO Inorganic materials 0.000 claims description 4
- 239000000463 material Substances 0.000 claims description 4
- 239000010409 thin film Substances 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 2
- 239000000243 solution Substances 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 abstract description 3
- 229920005591 polysilicon Polymers 0.000 abstract 2
- 238000000034 method Methods 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000010894 electron beam technology Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009616 inductively coupled plasma Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000002096 quantum dot Substances 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/775—Field effect transistors with one dimensional charge carrier gas channel, e.g. quantum wire FET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The invention discloses a single-impurity atom junction-free silicon nano wire transistor based on an SOI substrate, and a preparation method thereof. The single-impurity atom junction-free silicon nano wire transistor based on the SOI substrate comprises: an SOI substrate; a source region which is disposed at one side of the upper surface of the SOI substrate; a drain region which is disposed at the other side of the upper surface of the SOI substrate; a silicon nano wire which is disposed on the SOI substrate and is connected with the source region and the drain region; an insulation medium film layer which is prepared at the silicon nano wire and the surfaces of the source region and the drain region; a polysilicon grid which is prepared on the silicon nano wire between the source region and the drain region and at the two sides, is vertical to the silicon nano wire and exposes a part of the insulation medium film layer at the two sides of the polysilicon grid; a source electrode which is prepared on the source region; a drain electrode which is prepared on the drain region; and a grid electrode prepared on the grid. The single-impurity atom junction-free silicon nano wire transistor simplifies the structure and realizes accurate control of the number of implanted ions.
Description
Technical field
Even if the present invention relates to semiconductor device to make field, be specifically related to a kind of single foreign atom based on SOI substrate without knot silicon nano line transistor and preparation method thereof.
Background technology
Along with the continuous progress of ic manufacturing technology, the technology node of current metal-oxide semiconductor fieldeffect transistor (MOSFET) has entered into the 14nm stage, device physics grid are long is less than 20nm, and device architecture also develops into the three-dimensional structure of silicon nanowires gradually from planar structure.Along with device size continue reduce, its facing challenges is also increasing, therefore becomes the focus of research based on the nano electron device of new principle.
In common inversion mode transistor, channel region is different from the doping type of source-drain area, has the formation that pn ties.Along with device dimensions shrink, when device gate long little to 10nm magnitude time, the sudden change of doping content and doping type to be realized in the several nanometer in raceway groove two ends, realize very high doping content gradient, bring huge challenge to ion implantation technology and annealing process thereafter.And nodeless mesh body pipe achieves the unified heavy doping of channel region and source-drain area, channel direction does not exist the change of doping content and type, enormously simplify technology difficulty prepared by device.At present existing multiple seminar silicon on insulator (SOI) substrate successfully achieves without knot silicon nano line transistor, obtain and can to want compare even better performance with traditional inversion mode transistor.
Conducting without knot silicon nano line transistor needs at heavily doped silicon nanowires raceway groove, has the foreign atom of some to participate in conduction in silicon nanowires.And along with device size continue reduce, long constantly the reducing of silicon nanowires and grid, in conducting channel, foreign atom number will constantly reduce, and most extreme case is exactly single foreign atom transistor.
Single foreign atom transistor AND gate single-electronic transistor is similar, the transmission of device charge carrier when normal work be with minute quantity even Single Electron transport.Therefore have very little drain current during devices function, the circuit design for low-power consumption has potential using value.Single foreign atom in single foreign atom transistor, is just equivalent to the quantum-dot structure in single-electronic transistor between source and drain.Therefore, single foreign atom transistor can produce coulomb blockade effect in transport process.
The present invention proposes a kind of method utilizing focused ion beam technology to prepare single foreign atom transistor, accurately can control the number of foreign atom in silicon nanowires, the preparation for monatomic transistor opens a technology path.
Summary of the invention
In view of this, main purpose of the present invention is to provide a kind of single foreign atom based on SOI substrate without knot silicon nano line transistor and preparation method, has designs simplification and the accurate control achieving ion implantation number.
For achieving the above object, the invention provides a kind of single foreign atom based on SOI substrate without knot silicon nano line transistor, comprising:
One SOI substrate;
One source region, this source region is that the top layer silicon by etching SOI substrate obtains, and it is positioned at the side above SOI substrate;
One drain region, this drain region is that the top layer silicon by etching SOI substrate obtains, and it is positioned at the opposite side above SOI substrate;
One silicon nanowires, this silicon nanowires is positioned in SOI substrate, and this silicon nanowires connects source region and drain region;
One dielectric thin layer, this dielectric thin layer is made in the surface in this silicon nanowires and source region, drain region;
One polycrystalline grid, this grizzly bar is made on the silicon nanowires between source region and drain region and both sides, and perpendicular to silicon nanowires, goes out SI semi-insulation dielectric thin film layer in the exposed at both sides of polycrystalline grid;
One source electrode, this source electrode is made on source region;
One drain electrode, this drain electrode is made on drain region; And
One gate electrode, this gate electrode is made on grizzly bar.
The present invention also provides a kind of single foreign atom based on SOI substrate without the preparation method of knot silicon nano line transistor, comprises the steps:
Step 1: make the silicon nanowires of monatomic transistor, source region and drain region figure in the top layer silicon of SOI substrate, etching;
Step 2: generate SiO on the surface and sidewall in silicon nanowires, source region and drain region
2resilient coating;
Step 3: at the mid portion overlay electronic bundle resist of silicon nanowires;
Step 4: adulterated in the silicon nanowires of non-overlay electronic bundle resist, source region and drain region;
Step 5: removal covers the electron sensitive resist of silicon nanowires and generate SiO on silicon nanowires, source region and surface, drain region and sidewall
2resilient coating;
Step 6: adopt focused ion beam technology, realize the injection of single foreign atom at the mid portion of silicon nanowires;
Step 7: short annealing activates the foreign atom of doping;
Step 8: at the substrate surface growth dielectric thin layer of silicon nanowires, source region, drain region and exposure;
Step 9: cover polycrystalline silicon grid layer on dielectric thin layer, and ion implantation doping is carried out to polycrystalline silicon grid layer;
Step 10: etch polycrystalline grid on polycrystalline silicon grid layer; And
Step 11: make source electrode, drain electrode and gate electrode respectively in source region, drain region and polycrystalline grid, completes the preparation of device.
Can read a book from technique scheme, the present invention has following beneficial effect:
(1) the single foreign atom based on SOI substrate provided by the invention is without the preparation method tying silicon nano line transistor, by introducing the focused ion beam technology improved, be positioned on silicon nanowires and inject single foreign atom, the exact controllability of foreign atom number and position can be realized, monatomic transistor can be prepared on soi substrates.
(2) the single foreign atom based on SOI substrate provided by the invention is without the preparation method of knot silicon nano line transistor, and employ the focused ion beam technology of improvement, effectively make use of instrument and equipment, laboratory realizes comparatively simple.
(3) the single foreign atom based on SOI substrate provided by the invention is without the preparation method of knot silicon nano line transistor, and the effective cross section that can effectively reduce channel region silicon nanowires by thermal oxidation is amassed, and realizes the miniaturization of device.
Accompanying drawing explanation
For further illustrating technology contents of the present invention, be described in detail as follows with accompanying drawing in conjunction with the embodiments:
Wherein:
Fig. 1 is the three-dimensional structure schematic diagram of the single foreign atom transistor based on SOI substrate provided by the invention;
Fig. 2 is that the single foreign atom based on SOI substrate provided by the invention is without the preparation method's flow chart tying silicon nano line transistor.
Embodiment
Refer to shown in Fig. 1, the invention provides a kind of single foreign atom based on SOI substrate without knot silicon nano line transistor, comprising:
One SOI substrate 1, from top to bottom, comprises three-decker at the bottom of top layer silicon, oxygen buried layer and backing;
One source region 2, this source region 2 is that the top layer silicon by etching SOI substrate 1 obtains, and it is positioned at the side above SOI substrate 1;
One drain region 3, this drain region 3 is that the top layer silicon by etching SOI substrate 1 obtains, and it is positioned at the opposite side above SOI substrate 1;
One silicon nanowires 4, this silicon nanowires 4 is positioned in SOI substrate 1, and this silicon nanowires 4 connects source region 2 and drain region 3;
Wherein source region 2, drain region 3 and do not adopted N-type or P type to adulterate by the silicon nanowires 4 that polycrystalline grid is wrapped up, doping content is 10
18-10
19cm
-3magnitude;
One dielectric thin layer (not shown), this dielectric thin layer is made in the surface in this silicon nanowires 4 and source region 2, drain region 3, and the material that this dielectric thin layer described adopts is SiO
2, nitrogen oxide, HfO
2, Si
3n
4, ZrO
2, Ta
2o
5, BST or PZT;
One polycrystalline grid 8, this grizzly bar 8 is made on the silicon nanowires 4 between source region 2 and drain region 3 and both sides, and perpendicular to silicon nanowires 4, SI semi-insulation dielectric thin film layer is gone out in the exposed at both sides of polycrystalline grid 8, the part of the described silicon nanowires 4 wrapped up by polycrystalline grid 8 is only containing single foreign atom, the type of foreign atom adopts N-type or the doping of P type, and the type of the foreign atom of described polycrystalline grid 8 adopts P type or N-type doping, and doping content is 10
21-10
23cm
-3magnitude;
One source electrode 9, this source electrode 9 is made on source region 2;
One drain electrode 10, this drain electrode 10 is made on drain region 3; And
One gate electrode 11, this gate electrode 11 is made on grizzly bar 8.
Refer to Fig. 2, and combination is consulted shown in Fig. 1, the invention provides a kind of single foreign atom based on SOI substrate without the preparation method of knot silicon nano line transistor, comprise the steps:
Step 1: utilize electron beam lithography or photoetching technique to make the silicon nanowires 4 of monatomic transistor, source region 2 and drain region 3 figure in the top layer silicon of SOI substrate 1, recycling silicon inductively coupled plasma (ICP) etching, by electron beam adhesive Graphic transitions in the top layer silicon of SOI substrate, form the silicon nanowires of monatomic transistor, 4, source region 2 and drain region 3, complete device isolation;
Step 2: by thermal oxidation, the surface and sidewall in silicon nanowires 4, source region 2 and drain region 3 generate SiO
2resilient coating (not shown), described SiO
2resilient coating adopts hydrofluoric acid solution rinsing, SiO
2the thickness of resilient coating is 10-30nm;
Step 3: coating electron sensitive resist, adopt the exposure of electron-beam direct writing alignment and development, at the mid portion overlay electronic bundle resist of silicon nanowires 4, described is more than 100nm at the thickness of silicon nanowires 4 mid portion overlay electronic bundle resist;
Step 4: ion implantation doping is carried out to the silicon nanowires 4 of non-overlay electronic bundle resist, source region 2 and drain region 3; The type of described foreign atom adopts N-type or the doping of P type, and implantation dosage is 10
18-10
19cm
-3, the injection degree of depth is 20-70nm;
Step 5: removal covers the electron sensitive resist of silicon nanowires 4 and generate SiO on silicon nanowires 4, source region 2 and surface, drain region 3 and sidewall
2resilient coating;
Step 6: adopt focused ion beam technology, the injection of single foreign atom is realized at the mid portion of silicon nanowires 4, described focused ion beam technology is in conjunction with chopper, by controlling the signal dutyfactor of focused ion beam current value, chopper, control the number of ions by chopper in the unit interval, thus realize the injection of single Doped ions, the type of foreign atom adopts N-type or the doping of P type;
Step 7: short annealing activates the foreign atom of doping, described annealing temperature 1000 DEG C, annealing time 10 seconds;
Step 8: at silicon nanowires 4, source region 2, drain region 3 and the substrate surface growth dielectric thin layer that exposes, the material of described dielectric thin layer is SiO
2, nitrogen oxide, HfO
2, Si
3n
4, ZrO
2, Ta
2o
5, BST or PZT;
Step 9: cover polycrystalline silicon grid layer by chemical vapour deposition (CVD) on dielectric thin layer, and ion implantation doping is carried out to polycrystalline silicon grid layer, the type of foreign atom adopts P type or N-type doping, and doping content is 10
21-10
23cm
-3magnitude;
Step 10: etch polycrystalline grid 8 on polycrystalline silicon grid layer, the part of the described silicon nanowires 4 wrapped up by polycrystalline grid 8 is only containing single foreign atom;
Step 11: make source electrode 9, drain electrode 10 and gate electrode 11 respectively in source region 2, drain region 3 and polycrystalline grid 8, complete the preparation of device.
Single foreign atom based on SOI substrate provided by the invention is without the preparation method tying silicon nano line transistor, by introducing focused ion beam technology, be positioned on silicon nanowires and inject single foreign atom, the exact controllability of foreign atom number and position can be realized, monatomic transistor can be prepared on soi substrates.
Above-described specific embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., be all included in protection scope of the present invention.
Claims (10)
1. based on SOI substrate single foreign atom without knot a silicon nano line transistor, comprising:
One SOI substrate;
One source region, this source region is that the top layer silicon by etching SOI substrate obtains, and it is positioned at the side above SOI substrate;
One drain region, this drain region is that the top layer silicon by etching SOI substrate obtains, and it is positioned at the opposite side above SOI substrate;
One silicon nanowires, this silicon nanowires is positioned in SOI substrate, and this silicon nanowires connects source region and drain region;
One dielectric thin layer, this dielectric thin layer is made in the surface in this silicon nanowires and source region, drain region;
One polycrystalline grid, this grizzly bar is made on the silicon nanowires between source region and drain region and both sides, and perpendicular to silicon nanowires, goes out SI semi-insulation dielectric thin film layer in the exposed at both sides of polycrystalline grid;
One source electrode, this source electrode is made on source region;
One drain electrode, this drain electrode is made on drain region; And
One gate electrode, this gate electrode is made on grizzly bar.
2. the single foreign atom based on SOI substrate according to claim 1 is without knot silicon nano line transistor, wherein source region, drain region and do not adopted N-type or P type to adulterate by the silicon nanowires that polycrystalline grid is wrapped up, and doping content is 10
18-10
19cm
-3magnitude.
3. the single foreign atom based on SOI substrate according to claim 1 is without knot silicon nano line transistor, and the part of the silicon nanowires wherein wrapped up by polycrystalline grid is only containing single foreign atom, and the type of foreign atom adopts N-type or the doping of P type.
4. the single foreign atom based on SOI substrate according to claim 1 is without knot silicon nano line transistor, and the material that wherein this dielectric thin layer adopts is SiO
2, nitrogen oxide, HfO
2, Si
3n
4, ZrO
2, Ta
2o
5, BST or PZT.
5. the single foreign atom based on SOI substrate according to claim 1 is without knot silicon nano line transistor, and wherein the doping content of polycrystalline grid is 10
21-10
23cm
-3magnitude, the type of foreign atom adopts P type or N-type doping.
6. based on SOI substrate single foreign atom without knot silicon nano line transistor a preparation method, comprise the steps:
Step 1: make the silicon nanowires of monatomic transistor, source region and drain region figure in the top layer silicon of SOI substrate, etching;
Step 2: generate SiO on the surface and sidewall in silicon nanowires, source region and drain region
2resilient coating;
Step 3: at the mid portion overlay electronic bundle resist of silicon nanowires;
Step 4: adulterated in the silicon nanowires of non-overlay electronic bundle resist, source region and drain region;
Step 5: removal covers the electron sensitive resist of silicon nanowires and generate SiO on silicon nanowires, source region and surface, drain region and sidewall
2resilient coating;
Step 6: adopt focused ion beam technology, realize the injection of single foreign atom at the mid portion of silicon nanowires;
Step 7: short annealing activates the foreign atom of doping;
Step 8: at the substrate surface growth dielectric thin layer of silicon nanowires, source region, drain region and exposure;
Step 9: cover polycrystalline silicon grid layer on dielectric thin layer, and ion implantation doping is carried out to polycrystalline silicon grid layer;
Step 10: etch polycrystalline grid on polycrystalline silicon grid layer; And
Step 11: make source electrode, drain electrode and gate electrode respectively in source region, drain region and polycrystalline grid, completes the preparation of device.
7. the single foreign atom based on SOI substrate according to claim 6 is without the preparation method tying silicon nano line transistor, wherein said SiO
2resilient coating adopts hydrofluoric acid solution rinsing, SiO
2the thickness of resilient coating is 10-30nm, and wherein said is more than 100nm at the thickness of silicon nanowires mid portion overlay electronic bundle resist.
8. the single foreign atom based on SOI substrate according to claim 6 is without the preparation method tying silicon nano line transistor, and adulterate in the wherein said silicon nanowires to non-overlay electronic bundle resist, source region and drain region, implantation dosage is 10
18-10
19cm
-3magnitude, the injection degree of depth is 20-70nm, and the part of the silicon nanowires wherein wrapped up by polycrystalline grid is only containing single foreign atom, and the type of foreign atom adopts N-type or the doping of P type.
9. the single foreign atom based on SOI substrate according to claim 6 is without the preparation method tying silicon nano line transistor, and the material of wherein said dielectric thin layer is SiO
2, nitrogen oxide, HfO
2, Si
3n
4, ZrO
2, Ta
2o
5, BST or PZT.
10. the single foreign atom based on SOI substrate according to claim 6 is without the preparation method tying silicon nano line transistor, and wherein the doping content of polycrystalline grid is 10
21-10
23cm
-3magnitude, the type of foreign atom adopts P type or N-type doping.
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|---|---|---|---|
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|---|---|---|---|
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110085673A (en) * | 2019-05-06 | 2019-08-02 | 中国科学院半导体研究所 | Foreign atom array transistor and preparation method thereof |
| CN110148622A (en) * | 2019-05-06 | 2019-08-20 | 中国科学院半导体研究所 | Foreign atom transistor and preparation method thereof based on silicon nanocrystal constraint |
| CN110491940A (en) * | 2019-08-20 | 2019-11-22 | 中国科学院半导体研究所 | A kind of nano-wire transistor and preparation method thereof based on resonance tunnel-through |
| CN112614865A (en) * | 2020-12-15 | 2021-04-06 | 中国科学院半导体研究所 | Non-junction silicon nanowire transistor based on phase change material storage gate and preparation method |
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| CN110085673A (en) * | 2019-05-06 | 2019-08-02 | 中国科学院半导体研究所 | Foreign atom array transistor and preparation method thereof |
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| CN112614865A (en) * | 2020-12-15 | 2021-04-06 | 中国科学院半导体研究所 | Non-junction silicon nanowire transistor based on phase change material storage gate and preparation method |
| CN112614865B (en) * | 2020-12-15 | 2022-07-05 | 中国科学院半导体研究所 | Non-junction silicon nanowire transistor based on phase change material storage gate and preparation method |
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