CN112614865B - Non-junction silicon nanowire transistor based on phase change material storage gate and preparation method - Google Patents

Non-junction silicon nanowire transistor based on phase change material storage gate and preparation method Download PDF

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CN112614865B
CN112614865B CN202011479891.5A CN202011479891A CN112614865B CN 112614865 B CN112614865 B CN 112614865B CN 202011479891 A CN202011479891 A CN 202011479891A CN 112614865 B CN112614865 B CN 112614865B
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dielectric layer
gate dielectric
phase
phase change
gate
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CN112614865A (en
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杨冲
韩伟华
陈俊东
张晓迪
郭仰岩
杨富华
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Institute of Semiconductors of CAS
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Abstract

The invention discloses a junction-free silicon nanowire transistor based on a phase-change material storage gate.A nanowire structure, a source region and a drain region are formed by etching top silicon of an SOI substrate, a phase-change gate dielectric layer covers the surface of the nanowire structure, and a second insulated gate dielectric layer is arranged on the upper side of the phase-change gate dielectric layer; a main gate electrode is arranged on the upper side of one end of the second insulated gate dielectric layer, the main gate electrode is connected with the phase change gate dielectric layer through a first contact hole, and the main gate electrode covers the upper side of the nanowire; and an auxiliary gate electrode is arranged on the upper side of the other end of the second insulated gate dielectric layer and is connected with the phase-change gate dielectric layer through a second contact hole. The phase-change material is prepared in the nanowire transistor as the gate medium, so that multi-value storage can be realized, and the phase-change material can be used as an electronic synapse device to be applied to neuromorphic calculation. The device takes a junction-free silicon nanowire transistor as a carrier, and has the advantages of compatibility with a COMS (complementary metal oxide semiconductor) process, high storage density and separation of read-write operation.

Description

Non-junction silicon nanowire transistor based on phase change material storage gate and preparation method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a junction-free silicon nanowire transistor based on a phase-change material storage gate and a preparation method thereof.
Background
The rapid development of information technology enables the data scale to grow exponentially, and the huge data volume puts higher requirements on the processing and storage capacity of the data. In a traditional computing architecture, a storage unit is separated from a computing unit, so that more power consumption and delay are generated in the data transmission process, and a von Neumann bottleneck appears. The neuromorphic computing is a brain-like computing system based on an artificial neural network, can realize a computing mode integrating storage and computation, and has the advantages of high energy efficiency and low power consumption. The electronic synapse device is used as a basis for constructing a neural network and becomes a key for realizing the calculation of the neural morphology.
The phase-change material has the excellent characteristics of 2-3 orders of magnitude difference in resistivity under different crystal phases, compatibility with a CMOS process and the like, and becomes an ideal material of an electronic synapse device. More complex image recognition and processing tasks can be completed already based on the neural morphology calculation of the phase change memory unit. However, each memory cell in the currently applied circuit is composed of a phase change memory and a MOSFET gating end, so that the area of the device is large, and the improvement of the memory density is not facilitated; the size of the read value of each memory cell depends on the resistivity change of the phase-change material, and the information storage window of each memory cell is limited to the conductance value of the phase-change memory; meanwhile, the read operation may affect the state of the phase change memory, causing an undesirable change in the stored information.
The junction-free silicon nanowire transistor has the advantages of simple preparation process, strong gate control capability, large on-off current ratio and the like, and the unique bulk transport mode improves the channel mobility so that the junction-free silicon nanowire transistor has a better load function. If the two are combined, the phase-change material is used for recording information, the junctionless silicon nanowire transistor is used for expressing the information, and the junctionless silicon nanowire transistor is used as an electronic synapse device to build an artificial neural network, so that the problems can be improved. However, no junction-free silicon nanowire transistor integrating the phase change material is reported.
In summary, electronic synapse devices with high memory density and read-write separation characteristics are yet to be developed.
Disclosure of Invention
In view of this, the main objective of the present invention is to provide a junction-free silicon nanowire transistor based on a phase change material storage gate and a manufacturing method thereof, so as to implement a multi-value memory device, which is prepared in the silicon nanowire transistor by using a phase change material as a gate dielectric, as a basic electronic synapse device of an artificial neural network.
In this context, embodiments of the present invention are intended to provide a junction-free silicon nanowire transistor based on a phase-change material storage gate and a preparation method thereof.
In a first aspect of the embodiments of the present invention, there are provided a junction-free silicon nanowire transistor based on a phase-change material storage gate and a preparation method thereof, including:
forming a nanowire structure, a source region and a drain region by etching top silicon of the SOI substrate, wherein the source region and the drain region are respectively provided with two ends of the nanowire structure, the surfaces of the nanowire structure, the source region and the drain region are covered with a first insulated gate dielectric layer, the upper side of the source region is provided with a source electrode, and the upper side of the drain region is provided with a drain electrode;
the surface of the nanowire structure is covered with a phase change gate dielectric layer, and the phase change gate dielectric layer is arranged on the upper side of the first insulating gate dielectric layer; the phase change gate dielectric layer is perpendicular to the axis direction of the nanowire structure, and two ends of the phase change gate dielectric layer cover the upper side of the SOI substrate;
a second insulated gate dielectric layer is arranged on the upper side of the phase change gate dielectric layer, a first contact hole and a second contact hole are respectively arranged at two ends of the second insulated gate dielectric layer, and the first contact hole and the second contact hole are respectively positioned at two sides of the nanowire structure;
a main gate electrode is arranged on the upper side of one end of the second insulated gate dielectric layer, the main gate electrode is connected with the phase change gate dielectric layer through the first contact hole, and the main gate electrode covers the upper side of the nanowire; and an auxiliary gate electrode is arranged on the upper side of the other end of the second insulated gate dielectric layer and is connected with the phase-change gate dielectric layer through the second contact hole.
In an embodiment of the present invention, the material of the phase-change gate dielectric layer is Ge2Sb2Te5SbTe, GeTe, SiSbTe or GeSb.
In another embodiment of the present invention, the doping types of the source region, the drain region and the nanowire structure are N-type or P-type.
In another embodiment of the present invention, the nanowire structure has a length of 100 to 2000nm, a cross-sectional length dimension of 10 to 100nm, and a cross-sectional width dimension of 10 to 100 nm.
In yet another embodiment of the present invention, the material of the first insulated gate dielectric layer and the second insulated gate dielectric layer includes one of the following: SiO 22Nitrogen oxide, TiO2、HfO2、Si3N4、ZrO2、Ta2O5Or barium strontium titanate BST.
In still another embodiment of the present invention, the source electrode and the drain electrode are aluminum or nickel; the main gate electrode and the sub-gate electrode are made of polysilicon, polycrystalline silicon germanium, titanium nitride, or titanium aluminum alloy.
In a second aspect of the embodiments of the present invention, there is provided a method for preparing a junction-free silicon nanowire transistor based on a phase-change material storage gate, including:
generating an oxide mask layer on the surface of the SOI substrate through thermal oxidation;
injecting N-type or P-type impurities into the surface of the oxide mask layer by an ion injection method, and then carrying out rapid thermal annealing treatment;
sequentially adopting electron beam exposure, silicon dioxide etching and silicon etching methods to manufacture a source region, a drain region and a nanowire structure on the surface of the SOI substrate;
generating a first insulating gate dielectric layer on the surfaces of the source region, the drain region and the silicon nanowire structure by a thermal oxidation or atomic layer deposition method;
covering a phase change material layer on the first insulated gate dielectric layer through magnetron sputtering;
processing the phase change material layer by electron beam exposure and dry etching in sequence to manufacture a phase change gate dielectric layer;
generating a second insulated gate dielectric layer on the phase-change gate dielectric layer by an atomic layer deposition method or a PECVD process;
forming a source electrode and a drain electrode on the source region and the drain region, respectively;
manufacturing a first contact hole and a second contact hole which are used for connecting the main gate electrode, the auxiliary gate electrode and the phase-change gate dielectric layer on the second insulated gate dielectric layer;
covering a gate electrode material layer on the second insulated gate dielectric layer by a chemical vapor deposition or metal sputtering method, wherein the material of the gate electrode material layer comprises one of the following materials: polycrystalline silicon, polycrystalline silicon germanium, titanium nitride or titanium aluminum alloy;
and manufacturing the main gate electrode and the auxiliary gate electrode on the gate electrode material layer sequentially by electron beam exposure and dry etching.
In an embodiment of the invention, the thickness of the oxide mask layer is 5 to 20 nm.
In another embodiment of the present invention, the doping concentration of the N-type or P-type ions is 1016～1019cm-3The implantation energy is 20keV to 50keV, the annealing temperature is 900 ℃ to 1100 ℃, and the annealing time is 10s to 60 s.
In another embodiment of the present invention, the thickness of the first insulated gate dielectric layer and the second insulated gate dielectric layer is 1 to 20 nm; the thickness of the phase change gate dielectric layer is 1-20 nm, and the axial width of the nanowire structure is 100-500 nm.
According to the non-junction silicon nanowire transistor based on the phase change material storage gate and the preparation method thereof, the phase change material is prepared in the nanowire transistor as a gate medium, the phase change of the phase change material is controlled through the main gate electrode and the auxiliary gate electrode, the conduction state of a channel is controlled by using the change of the dielectric constant in the phase change process, the multi-value storage is realized, and the non-junction silicon nanowire transistor can be used as an electronic synapse device to be applied to a neural network; meanwhile, the strain generated in the phase change process of the phase change material can effectively improve the carrier mobility of a transistor channel.
The junction-free silicon nanowire transistor based on the phase-change material storage gate provided by the invention takes the whole junction-free silicon nanowire transistor as a storage unit, the area of a device is small, and the storage density is effectively improved; meanwhile, the phase-change gate medium is used for storing information, the channel current of the transistor is used for expressing the information, and the phase-change gate medium has the advantages of high storage density, read-write separation and large information storage window. In addition, the preparation process of the junction-free silicon nanowire transistor based on the phase-change material storage gate is compatible with a CMOS (complementary metal oxide semiconductor) process, and the manufacturing and the application are convenient.
Drawings
FIG. 1 is a schematic structural diagram of a junction-free silicon nanowire transistor based on a phase-change material storage gate according to an embodiment of the present invention;
FIG. 2 is a cross-sectional view of a junction-free silicon nanowire transistor based on a phase-change material memory gate, taken along line AB in FIG. 1, according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of an SOI substrate provided by an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a source region, a drain region and a nanowire structure provided by an embodiment of the invention;
FIG. 5 is a schematic structural diagram of a phase-change gate dielectric layer according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a second insulated gate dielectric layer according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a source electrode and a drain electrode provided in an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of a first contact hole and a second contact hole provided in an embodiment of the present invention;
in the figure: 1. an SOI substrate; 2. a nanowire structure; 3. a source region; 4. a drain region; 5. a phase change gate dielectric layer; 6. a second insulated gate dielectric layer; 7. a source electrode; 8. a drain electrode; 9. a main gate electrode; 10. a sub-gate electrode; 11. a first contact hole; 12. and a second contact hole.
Fig. 9 is a flowchart of a method for manufacturing a junction-free silicon nanowire transistor based on a phase-change material storage gate according to an embodiment of the present invention.
Detailed Description
In order that the objects, technical solutions and advantages of the present invention will become more apparent, the present invention will be further described in detail with reference to the accompanying drawings in conjunction with the following specific embodiments.
As shown in fig. 1 and fig. 2, a junction-free silicon nanowire transistor based on a phase-change material storage gate according to an embodiment of the present invention includes: the structure comprises an SOI substrate 1, a nanowire structure 2, a source region 3, a drain region 4, a phase change gate dielectric layer 5, a second insulated gate dielectric layer 6, a source electrode 7, a drain electrode 8, a main gate electrode 9, an auxiliary gate electrode 10, a first contact hole 11 and a second contact hole 12.
In one embodiment of the present invention, the top silicon of the SOI substrate 1 is etched to form a nanowire structure 2, a source region 3 and a drain region 4, the source region 3 and the drain region 4 are respectively disposed at two ends of the nanowire structure 2, wherein the surfaces of the nanowire structure 2, the source region 3 and the drain region 4 are covered with a first insulated gate dielectric layer, the upper side of the source region 3 is provided with a source electrode 7, and the upper side of the drain region 4 is provided with a drain electrode 8;
the surface of the nanowire structure 2 is covered with a phase change gate dielectric layer 5, and the phase change gate dielectric layer 5 is arranged on the upper side of the first insulating gate dielectric layer; the phase change gate dielectric layer 5 is vertical to the axial direction of the nanowire structure 2, and two ends of the phase change gate dielectric layer 5 cover the upper side of the SOI substrate 1;
a second insulated gate dielectric layer 6 is arranged on the upper side of the phase change gate dielectric layer 5, a first contact hole 11 and a second contact hole 12 are respectively arranged at two ends of the second insulated gate dielectric layer 6, and the first contact hole 11 and the second contact hole 12 are respectively positioned at two sides of the nanowire structure 2;
a main gate electrode 9 is arranged on the upper side of one end of the second insulated gate dielectric layer 6, the main gate electrode 9 is connected with the phase change gate dielectric layer 5 through a first contact hole 11, and the main gate electrode 9 covers the upper side of the nanowire; an auxiliary gate electrode 10 is arranged on the upper side of the other end of the second insulated gate dielectric layer 6, and the auxiliary gate electrode 10 is connected with the phase change gate dielectric layer 5 through a second contact hole 12.
In this embodiment, the material of the phase-change gate dielectric layer 5 is Ge2Sb2Te5SbTe, GeTe, SiSbTe or GeSb, or other phase change materials satisfying the same function.
In the embodiment, the thicknesses of the first insulated gate dielectric layer and the second insulated gate dielectric layer 6 are 1-20 nm; the thickness of the phase change gate dielectric layer 5 is 1-20 nm, and the axial width of the nanowire structure 2 is 100-500 nm; the length of the nanowire structure 2 is 100-2000 nm, the length size of the cross section is 10-100 nm, and the width size of the cross section is 10-100 nm.
In the present embodiment, the doping types of the source region 3, the drain region 4 and the nanowire structure 2 are N-type or P-type.
According to the embodiment of the invention, a phase-change material is prepared in a nanowire transistor as a gate medium, the phase change of the phase-change material is controlled through a main gate electrode 9 and an auxiliary gate electrode 10, the conduction state of a channel is controlled by using the change of a dielectric constant in the phase change process, the multi-value storage is realized, and the phase-change material is used as an electronic synapse device to be applied to a neural network; meanwhile, the strain generated in the phase change process of the phase change material can effectively improve the carrier mobility of a transistor channel.
Having introduced the junction-less silicon nanowire transistor according to an exemplary embodiment of the present invention, a method for fabricating the junction-less silicon nanowire transistor based on the phase change material memory gate according to an exemplary embodiment of the present invention will be described with reference to fig. 3 to 9.
In another embodiment of the present invention, as shown in fig. 9, a method for manufacturing a junction-free silicon nanowire transistor based on a phase change material memory gate according to an embodiment of the present invention includes operations S101 to S108.
In operation S101, as shown in fig. 3, an oxide mask layer is generated on the surface of the SOI substrate 1 through thermal oxidation, an N-type or P-type impurity is implanted into the surface of the oxide mask layer through an ion implantation method, and then a rapid thermal annealing process is performed, specifically, the thickness of the oxide mask layer in this embodiment is 5 to 20 nm; the doping concentration of N-type or P-type impurity is 1016～1019cm-3The implantation energy is 20keV to 50keV, the annealing temperature is 900 ℃ to 1100 ℃, and the annealing time is 10s to 60 s.
In operation S102, as shown in fig. 4, a source region 3, a drain region 4 and a nanowire structure 2 are formed on a surface of the SOI substrate 1 by sequentially performing electron beam exposure, silicon dioxide etching and silicon etching.
In operation S103, source and drain regions 3 and 3 are formed4, generating a first insulating gate dielectric layer on the surface of the silicon nanowire structure 2 by a thermal oxidation or atomic layer deposition method, specifically, the first insulating gate dielectric layer material of this embodiment is SiO2Nitrogen oxide, TiO2、HfO2、Si3N4、ZrO2、Ta2O5Or barium strontium titanate BST, or other materials that perform the same function.
In operation S104, as shown in fig. 5, a phase-change material layer is covered on the first insulated gate dielectric layer by magnetron sputtering, and the phase-change material layer is processed by electron beam exposure and dry etching in sequence to manufacture the phase-change gate dielectric layer 5, specifically, the phase-change gate dielectric layer 5 of this embodiment is made of Ge2Sb2Te5SbTe, GeTe, SiSbTe or GeSb, or other phase change materials satisfying the same function.
In operation S105, as shown in fig. 6, a second insulated gate dielectric layer 6 is formed on the phase-change gate dielectric layer 5 by an atomic layer deposition method or a PECVD process, specifically, the second insulated gate dielectric layer 6 of the embodiment is made of SiO2Nitrogen oxide, TiO2、HfO2、Si3N4、ZrO2、Ta2O5Or barium strontium titanate BST, or other materials that perform the same function.
In operation S106, as shown in fig. 7, a source electrode 7 and a drain electrode 8 are respectively formed on the source region 3 and the drain region 4, specifically, the source electrode 7 and the drain electrode 8 of the present embodiment are aluminum or nickel, or may be other metals or alloys satisfying the same function.
In operation S107, as shown in fig. 8, a first contact hole 11 and a second contact hole 12 connecting the main gate electrode 9, the sub-gate electrode 10 and the phase-change gate dielectric layer 5 are formed on the second insulating gate dielectric layer 6.
In operation S108, a gate electrode material layer is covered on the second insulated gate dielectric layer 6 by a chemical vapor deposition or metal sputtering method, and the main gate electrode 9 and the sub-gate electrode 10 are manufactured on the gate electrode material layer sequentially by an electron beam exposure method and a dry etching method, specifically, the main gate electrode 9 and the sub-gate electrode 10 in this embodiment are polysilicon, polysilicon germanium, titanium nitride, or titanium-aluminum alloy, and may be other materials satisfying the same function.
According to the embodiment of the invention, the whole junction-free silicon nanowire transistor is used as a storage unit, so that the area is small, and the storage density is effectively improved; in addition, the preparation process of the junction-free silicon nanowire transistor based on the phase-change material storage gate is compatible with a CMOS (complementary metal oxide semiconductor) process, and the manufacturing and the application are convenient.
The above-mentioned embodiments, objects, technical solutions and advantages of the present invention are further described in detail, it should be understood that the above-mentioned embodiments are only examples of the present invention, and should not be construed as limiting the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (10)

1. A junction-free silicon nanowire transistor based on a phase change material memory gate, comprising:
an SOI substrate;
the top silicon of the SOI substrate is etched to form a nanowire structure, a source region and a drain region, the source region and the drain region are respectively arranged at two ends of the nanowire structure, wherein the surfaces of the nanowire structure, the source region and the drain region are covered with a first insulating gate dielectric layer, a source electrode is arranged on the upper side of the source region, and a drain electrode is arranged on the upper side of the drain region;
the surface of the nanowire structure is covered with a phase change gate dielectric layer, and the phase change gate dielectric layer is arranged on the upper side of the first insulating gate dielectric layer; the phase change gate dielectric layer is perpendicular to the axis direction of the nanowire structure, and two ends of the phase change gate dielectric layer cover the upper side of the SOI substrate;
a second insulated gate dielectric layer is arranged on the upper side of the phase change gate dielectric layer, a first contact hole and a second contact hole are respectively arranged at two ends of the second insulated gate dielectric layer, and the first contact hole and the second contact hole are respectively positioned at two sides of the nanowire structure;
a main gate electrode is arranged on the upper side of one end of the second insulated gate dielectric layer, the main gate electrode is connected with the phase change gate dielectric layer through the first contact hole, and the main gate electrode covers the upper side of the nanowire; and an auxiliary gate electrode is arranged on the upper side of the other end of the second insulated gate dielectric layer and is connected with the phase-change gate dielectric layer through the second contact hole.
2. The junction-free silicon nanowire transistor based on the phase-change material storage gate of claim 1, wherein the phase-change gate dielectric layer is made of Ge2Sb2Te5SbTe, GeTe, SiSbTe or GeSb.
3. The junction-free silicon nanowire transistor based on the phase-change material storage gate of claim 1, wherein the doping types of the source region, the drain region and the nanowire structure are N-type or P-type.
4. The junction-free silicon nanowire transistor based on the phase-change material storage gate of claim 1, wherein the nanowire structure has a length of 100-2000 nm, a cross-sectional length dimension of 10-100 nm, and a cross-sectional width dimension of 10-100 nm.
5. The junction-free silicon nanowire transistor based on a phase change material memory gate of claim 1, wherein the material of the first and second insulated gate dielectric layers comprises one of: SiO 22Nitrogen oxide, TiO2、HfO2、Si3N4、ZrO2、Ta2O5Or barium strontium titanate BST.
6. The junction-free silicon nanowire transistor based on a phase-change material memory gate of claim 1, wherein the source electrode and the drain electrode are aluminum or nickel; the main gate electrode and the auxiliary gate electrode are made of polycrystalline silicon, polycrystalline silicon germanium, titanium nitride or titanium-aluminum alloy.
7. A preparation method of a junction-free silicon nanowire transistor based on a phase-change material storage gate is characterized by comprising the following steps:
generating an oxide mask layer on the surface of the SOI substrate through thermal oxidation;
injecting N-type or P-type impurities into the surface of the oxide mask layer by an ion injection method, and then carrying out rapid thermal annealing treatment;
sequentially adopting methods of electron beam exposure, silicon dioxide etching and silicon etching to manufacture a source region, a drain region and a nanowire structure on the surface of the SOI substrate;
generating a first insulating gate dielectric layer on the surfaces of the source region, the drain region and the silicon nanowire structure by a thermal oxidation or atomic layer deposition method;
covering a phase change material layer on the first insulating gate dielectric layer through magnetron sputtering;
processing the phase change material layer by electron beam exposure and dry etching in sequence to manufacture a phase change gate dielectric layer;
generating a second insulated gate dielectric layer on the phase-change gate dielectric layer by an atomic layer deposition method or a PECVD process;
respectively manufacturing a source electrode and a drain electrode on the source region and the drain region;
manufacturing a first contact hole and a second contact hole which are used for connecting the main gate electrode, the auxiliary gate electrode and the phase-change gate dielectric layer on the second insulated gate dielectric layer;
covering a gate electrode material layer on the second insulated gate dielectric layer by a chemical vapor deposition or metal sputtering method, wherein the material of the gate electrode material layer comprises one of the following materials: polycrystalline silicon, polycrystalline silicon germanium, titanium nitride or titanium aluminum alloy;
and manufacturing the main gate electrode and the auxiliary gate electrode on the gate electrode material layer sequentially by electron beam exposure and dry etching.
8. The method of claim 7, wherein the oxide mask layer has a thickness of 5 to 20 nm.
9. The method according to claim 7, wherein the doping concentration of the N-type or P-type impurity is 1016～1019cm-3The implantation energy is 20keV to 50keV, the annealing temperature is 900 ℃ to 1100 ℃, and the annealing time is 10s to 60 s.
10. The preparation method of claim 7, wherein the thickness of the first insulated gate dielectric layer and the second insulated gate dielectric layer is 1-20 nm; the thickness of the phase change gate dielectric layer is 1-20 nm, and the axial width of the nanowire structure is 100-500 nm.
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JP2016040843A (en) * 2015-11-06 2016-03-24 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． Semiconductor device and semiconductor device manufacturing method
CN110491940A (en) * 2019-08-20 2019-11-22 中国科学院半导体研究所 A kind of nano-wire transistor and preparation method thereof based on resonance tunnel-through
CN110660846A (en) * 2019-09-30 2020-01-07 合肥鑫晟光电科技有限公司 Thin film transistor, manufacturing method and light-emitting device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104867834A (en) * 2015-04-22 2015-08-26 中国科学院半导体研究所 Single-impurity atom junction-free silicon nano wire transistor based on SOI substrate, and preparation method thereof
JP2016040843A (en) * 2015-11-06 2016-03-24 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． Semiconductor device and semiconductor device manufacturing method
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