CN116314287B - Self-aligned two-dimensional semiconductor lightly doped drain preparation method and two-dimensional semiconductor transistor - Google Patents
Self-aligned two-dimensional semiconductor lightly doped drain preparation method and two-dimensional semiconductor transistor Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
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- Ceramic Engineering (AREA)
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- General Physics & Mathematics (AREA)
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- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The invention provides a preparation method of a Light Doped Drain (LDD) of a two-dimensional semiconductor transistor and the two-dimensional semiconductor transistor, wherein the preparation method comprises the following steps: providing a substrate; forming a semiconductor material layer; forming a gate structure; performing a first surface modification treatment; forming a first solid active source metal layer and a first conventional metal layer; carrying out primary annealing treatment to obtain a first two-dimensional semi-metal material layer; forming a side wall of the gate structure; performing a second surface modification treatment; forming a second solid active source metal layer and a second conventional metal layer; and carrying out secondary annealing treatment to obtain a second two-dimensional semi-metal material layer with metal atom concentration larger than that of the first two-dimensional semi-metal material layer, and photoetching to form a source-drain contact region in a self-alignment mode, wherein the source-drain contact region comprises a second solid active source metal layer, a second conventional metal layer, the second two-dimensional semi-metal material layer and the first two-dimensional semi-metal material layer. The method can realize the self-alignment process of the two-dimensional semiconductor lightly doped drain structure and is compatible with the semiconductor processing process.
Description
Technical Field
The invention particularly relates to a preparation method of a self-aligned two-dimensional semiconductor transistor lightly doped drain and a two-dimensional semiconductor transistor, and belongs to the technical field of two-dimensional semiconductors.
Background
The silicon-based technology is about to reach the physical limit of moore's law, the scaling speed of the integrated circuit transistor is continuously reduced, the benefit is limited by the process cost and the yield is gradually narrowed, in addition, the power consumption of the unit area of the silicon-based integrated circuit is rapidly increased due to the unit integration level improvement and the current density improvement, the problem of ' power consumption wall ' accompanied by the scattering problem is more serious, and the problems are more and more acute in advanced nodes of sub 10 nm. Due to the ultra-thin atomic level characteristic of the two-dimensional semiconductor material, the moore's law can be extended, the problem of ' power consumption wall ' can be hopefully broken, the performance is further improved, and the power consumption is reduced. Since stacked transistors in the form of 3D (three-dimensional) integrated chips can alleviate memory bandwidth problems or "memory walls," it is believed that the future of half-moore's law will be driven by 3D integrated chips, which may also drastically change the design and routing methods. Where two-dimensional semiconductors may be a key solution to create such 3D integrated chips because they can be grown easily at low temperatures while leaving the electrical properties intact, but high resistance contacts have been an obstacle to the adoption of two-dimensional semiconductors.
For low-dimensional semiconductor material transistors, particularly two-dimensional semiconductors, the hot electron effect of a channel is strongly dependent on the maximum electric field intensity in the channel, and the too strong electric field near a drain end can cause excessive tunneling current and obvious short channel effect. In a short channel ballistic transport two-dimensional transistor, the hot electron effect must be suppressed in order to ensure reliable operation of the device, and it is desirable to reduce the maximum electric field at the drain terminal to reduce the tunneling current.
The use of a lightly doped drain (l ight ly Doped Drain, LDD) structure allows the peak electric field location to be transferred from the channel drain to the drain lightly doped junction, thereby reducing the maximum electric field strength and drain tunneling current. However, because the silicon-based ion implantation method is not suitable for two-dimensional ultrathin materials, no technology compatible with semiconductor processing technology exists in the aspect of controllable light doping and heavy doping of two-dimensional semiconductor materials.
In order to reduce the area of the functional region and improve the integration and performance, a self-aligned process needs to be developed to realize the LDD structure. The current self-alignment mode of the low-dimensional material is only shown in a metal stripping process, which is not compatible with large-scale process
Therefore, the self-aligned process for reducing the contact resistance and realizing the two-dimensional semiconductor lightly doped drain structure is a technical problem to be solved.
Disclosure of Invention
The invention aims to reduce the contact resistance of the source and drain regions of the two-dimensional semiconductor transistor, reduce the maximum electric field of the drain end, reduce the tunneling current, realize the self-alignment process of the two-dimensional semiconductor lightly doped drain structure and be compatible with the semiconductor processing process.
In order to achieve the above purpose, the present invention adopts the following technical scheme.
A method for fabricating a Lightly Doped Drain (LDD) of a two-dimensional semiconductor transistor, comprising the steps of: providing a substrate; forming a semiconductor material layer on the substrate; forming a gate structure on the semiconductor material layer; performing first surface modification treatment on the surface of the two-dimensional semiconductor material layer which is not covered by the grid structure; forming a first solid active source metal layer and a first conventional metal layer; carrying out primary annealing treatment to obtain a first two-dimensional semi-metal material layer; removing the first solid active source metal layer and the first conventional metal layer, and forming a side wall of the gate structure on the first two-dimensional semi-metal material layer; carrying out second surface modification treatment on the surface of the first two-dimensional semi-metal material layer which is not covered by the grid structure and the side wall; forming a second solid active source metal layer and a second conventional metal layer; carrying out secondary annealing treatment to obtain a second two-dimensional semi-metal material layer, wherein the concentration of metal atoms in the second two-dimensional semi-metal material layer is greater than that of the first two-dimensional semi-metal material layer; and photoetching the second solid active source metal layer and the second conventional metal layer, and forming a source-drain contact region in a self-aligned manner, wherein the source-drain contact region comprises the second solid active source metal layer, the second conventional metal layer, the second two-dimensional semi-metal material layer and the first two-dimensional semi-metal covered by the grid structure and the side wall.
Wherein the first surface modification treatment and the second surface modification treatment comprise bombarding a surface of the two-dimensional semiconductor material layer away from the substrate with ultra-low power soft plasma.
Wherein the second surface modification treatment has a treatment strength greater than that of the first surface modification treatment.
Wherein the first annealing treatment and the second annealing treatment adopt a rapid annealing mode of annealing for 2-60s from 250 ℃ to 600 ℃.
Wherein the temperature and time of the first annealing treatment are greater than the temperature and time of the second annealing treatment.
Wherein the two-dimensional semiconductor material layer comprises any one of indium selenide (I nSe), molybdenum disulfide (MoS 2), indium diselenide (MoSe 2), tungsten disulfide (WS 2), tungsten diselenide (WSe 2), molybdenum telluride (MoTe 2), black Phosphorus (BP), silylene (Si l iene), germanene (GERMANENE), telluroene (Te l l urene), an ionic layered semiconductor material (Bi 2O2X, x=s or Se), or a combination thereof.
Wherein the solid active source metal layer comprises any one of yttrium (Y), scandium (Sc), vanadium (V), iron (Fe), molybdenum (Mo), tantalum (Ta), rhenium (Re), or a combination thereof.
The present invention also provides a two-dimensional semiconductor transistor including: a substrate; a two-dimensional semiconductor material layer disposed on the substrate; a gate structure disposed on the two-dimensional semiconductor material layer; a first two-dimensional semi-metallic material layer disposed on the two-dimensional semiconductor material layer; the side wall is arranged on the first two-dimensional semi-metal material layer and coats the side wall of the gate structure; a second two-dimensional semi-metal material layer disposed on the two-dimensional semiconductor material layer, the concentration of metal atoms in the second two-dimensional semi-metal material layer being greater than the concentration of metal atoms in the first two-dimensional semi-metal material layer; a solid source active metal layer arranged on the surface of the second two-dimensional semi-metal material layer far away from the two-dimensional semiconductor material layer; and a conventional metal layer arranged on the surface of the solid source active metal layer far away from the second two-dimensional semi-metal material layer.
The first two-dimensional semi-metal material layer is a semi-metal material layer obtained by inducing phase change of the two-dimensional semi-metal material layer by metal atoms.
And the metal atoms in the second two-dimensional semi-metal material layer and the solid source active metal layer further induce the phase change of the first two-dimensional semi-metal material layer to obtain a semi-metal material layer with higher metal atom concentration.
The invention has the following advantages and technical effects:
The self-aligned two-dimensional semiconductor lightly doped drain preparation method provided by the invention has the advantages that the two-dimensional semiconductor material of the contact area is induced to be changed into the two-dimensional semi-metal material or the two-dimensional metal material, the induced two-dimensional semi-metal material or the induced two-dimensional metal material is directly contacted with the two-dimensional semiconductor material, the contact resistance of the source and drain regions of the two-dimensional semiconductor transistor is reduced, the maximum electric field of the drain end can be reduced, the tunneling current is reduced, the self-aligned process of the two-dimensional semiconductor lightly doped drain structure is realized, and the self-aligned semiconductor lightly doped drain preparation method is compatible with the semiconductor processing process.
Drawings
In order to more clearly illustrate the technical solution of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it will be apparent that the drawings in the following description are only some embodiments of the present invention, and that several modifications and variations can be made by those skilled in the art without departing from the technical principles of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Fig. 1 to 15 are schematic structural diagrams of two-dimensional semiconductor transistors prepared by the self-aligned patterning method according to the present invention.
Fig. 16 is a schematic structural diagram of a two-dimensional semiconductor transistor provided according to the present invention.
Detailed Description
For the purposes of clarity, content, and advantages of the present invention, a detailed description of the embodiments of the present invention will be described in detail below with reference to the drawings and examples. The following examples are only for more clearly illustrating the technical aspects of the present invention, and are not intended to limit the scope of the present invention.
Example 1
The embodiment specifically describes a method for preparing a Lightly Doped Drain (LDD) of a two-dimensional semiconductor transistor, which comprises the following steps: providing a substrate; forming a semiconductor material layer on the substrate; forming a gate structure on the semiconductor material layer; performing first surface modification treatment on the surface of the two-dimensional semiconductor material layer which is not covered by the grid structure; forming a first solid active source metal layer and a first conventional metal layer; carrying out primary annealing treatment to obtain a first two-dimensional semi-metal material layer; removing the first solid active source metal layer and the first conventional metal layer, and forming a side wall of the gate structure on the first two-dimensional semi-metal material layer; carrying out second surface modification treatment on the surface of the first two-dimensional semi-metal material layer which is not covered by the grid structure and the side wall; forming a second solid active source metal layer and a second conventional metal layer; carrying out secondary annealing treatment to obtain a second two-dimensional semi-metal material layer, wherein the concentration of metal atoms in the second two-dimensional semi-metal material layer is greater than that of the first two-dimensional semi-metal material layer; and photoetching the second solid active source metal layer and the second conventional metal layer, and forming a source-drain contact region in a self-aligned manner, wherein the source-drain contact region comprises the second solid active source metal layer, the second conventional metal layer, the second two-dimensional semi-metal material layer and the first two-dimensional semi-metal covered by the grid structure and the side wall. .
A two-dimensional semiconductor-based solid-state source doping method is described in detail below in conjunction with fig. 1-11, the method comprising the steps of:
s1, providing a substrate 100, wherein the substrate material comprises insulating materials such as silicon, silicon oxide, sapphire, mica and the like;
S2, preparing a two-dimensional semiconductor material layer 101 on the substrate 101, wherein the obtained structure is shown in fig. 1, and the two-dimensional semiconductor material layer comprises any one of indium selenide (I nSe), molybdenum disulfide (MoS 2), indium diselenide (MoSe 2), tungsten disulfide (WS 2), tungsten diselenide (WSe 2), molybdenum telluride (MoTe 2), black Phosphorus (BP), silylene (Si l iene), germanene (GERMANENE), tellerene (Te l l urene), an ionic layered semiconductor material (Bi 2O2X, x=s or Se), or a combination thereof, but the present invention is not limited thereto;
s3, forming a gate structure on the semiconductor material layer, including forming a gate dielectric layer 102 on the semiconductor material layer 101 and forming a gate layer 103 on the gate dielectric layer, wherein the obtained structure is shown in FIG. 2, and the gate layer 103 can be a polysilicon or amorphous silicon dummy gate or a metal gate, and the gate structure is compatible with a first gate process (including gate dielectric and metal gate) and a dummy gate structure of a later gate process (including gate dielectric and polysilicon dummy gate and amorphous silicon dummy gate);
S4, as shown in FIG. 3, bombarding the surface of the two-dimensional semiconductor material layer by adopting soft plasma, and carrying out surface modification treatment on the surface of the two-dimensional semiconductor material layer 101 which is not covered by the grid structure, wherein the specific method is that ultra-low power soft plasma (such as nitrogen, argon, hydrogen and the like) with the weight of 1-100w is used for bombarding the two-dimensional semiconductor material layer for 5-300 seconds, so that lattice defects, distortion and the like are generated on the surface of the two-dimensional semiconductor material layer 101 which is not covered, and active metal atoms are easier to be injected in the follow-up process, and the first surface modification treatment is carried out on the semiconductor material layer;
S5, forming a first solid active source metal layer 104 and a first conventional metal layer 105, wherein the first solid active source metal layer 104 and the first conventional metal layer 105 can be formed by adopting an evaporation or sputtering method, the thickness of the first solid active source metal layer is 0.5-5nm, the metal in the first solid active source metal layer is a metal which is easy to react with a two-dimensional semiconductor material, the metal can comprise any one or combination of yttrium (Y), scandium (Sc), vanadium (V), iron (Fe), molybdenum (Mo), tantalum (Ta), rhenium (Re) and the like, the thickness of the first conventional metal layer is more than 5nm, the metal in the conventional metal layer is usually an inert metal such as gold (Au), titanium (Ti), aluminum (Al), nickel (Ni), palladium (Pd), silver (Ag), titanium nitride (TiNx) or the combination thereof, and the metal in the first solid active source metal layer can be passivated to prevent the active metal layer from being oxidized;
S6, carrying out annealing treatment, wherein the obtained structure is shown in FIG. 5, metal atoms in the first solid active source metal layer 104 are injected into the two-dimensional semiconductor material layer 101, substitutional doping occurs, the substitutional doped two-dimensional semiconductor material layer is converted into the first two-dimensional semiconductor material layer 106 by induced phase change, the annealing treatment can adopt a rapid annealing mode of annealing for 2-60S from 250 ℃ to 600 ℃, or a conventional annealing mode of annealing for 15 min-4 h from 150 ℃ to 250 ℃ under high vacuum, the annealing time and temperature determine the atom concentration of substitutional doping, the annealing time and the annealing temperature are long, the doping concentration is high, the semiconductor material layer is converted into the two-dimensional metal material layer, the doping concentration is low, and the annealing treatment is the first annealing treatment;
S7, removing the first solid active source metal layer 104 and the first conventional metal layer 105, wherein the obtained structure is shown in FIG. 6;
s8, depositing a dielectric layer 107 by adopting a PECVD (plasma enhanced chemical vapor deposition) method to cover the first two-dimensional semi-metal material layer 106 and the grid structure, wherein the obtained structure is shown in FIG. 7, and the material of the dielectric layer 104 can be insulating materials such as silicon nitride; then, etching back the dielectric layer 107 to form a pseudo-gate sidewall 108 surrounding the sidewall of the gate structure, and the resulting structure is shown in fig. 8;
S9, as shown in FIG. 9, bombarding the surface of the two-dimensional semiconductor material layer by soft plasma, and carrying out surface modification treatment on the surface of the first two-dimensional semi-metal material layer 106 which is not covered by the side wall 108, wherein the specific method is that ultra-low power soft plasma (such as nitrogen, argon, hydrogen and the like) with the weight of 1-100w is used for bombarding the first two-dimensional semi-metal material layer 106 for 5-300 seconds, so that lattice defects, distortion and the like are generated on the surface of the first two-dimensional semi-metal material layer 106 which is not covered, active metal atoms are easier to inject in the follow-up process, the surface modification treatment is carried out for the second time, and the power and the time of the second surface modification treatment are both greater than those of the first surface modification treatment, so that more metal atoms are subjected to substitution doping in the follow-up process;
S10, forming a second solid active source metal layer 109 and a second conventional metal layer 110, wherein the second solid active source metal layer 109 and the second conventional metal layer 110 can be formed by adopting an evaporation or sputtering method, the thickness of the second solid active source metal layer is 0.5-5nm, the metal in the first solid active source metal layer is a metal which is easy to react with a two-dimensional semiconductor material, the metal can comprise any one of yttrium (Y), scandium (Sc), vanadium (V), iron (Fe), molybdenum (Mo), tantalum (Ta), rhenium (Re) and the like, the thickness of the second conventional metal layer is more than 5nm, the metal in the conventional metal layer is often an inert metal such as gold (Au), titanium (Ti), aluminum (Al), nickel (Ni), palladium (Pd), silver (Ag), titanium nitride (TiNx) or a combination thereof, the metal in the first solid active source metal layer is easy to react with the two-dimensional semiconductor material, the metal can be passivated to prevent the active metal layer from oxidizing, and the metal in the second solid active source metal layer 109 can be the same as the first active source metal layer 104 or the second conventional metal layer 110 or different from the first conventional metal layer 110 or the solid active source metal layer or the second active layer can have the same composition as the first conventional metal layer 110;
S11, performing annealing treatment, wherein the obtained structure is shown in FIG. 11, metal atoms in the second solid active source metal layer 109 are injected into the first two-dimensional semi-metal material layer 106, substitutional doping further occurs, the first two-dimensional semi-metal material layer 106 is further subjected to induced phase transition to be converted into the second two-dimensional semi-metal material layer 109, the second two-dimensional semi-metal material layer 106 is covered by the side wall 108 and is reserved, the annealing treatment can be performed in a rapid annealing mode of annealing for 2-60S from 250 ℃ to 600 ℃, or in a conventional annealing mode of annealing for 15 min-4 h from 150 ℃ to 250 ℃ under high vacuum, the annealing treatment is performed for the second annealing treatment, the temperature and the time of the second annealing treatment are both greater than those of the first annealing treatment, so that more metal atoms are doped into the second two-dimensional semi-metal material layer 109, that is, the concentration of the metal atoms in the second two-dimensional semi-metal material layer 109 is greater than that in the first two-dimensional semi-metal material layer 106, that is, the second two-dimensional semi-metal material layer 109 is doped with heavy metal material layer 150 is light-doped by the side wall 106, and the light two-dimensional semi-metal layer 106 is reserved in a two-dimensional structure of the light-doped semiconductor structure;
S12, preparing an SOD dielectric layer 112 by a sampling spin coating method, or growing the dielectric layer 112 by PECVD, wherein the obtained structure is shown in FIG. 12, and the material of the dielectric layer can be silicon nitride or silicon oxide and the like;
s13, using the second conventional metal layer 110 on the conventional gate structure as a stop layer, and adopting CMP (chemical mechanical polishing) to planarize the dielectric layer 112, wherein the obtained structure is shown in FIG. 13;
S14, etching back the dielectric layer 109 until the dielectric layer is thinned above the second conventional metal layer 110 of the contact area, reserving a dielectric layer 112 with the thickness of 10-20 nanometers above the contact area, and exposing the conventional metal layers on the outer wall and the top of the gate outside the contact area, wherein the obtained structure is shown in FIG. 14;
S15, photoetching and defining the size of a transistor, so as to form a source-drain contact area in a self-alignment manner, photoetching and defining the size of the transistor, adopting photoresist as a mask, windowing to define the total pattern size of a source-drain area and a gate, and etching away the rest dielectric layers, thereby forming the source-drain contact area in a self-alignment manner, wherein the obtained structure is shown in figure 15;
s16, the dielectric layer 109 is used as a self-mask, and the contact metal layer in other areas is selectively etched, so that a two-dimensional semiconductor transistor is obtained, and the structure diagram of the two-dimensional semiconductor transistor is shown in FIG. 16.
According to the preparation method of the self-aligned two-dimensional semiconductor lightly doped drain, provided by the embodiment, the two-dimensional semiconductor material of the contact area is subjected to induced phase change to be a two-dimensional semiconductor material, the induced two-dimensional semiconductor material layer is directly contacted with the two-dimensional semiconductor material, the Fermi pinning effect generated by direct evaporation of conventional metal is avoided, ohmic contact can be formed, the problem of high-resistance contacts is solved with lower cost, meanwhile, a lightly doped drain structure covered by a grid side wall and a heavily doped two-dimensional semiconductor material layer not covered by the side wall are formed by adopting a secondary surface treatment and a secondary annealing treatment process, the maximum electric field of the drain end can be reduced, tunneling current is reduced, the self-alignment process of the two-dimensional semiconductor lightly doped drain structure is realized, and the self-aligned two-dimensional semiconductor lightly doped drain structure is compatible with a semiconductor processing process.
The present embodiment also provides a two-dimensional semiconductor transistor, as shown in fig. 16, including: a substrate 100; a two-dimensional semiconductor material layer 101 disposed on the substrate; a gate structure disposed on the two-dimensional semiconductor material layer 101, the gate structure including a gate dielectric layer 102 and a gate layer 103 disposed on the gate dielectric layer; a first two-dimensional semi-metallic material layer 106 disposed on the two-dimensional semi-metallic material layer; the side wall 108 is arranged on the first two-dimensional semi-metal material layer 106, the side wall covers the side wall of the gate structure, and the side wall covers the first two-dimensional semi-metal material layer 106; a second two-dimensional semi-metallic material layer 111 disposed on the two-dimensional semiconductor material layer, the concentration of metal atoms in the second two-dimensional semi-metallic material layer being greater than the concentration of metal atoms in the first two-dimensional semi-metallic material layer; a second solid source active metal layer 106 disposed on a surface of the second two-dimensional semi-metallic material layer 111 remote from the two-dimensional semiconductor material layer 101; a second conventional metal layer 110 is disposed on a surface of the second solid state source active metal layer 109 remote from the second two-dimensional semi-metallic material layer 111.
The first two-dimensional semi-metal material layer is obtained by inducing phase change of the two-dimensional semi-metal material layer by metal atoms in the first solid source active metal layer (removed in the preparation process). The second two-dimensional semi-metal material layer is a semi-metal material layer obtained by further inducing phase change of the first two-dimensional semi-metal material layer by metal atoms in the second solid source active metal layer, and the concentration of doped metal atoms in the second two-dimensional semi-metal material layer is higher.
As described above, the two-dimensional semi-metal material layer of the contact region is a semi-metal material layer obtained by inducing the phase change of the two-dimensional semi-metal material layer by metal atoms in the solid source active metal layer, the Fermi pinning effect generated by the direct evaporation of conventional metals is avoided, ohmic contact can be formed, the contact resistance is reduced to be lower than 200Ω·μm, and the Schottky barrier height is close to 0meV of the physical limit.
In addition, the first two-dimensional semi-metal material layer 106 covered by the grid side wall 108 is lightly doped to form a lightly doped drain structure of the two-dimensional transistor, the contact area further comprises a second two-dimensional semi-metal material layer which is not covered by the side wall, the second two-dimensional semi-metal material layer is heavily doped, and the thus formed two-dimensional semiconductor transistor lightly doped drain structure can reduce the maximum electric field of the drain end, reduce tunneling current, realize a self-alignment process of the two-dimensional semiconductor lightly doped drain structure, and is compatible with semiconductor processing processes
The above-described embodiments are provided for illustrating the technical concept and features of the present invention, and are intended to be preferred embodiments for those skilled in the art to understand the present invention and implement the same according to the present invention, not to limit the scope of the present invention. All equivalent changes or modifications made according to the spirit of the present invention should be included in the scope of the present invention.
Claims (9)
1. A method for fabricating a self-aligned two-dimensional semiconductor transistor Lightly Doped Drain (LDD), comprising the steps of:
Providing a substrate;
forming a semiconductor material layer on the substrate;
forming a gate structure on the semiconductor material layer;
performing first surface modification treatment on the surface of the two-dimensional semiconductor material layer which is not covered by the grid structure, wherein the first surface modification treatment is first bombardment by adopting ultra-low power soft plasma of 1-100 w;
Forming a first solid active source metal layer and a first conventional metal layer;
carrying out primary annealing treatment to obtain a first two-dimensional semi-metal material layer;
Removing the first solid active source metal layer and the first conventional metal layer, and forming a side wall of the gate structure on the first two-dimensional semi-metal material layer;
performing second surface modification treatment on the surface of the first two-dimensional semi-metal material layer, which is not covered by the gate structure and the side wall, wherein the second surface modification treatment is that ultra-low power soft plasma with the weight of 1-100w is adopted for performing second bombardment;
Forming a second solid active source metal layer and a second conventional metal layer;
Carrying out secondary annealing treatment to obtain a second two-dimensional semi-metal material layer, wherein the concentration of doped metal atoms in the second two-dimensional semi-metal material layer is greater than that in the first two-dimensional semi-metal material layer;
And photoetching the second solid active source metal layer and the second conventional metal layer, and forming a source-drain contact region in a self-aligned manner, wherein the source-drain contact region comprises the second solid active source metal layer, the second conventional metal layer, the second two-dimensional semi-metal material layer and the first two-dimensional semi-metal material layer covered by the gate structure and the side wall.
2. The method of claim 1, wherein the second bombardment is performed at a higher power and for a longer time than the first bombardment.
3. The method of manufacturing a self-aligned two-dimensional semiconductor transistor Lightly Doped Drain (LDD) according to claim 1, wherein the first annealing process and the second annealing process use a rapid annealing process of annealing at 250 ℃ to 600 ℃ for 2-60 seconds.
4. The method of claim 1, wherein the first annealing process is performed at a temperature and time greater than the second annealing process.
5. The method of claim 1, wherein the two-dimensional semiconductor material layer comprises any one of indium selenide (InSe), molybdenum disulfide (MoS 2), molybdenum diselenide (MoSe 2), tungsten disulfide (WS 2), tungsten diselenide (WSe 2), molybdenum telluride (MoTe 2), black Phosphorus (BP), silylene (Siliene), germanene (GERMANENE), tellurone (Tellurene), an ionic layered semiconductor material, or a combination thereof.
6. The method of claim 1, wherein the solid state active source metal layer comprises any one of yttrium (Y), scandium (Sc), vanadium (V), iron (Fe), molybdenum (Mo), tantalum (Ta), rhenium (Re), or a combination thereof.
7. A two-dimensional semiconductor transistor, comprising:
A substrate;
a two-dimensional semiconductor material layer disposed on the substrate;
A gate structure disposed on the two-dimensional semiconductor material layer;
A first two-dimensional semi-metallic material layer disposed on the two-dimensional semiconductor material layer;
The side wall is arranged on the first two-dimensional semi-metal material layer and coats the side wall of the gate structure;
A second two-dimensional semi-metal material layer disposed on the two-dimensional semiconductor material layer, the concentration of metal atoms in the second two-dimensional semi-metal material layer being greater than the concentration of metal atoms in the first two-dimensional semi-metal material layer;
A solid source active metal layer arranged on the surface of the second two-dimensional semi-metal material layer far away from the two-dimensional semiconductor material layer;
and a conventional metal layer arranged on the surface of the solid source active metal layer far away from the second two-dimensional semi-metal material layer.
8. The two-dimensional semiconductor transistor according to claim 7, wherein the first two-dimensional semi-metal material layer is a semi-metal material layer obtained by inducing phase change of the two-dimensional semiconductor material layer by metal atoms.
9. The two-dimensional semiconductor transistor according to claim 8, wherein the second two-dimensional semi-metal material layer is a semi-metal material layer with higher concentration of metal atoms obtained by further inducing phase transition of the first two-dimensional semi-metal material layer by metal atoms in the solid source active metal layer.
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