JP2015035478A - Field effect transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a field effect transistor capable of achieving both high channel mobility and a high ON/OFF ratio, and a method of driving the same.SOLUTION: The field effect transistor includes: a channel layer comprising a Dirac electron system material; a source electrode and a drain electrode connected to the channel layer; a first gate insulating film formed on a first surface of the channel layer; a first gate electrode formed on the first gate insulating film; a second gate insulating film formed on a second surface of the channel layer; and a second gate electrode formed on the second gate insulating film. In the first gate insulating film, capacitance between the channel layer and the first gate electrode gradually increases from the source electrode side toward the drain electrode side.

Description

  The present invention relates to a field effect transistor using a Dirac electronic material.

  In addition to the energy required to manipulate and store information, current computer power consumption is increased by Joule heat dissipated in devices and wiring. This energy dissipation occurs in the process in which the electron flow is scattered by lattice defects and phonons. Therefore, in order to meet the recent demand for power saving, it is important how to suppress electron scattering in the device.

  In recent years, as one solution for suppressing electron scattering, it has been proposed to use the conduction characteristics of a crystal system called a Dirac electron system. Electron scattering is suppressed in this new material because the effective carrier equation is the same as the Dirac equation with zero mass, and the topological quantum mechanical phase around the singular point of the band structure is exactly π (non- Patent Document 1). This means that the backscattering of electrons is greatly suppressed by quantum mechanical interference, the mobility of the device channel is increased, and the power consumption is reduced.

  Of particular interest in the Dirac electron system are graphene produced in 2004 and topological insulators theoretically proposed in 2007 (Non-Patent Document 2).

JP 2009-059902 A JP 2010-109177 A

A. H. Castro Neto et al., Rev. Mod. Phys. 81, 109-162 (2009) M. Z. Hasan et al., Rev. Mod. Phys. 82, 3045-3067 (2010) F. Shcwierz, Nature Nanotechnology 5, 487-496 (2010) M. S. Lundstrom et al., “Nanoscaletransistors: Device Physics, Modeling and Simulation”, Springer 2006 J. Xia et al., “Measurement of the quantum capacitance of graphene”, Nature Nanotechnology 4, 505-509 (2009) M. Kim et al., PNAS January 17, 2012 vol. 109 No. 3, 671-674 J. Tominagaet al. Nature Nanotechnology, 6, 501 (2011). S. Datta, “Quantum Transport-Atom to Transistor”, Cambridge University Press

  As described above, it is theoretically expected that electron scattering can be suppressed by utilizing the quantum effect of the Dirac electron system. It has also been confirmed from both first-principles calculations and experiments that graphene and topological insulators have a band structure as a Dirac electron system.

  However, the quantum effect of the Dirac electron system has not been fully utilized in the device formation. First, the existence of topological insulators was predicted relatively recently in 2007, and the basic research is still emphasized. Graphene precedes topological insulators in device research, but has not yet reached the stage where electron scattering can be suppressed using the quantum effect in the fabricated devices. On the contrary, it has not been possible to simultaneously achieve the minimum three functions required for use as a transistor, switching (high on / off ratio), drain current saturation, and quick response.

  In addition, graphene transistors currently have the dilemma that channel mobility is sacrificed when the on / off ratio is increased, and that the drain current does not saturate in transistor channels where channel mobility is maximized. And did not meet the requirements for practical application.

  An object of the present invention is to provide a field effect transistor that can achieve both high channel mobility and high on / off ratio.

  According to one aspect of the embodiment, a channel layer made of a Dirac electronic material, a source electrode and a drain electrode connected to the channel layer, and a first of the channel layer between the source electrode and the drain electrode. A first gate insulating film formed on the surface of the first gate electrode, a first gate electrode formed on the first insulating film, and a second layer of the channel layer between the source electrode and the drain electrode. A second gate insulating film formed on the surface and a second gate electrode formed on the second insulating film, wherein the first gate insulating film includes the channel layer and the channel layer. A field effect transistor is provided in which a capacitance between the first gate electrode and the first gate electrode gradually increases from the source electrode side toward the drain electrode side.

  According to another aspect of the embodiment, a channel layer made of a Dirac electronic material, a source electrode and a drain electrode connected to the channel layer, and the channel layer between the source electrode and the drain electrode A first gate insulating film formed on the first surface, a plurality of first gate electrodes formed on the first insulating film, and between the source electrode and the drain electrode. A field effect transistor having a second gate insulating film formed on the second surface of the channel layer and a second gate electrode formed on the second insulating film is provided.

  According to the disclosed field effect transistor, it is possible to realize a high-speed and low power consumption field-effect transistor that achieves both high channel mobility and a high on / off ratio.

FIG. 1 is a schematic cross-sectional view showing the structure of the field effect transistor according to the first embodiment. FIG. 2 is an off-state energy band diagram for a traditional MOSFET. FIG. 3 is an energy band diagram of an off state in the field effect transistor according to the first embodiment. FIG. 4 is a graph showing the relationship between the Z ₂ invariant and the external electric field in the Sb ₂ Te ₃ thin film. FIG. 5 is a schematic diagram showing the structure of Sb ₂ Te ₃ . FIG. 6 is a diagram showing the structure of the phase change material layer of the field effect transistor according to the first embodiment. FIG. 7 is an energy band diagram (part 1) for explaining the operation of the field effect transistor according to the first embodiment. FIG. 8 is an energy band diagram (part 2) for explaining the operation of the field effect transistor according to the first embodiment. FIG. 9 is a process cross-sectional view (part 1) illustrating the method for manufacturing the field effect transistor according to the first embodiment. FIG. 10 is a process cross-sectional view (part 2) illustrating the method for manufacturing the field effect transistor according to the first embodiment. FIG. 11 is a process cross-sectional view (part 3) illustrating the method for manufacturing the field effect transistor according to the first embodiment. FIG. 12 is a process cross-sectional view (part 4) illustrating the method for manufacturing the field effect transistor according to the first embodiment. FIG. 13 is a process cross-sectional view (part 5) illustrating the method for manufacturing the field effect transistor according to the first embodiment. FIG. 14 is a process cross-sectional view (No. 6) illustrating the method for manufacturing the field effect transistor according to the first embodiment. FIG. 15 is a process cross-sectional view (No. 7) illustrating the method for manufacturing the field effect transistor according to the first embodiment. FIG. 16 is a process cross-sectional view (No. 8) illustrating the method for manufacturing the field effect transistor according to the first embodiment. FIG. 17 is a process cross-sectional view (No. 9) illustrating the method for manufacturing the field effect transistor according to the first embodiment. FIG. 18 is a process cross-sectional view (No. 10) illustrating the method for manufacturing the field effect transistor according to the first embodiment. FIG. 19 is a process cross-sectional view (No. 11) illustrating the method for manufacturing the field effect transistor according to the first embodiment. FIG. 20 is a process cross-sectional view (No. 12) illustrating the method for manufacturing the field effect transistor according to the first embodiment. FIG. 21 is a schematic cross-sectional view showing the structure of the field effect transistor according to the second embodiment. FIG. 22 is a process cross-sectional view (part 1) illustrating the method for manufacturing the field effect transistor according to the second embodiment. FIG. 23 is a process cross-sectional view (part 2) illustrating the method for manufacturing the field effect transistor according to the second embodiment. FIG. 24 is a process cross-sectional view (part 3) illustrating the method for manufacturing the field effect transistor according to the second embodiment. FIG. 25 is a process cross-sectional view (part 4) illustrating the method for manufacturing the field effect transistor according to the second embodiment. FIG. 26 is a process cross-sectional view (part 5) illustrating the method for manufacturing the field effect transistor according to the second embodiment. FIG. 27 is a process cross-sectional view (No. 6) illustrating the method for manufacturing the field effect transistor according to the second embodiment. FIG. 28 is a process cross-sectional view (part 7) illustrating the method for manufacturing the field effect transistor according to the second embodiment. FIG. 29 is a schematic sectional view showing the structure of the field effect transistor according to the third embodiment. FIG. 30 is an energy band diagram (part 1) for explaining the operation of the field effect transistor according to the third embodiment. FIG. 31 is an energy band diagram (part 2) for explaining the operation of the field effect transistor according to the third embodiment. FIG. 32 is a process cross-sectional view (part 1) illustrating the method for manufacturing the field effect transistor according to the third embodiment. FIG. 33 is a process cross-sectional view (part 2) illustrating the method for manufacturing the field effect transistor according to the third embodiment. FIG. 34 is a process cross-sectional view (part 3) illustrating the method for manufacturing the field effect transistor according to the third embodiment. FIG. 35 is a process cross-sectional view (part 4) illustrating the method for manufacturing the field effect transistor according to the third embodiment.

[First Embodiment]
The field effect transistor and the manufacturing method thereof according to the first embodiment will be described with reference to FIGS.

FIG. 1 is a schematic cross-sectional view showing the structure of the field effect transistor according to the present embodiment. FIG. 2 is an off-state energy band diagram for a traditional MOSFET. FIG. 3 is an energy band diagram of an off state in the field effect transistor according to the present embodiment. FIG. 4 is a graph showing the relationship between the Z ₂ invariant and the external electric field in the Sb ₂ Te ₃ thin film. FIG. 5 is a schematic diagram showing the structure of Sb ₂ Te ₃ . FIG. 6 is a view showing the structure of the phase change material layer of the field effect transistor according to the present embodiment. 7 and 8 are energy band diagrams for explaining the operation of the field effect transistor according to the present embodiment. 9 to 20 are process cross-sectional views illustrating the method of manufacturing the field effect transistor according to the present embodiment.

[Cross-sectional structure and operation outline of field effect transistor]
First, the structure of the field effect transistor according to the present embodiment will be explained with reference to FIGS.

  An impurity layer 24 is formed on the silicon substrate 10. On the silicon substrate 10 on which the impurity layer 24 is formed, an element isolation insulating film 22 that defines the active regions 22A and 22B is formed. The active region 22A is a transistor formation region, and the active region 22B is a contact region to the impurity layer 24.

  On the active region 22A of the silicon substrate 10, a first gate insulating film 28, a phase change material layer 36, and a second gate insulating film 46 are stacked. The phase change material layer 36 is formed of a Dirac electronic material in which topological phase transition occurs. The film thickness of the first gate insulating film 28 gradually increases from the source region side (left side in the figure) to the drain region side (right side in the figure). On the other hand, the film thickness of the second gate insulating film 46 gradually decreases from the source region side (left side in the figure) to the drain region side (right side in the figure). A gate electrode 52 is formed on the second gate insulating film 46.

  Thereby, the silicon substrate 10 includes an impurity layer 24 functioning as a back gate electrode, a first gate insulating film 28, a phase change material layer 36 functioning as a channel layer, a second gate insulating film 46, and a top gate electrode. A field effect transistor having the gate electrode 52 is formed.

  An interlayer insulating film 54 is formed on the silicon substrate 10 on which the field effect transistor is formed. On the interlayer insulating film 54, wiring 68A connected to the gate electrode 52, wirings 68B (source electrode) and 68C (drain electrode) connected to the phase change material layer 36, and wiring 68D connected to the impurity layer 24 are provided. Is formed.

  As described above, the field effect transistor according to the present embodiment uses the phase change material layer 36 in which the topological phase transition occurs as a channel layer, and the current flowing between the source electrode (wiring 68B) and the drain electrode (wiring 68C) It is controlled by an electric field applied between the gate electrode (impurity layer 24) and the top gate electrode (gate electrode 52).

  In the field effect transistor according to the present embodiment, the first potential increases from the source region side toward the drain side so that a gradient is formed along the channel length direction in the electrostatic potential of the channel layer (phase change material layer 36). The thickness of the gate insulating film 28 is increased, and the thickness of the second gate insulating film is decreased. By doing so, it is possible to give a gradient to the electrostatic potential in the channel layer along the channel length direction.

  In the development of devices of the Dirac electronic system so far, an approach using a conventional transistor operation model (hereinafter referred to as “traditional MOSFET model”) that has been optimized for a non-Dirac electronic system has been taken.

  However, in the first place, the Dirac electronic system and the non-Dirac electronic system are completely different from the effective equation of carriers. In fact, in graphene, the effective carrier equation is a first-order differential equation of the same shape as the mass-free Dirac equation, similar to the surface state of the topological insulator, whereas in a normal semiconductor that is a non-Dirac electron system, The effective equation is a second-order differential equation that is identical to the Schroedinger equation. If the form of this second-order differential equation is forcibly applied to the band structure of a Dirac electron system with zero mass, the effective mass becomes infinite. The conventional approach of applying a model for a non-Dirac electronic system to a Dirac electronic system not only deteriorates the performance of the graphene transistor, but also theoretically fails.

  In addition, in a graphene transistor based on the traditional MOSFET model (hereinafter referred to as “classical graphene transistor”), channel mobility decreases when attempting to suppress the leakage current, and on the other hand, if channel mobility is decreased. There is a dilemma that leakage current increases. This dilemma results in a mobility-bandgap tradeoff relationship in classical graphene transistors. This is called a trade-off because high mobility can only be obtained at the cost of a small bandgap, while a large bandgap can only be obtained at the cost of a low mobility. This trade-off arises from the nature of nature and cannot be improved beyond the theoretical limit.

  That is, in the graphene transistor manufactured according to the traditional MOSFET model, the off-state leakage current is determined by the size of the band gap. The inability to change the mobility-bandgap trade-off means that it is impossible to achieve both an increase in mobility and a reduction in leakage current.

  In other words, the mobility-leakage current dilemma increases only the mobility and bandgap with an unchangeable trade-off relationship without changing the classical design that can be changed to apply the quantum effect. It arises from the mistake of trying. Actually, no matter how much the mobility is increased or the band gap is increased without changing the classic design, only the next problem 1 and problem 2 are moved back and forth (Non-patent Document 3). See).

  (Problem 1) If the band gap is kept small, the mobility can be increased. However, the off-state leakage current increases.

  (Problem 2) If the band gap is widened, the off-state leakage current can be suppressed. However, the mobility is degraded.

  A transistor is required not only for switching (high on / off ratio, that is, suppression of leakage current) but also quick response (high channel mobility) as a necessary condition. Nevertheless, with classical graphene transistors, only one can be achieved, even if best implemented.

  The classical graphene transistor design is based on the traditional MOS structure designed to work well in the "MOS limit" (channel capacitance >> gate capacitance). And there is a contradiction that the Dirac electronic system behaves close to the opposite "bipolar limit" (channel capacitance << gate capacitance) (for MOS limit and bipolar limit) (Refer nonpatent literature 4). Actually, experiments so far show that in a graphene transistor, the capacitance of the channel <the capacitance of the gate, or the two capacitances have the same order (see Non-Patent Document 5). .

FIG. 2 is an off-state energy band diagram for a traditional MOSFET. FIG. 3 is an energy band diagram of an off state in the field effect transistor according to the present embodiment. In the figure, E _V is the energy of the valence band edge, the E _C represents the energy of the conduction band, E _F is the Fermi energy, E _g is the energy band gap, U the electrostatic potential.

  In the field effect transistor according to the present embodiment in which the channel layer is formed of a Dirac electronic material, the back gate electrode (impurity layer 24) and the top are taken into consideration that the channel capacitance is not so large as to conform to the design principle of the classical graphene transistor By applying a voltage to the gate electrode (gate electrode 52), the energy band of the channel portion is inclined as shown in FIG.

  In addition, the long mean free path of conduction electrons of Dirac electrons is several hundred nanometers, which is not a classical conduction model as assumed in a traditional MOSFET but a quantum conduction model. Thus, using the Landauer equation to estimate the current passing through the channel, the leakage current causes the electrons to be thermally excited from the Fermi level to the top of the electrostatic potential barrier (the bottom of the conduction band in the channel). It can be seen that it is proportional to the probability (Boltzmann factor).

As a result, the energy width of the thermal excitation that causes the leakage current is an energy width corresponding to the band gap at most in the traditional MOSFET, whereas the field effect transistor according to the present embodiment has several times the energy width. It becomes width. That is, the transport gap is doubled. In comparison with the off-state leakage current, the leakage current in the traditional MOSFET is proportional to exp (−β (E _g − (E _F −E _C ))), whereas in the field effect transistor according to the present embodiment, exp (− β (αE _g − (E _F −E _C ))). That is, according to the field effect transistor according to the present embodiment, the off-state leakage current can be greatly reduced as compared with the case of the traditional MOSFET.

[Use of topological phase change when electric field is applied]
Further, in the field effect transistor according to the present embodiment, paying attention to the topological phase that is the source of the conduction characteristics of the Dirac electron system, the channel layer is formed of a phase change material that causes a topological phase transition. The topological phase is a phase change of the wave function when the external parameter of the Hamiltonian changes, and is also called a belly phase. The Z ₂ invariant calculated from this phase characterizes two topological quantum phases, a topological insulator and a normal insulator, and takes different values for each quantum phase.

  In topological insulators, the special band structure of the zero-mass Dirac electron system results from the relativistic effect of the inner core electrons. This is because the heavy elements contained in the topological insulator are moving at such a high speed (˜10% of the speed of light) that the relativistic effect of the inner core electrons cannot be ignored. Of these relativistic effects, the largest correction to the non-relativistic Schroedinger equation is the interaction between the orbital momentum of electrons and spin. Therefore, in the topological insulator, the energy level that would have been degenerated if there was no spin-orbit interaction was split, and the band structure changed. As a result, there is a special band structure in which the band corresponding to the inside of the material has a gap like an insulator, but the two bands corresponding to the surface level intersect like a conductor (non-conducting). (See Patent Documents 2, 6, and 7).

  The name topological insulator is derived from topology and topology. This is because the index characterizing the band structure does not change with the continuous deformation of the electronic Hamiltonian, just as the invariant in topology does not change with the continuous deformation of the figure.

  At present, it has been confirmed that topological insulators are not only theoretically possible, but actually exist. However, even if a single crystal produced by a method of cooling molten metal or the like is a topological insulator, it cannot be immediately applied to an electronic device because its conduction state is limited to the interface with vacuum.

  The inventors of the present application have found a superlattice structure in which not only the interface with the vacuum but also the boundaries of all the alloy layers can be in a topological conduction state, and have proposed a device using the superlattice structure (Patent Document 1). And Patent Document 2). By using such a superlattice structure, it is possible to realize a topological conduction state in the device and to realize low power consumption.

  The inventors of the present application have newly found that the dilemma of the graphene transistor performance can be eliminated by using the transition of the topological quantum phase by the external electric field.

  Usually, the transition of the topological quantum phase is known as a change from a normal insulator to a topological insulator depending on the alloy composition, as experimentally shown for bismuth-tellurium and antimony-tellurium alloys. It has been. However, recent theoretical calculations suggest that changes in the external electric field can also cause a quantum phase transition in a solid having a superlattice structure (Non-Patent Document 6).

FIG. 4 is a graph showing changes in the Z ₂ invariant when an external electric field is applied to the Sb ₂ Te ₃ thin film (cited from Non-Patent Document 6). In the figure, when the Z ₂ invariant is 0, it represents a normal insulator, and when the Z ₂ invariant is 1, it represents a topological insulator. In the figure, the ● mark plot is 3QLs, and the ▪ mark plot is 4QLs. As shown in FIG. 3, QL is a unit structure layer of Sb ₂ Te ₃ formed of five atomic layers (in the figure, expressed as “ONE QUINTUPLE LAYER”), and “3QLs” Three layers are stacked, and “4QLs” is a stack of four unit structure layers. As shown in FIG. 5, the external electric field is applied in the direction perpendicular to the unit structure layer.

As shown in FIG. 4, in Sb ₂ Te _{3 of} 3QLs, it changes from a normal insulator to a topological insulator by application of an external electric field. On the other hand, in Sb ₂ Te _{3 of} 4QLs, it changes from a topological insulator to a normal insulator by application of an external electric field. In Sb ₂ Te ₃ , when the number of unit structure layers is three or less, the application of an external electric field changes from a normal insulator to a topological insulator, and when the number of unit structure layers is four or more, an external electric field is applied. Is confirmed to change from a topological insulator to a normal insulator.

  The inventors of the present application have confirmed that the above-described superlattice structure is a topological insulator by both the band structure from the first-principles calculation and the change in reflectance of circularly polarized light (Non-Patent Document 7). The superlattice structure that has been verified was formed as a laminated structure in which a crystalline alloy layer composed of germanium and tellurium and a crystalline alloy layer composed of antimony and tellurium are aligned with the <111> plane axis and the c-axis of each. Is. According to the first-principles calculation, it was found that the superlattice structure becomes a topological insulator when the antimony-tellurium alloy layer is one block or more, and becomes a normal insulator when it is thicker than 6 blocks. Then, the inventors of the present application formed the superlattice type phase change film having a different thickness of the antimony-tellurium alloy layer on the silicon wafer, applied an external magnetic field in a direction perpendicular to the surface, and time-reversal symmetry. The spin electron density was changed by breaking and the circularly polarized light was incident on this state, and the change in reflectance was measured. Then, the change of the spin current that should exist at the edge of the sample was confirmed, and it was concluded that the superlattice structure of the present inventors becomes a topological insulator. We also found that when the space reversal symmetry is broken by an electric field, it undergoes a phase transition to a normal insulator with a large Rashba effect.

  Therefore, a transistor that operates in a topological conduction state can be realized by using, for the channel layer, the phase-change material layer 36 including such a material layer in which a topological quantum phase transition occurs by application of an external electric field.

[Driving Method of Field Effect Transistor]
Next, the operation of the field effect transistor according to the present embodiment will be described with reference to FIGS.

Here, the phase change material layer 36 is assumed to change from a normal insulator to a topological insulator by application of an external electric field. For example, in the phase change material layer 36 having a superlattice structure in which a GeTe layer and an Sb ₂ Te ₃ layer are stacked, an Sb ₂ Te ₃ layer of 6QL or more is used.

  First, preconditions for driving the transistor will be described.

The source is grounded, and its potential V _S is set equal to the Fermi level E _F (V _S = −E _F / e = 0). Further, the back gate electrode by applying a positive voltage, the electrostatic governed sufficiently higher than the bottom of the conduction band and the Fermi level E _F of the source region by (field effect doping), i.e. such that the degenerate extreme (E _F -E _C >> k _B T).

  When discussing quantum conduction, the part of the channel region that is in contact with the source electrode and not affected by the top gate electrode is commonly called the left lead, and is the part that is in contact with the drain electrode and is not affected by the top gate electrode. Is called the right lead. In this specification, the left lead and the right lead are referred to as a source region and a drain region, respectively.

  Next, voltage application conditions for turning off the transistor will be described.

When the transistor is turned off, a negative voltage V _TG smaller than the threshold voltage V _TG ^{C at} which the phase change material layer 36 causes a topological phase transition is applied to the gate electrode 52 that is the top gate electrode (| V _TG | <V _TG ^C ). Further, a positive voltage V _BG smaller than the threshold voltage V _BG ^{C at} which the phase change material layer 36 causes topological phase transition is applied to the impurity layer 24 as the back gate electrode (0 <V _BG <V _BG ^C ). . The source electrode 68B is grounded, and a positive voltage is applied to the drain electrode 68C so that a predetermined source-drain voltage is applied.

When such a voltage is applied to each terminal of the transistor, an energy band structure in a region from the source region to the drain region through the channel region is as illustrated in FIG. In Figure 7, E _F is the Fermi level, E _C is the band edge of the conduction band, E _V is the band edge of the valence band, U is represents the electrostatic potential.

A source region of the phase change material layer 36 is electrostatically dominated intensified by the back gate electrode because it is close to the back gate electrode (impurity layer 24), pulled than the electrostatic potential U is the Fermi level E _F It is done.

On the other hand, the channel region of the phase change material layer 36 is affected by the voltage V _TG of the top gate electrode (gate electrode 52) in addition to weakening of the electrostatic control by the back gate electrode. U is higher than the Fermi level E _F. This tendency increases as the drain region is approached depending on the film thickness gradient of the first gate insulating film 28 and the second gate insulating film 46. As a result, the electrostatic potential U in the channel region becomes the highest at the end of the drain region, and the energy band bends accordingly.

In order for electrons to escape from the source region side to the drain region side in this state, before the transmission takes place, the electrons move to an energy level higher than the energy E _{C at} the bottom of the raised conduction band of the channel region. It must be pre-heated. This is because electrons having lower energy cannot receive energy from phonons (or by other inelastic scattering) in the channel region, and therefore cannot escape to the drain region side due to the band gap. is there. Incidentally, the phonon scattering does not occur in the channel region because the transistor is manufactured so that the channel length is shorter than the inelastic scattering length.

  As a result, no drain current flows and the transistor is turned off.

  Next, voltage application conditions for turning on the transistor will be described.

When the transistor is turned on, a positive voltage V _TG greater than the threshold voltage V _TG ^{C at} which the phase change material layer 36 causes a topological phase transition is applied to the gate electrode 52 that is the top gate electrode. Further, a positive voltage V _BG smaller than a threshold voltage V _TG ^{C at} which the phase change material layer 36 causes a topological phase transition is applied to the impurity layer 42 serving as the back gate electrode, as in the off state. The source electrode 68B is grounded, and a positive voltage is applied to the drain electrode 68C so that a predetermined source-drain voltage is applied.

When such a voltage is applied to each terminal of the transistor, an energy band structure in a region from the source region to the drain region through the channel region is as illustrated in FIG. In Figure 8, E _F is the Fermi level, E _C is the band edge of the conduction band, E _V is the band edge of the valence band, U is represents the electrostatic potential.

As in the OFF state, the source region of the phase change material layer 36 is close to the back gate electrode (impurity layer 24), so that electrostatic control by the back gate electrode is strengthened, and the electrostatic potential U is Fermi than the level _{E F} is pulled down. Thereby, a sufficient carrier density can be obtained.

Further, a voltage larger than the threshold voltage V _TG ^C causing the topological phase transition is applied to the channel region of the phase change material layer 36, and the phase change material layer 36 undergoes a phase transition from a normal insulator to a topological insulator, The band gap of the channel region is closed.

In addition, since the electrostatic potential U at the center of the channel is pushed down by the electrostatic control of the top gate electrode, the energy barrier separating the source region and the drain region disappears. Since the energy E _{C at} the bottom of the conduction band also bends in accordance with the electrostatic potential U, Fermi level electrons can be transmitted ballistically (or while maintaining quantum coherence) from the source region to the drain region. A current flows and the transistor is turned on.

As you just increase the drain voltage V _DS, the Fermi level E _F of the drain region, pushed down below the Fermi level E _F of the source region. As a result, electrons in the conduction band on the source region side can escape to the open energy level on the drain region side.

A source region of the transistor due to the degeneracy extreme, the drain current is proportional to the difference in the Fermi level E _F the Fermi level E _F and the drain region of the source region. That is, the drain current increases in proportion to the drain voltage ratio. However, the Fermi level E _F of the drain region is smaller than the energy E _C at the bottom of the conduction band of the source region, eventually, the drain current is greater, increasing not (Non-Patent Document 8). That is, the drain current is saturated.

  As described above, the field effect transistor according to the present embodiment can saturate the drain current while maximizing the carrier mobility in the channel region without being blocked by the dilemma of the conventional graphene transistor.

[Specific structure of transistor channel causing topological phase change]
The material that can be applied to the phase change material layer 36 of the field effect transistor according to the present embodiment and causes the transition of the topological quantum phase by an external electric field is not particularly limited, but, for example, Ge (germanium), Te ( Examples thereof include a material layer mainly composed of tellurium) or Bi (bismuth). Alternatively, the phase change material layer 20 may have Ge, Sb and Te as main components, Ge, Bi and Te as main components, Al, Sb and Te as main components, Al, Bi and Te may be the main components. The “main component” means the component that is contained most.

  As a combination of elements constituting the main component of the phase change material layer 36, a combination of Ge, Sb, and Te, a combination of Ge, Bi, and Te, a combination of Al, Sb, and Te, Al, Bi, The combination with Te etc. is mentioned, Among these, the combination of Ge, Sb, and Te is preferable.

Examples of the constituent components of the phase change material layer 36 include GeTe, Sb ₂ Te _{3 and the} like when the phase change material layer 36 is mainly composed of Ge, Sb, and Te. Further, when the phase change material layer 36 is mainly composed of Ge, Bi, and Te, GeTe, Bi ₂ Te ₃ , Bi, and the like can be given. Further, when the phase change material layer 36 is mainly composed of Al, Sb and Te, AlTe, Sb ₂ Te _{3 and the} like can be mentioned. Further, when the phase change material layer 36 is mainly composed of Al, Bi, and Te, AlTe, Bi ₂ Te ₃ , Bi, and the like can be given.

In the phase change material layer 36 mainly composed of Ge, Sb, and Te, it is desirable that the GeTe layer and the Sb ₂ Te ₃ layer are laminated adjacently. Thereby, a superlattice structure composed of the GeTe layer and the Sb ₂ Te ₃ layer can be formed.

The superlattice structure composed of the GeTe layer and the Sb ₂ Te ₃ layer has a feature that a band having two different spin-like bodies at the band center called Γ point is degenerated at one point. This state is firmly protected by a physical conservation law called time reversal symmetry, and is not destroyed by the incorporation of nonmagnetic impurities. For this reason, scattering is remarkably suppressed, and theoretically, the mobility may be infinite due to the linear dispersion relation. Unlike graphene, the Dirac cone is composed of two bands having different spin states, and therefore a band gap can be formed at the Dirac point by applying an external electric field. That is, the band gap can be opened and closed by the electric field.

A superlattice structure composed of a GeTe layer and an Sb ₂ Te ₃ layer having such a Dirac cone and capable of reversibly opening and closing a band gap by an external electric field is particularly [[GeTe) _x (Sb ₂ Te ₃ ) _Y ] The repeating structure consisting of _z is mentioned. Here, x, y, and z are integers. In particular, this characteristic is exhibited when x ≧ 2, y ≧ 1, z ≧ 2, and x = 2, y = 4, and z = 8 are optimal. And z are not limited to this. If x exceeds 4, the gap remains open even when an electric field is applied. The thickness of each unit layer is 0.5 nm for GeTe and about 1 nm for Sb ₂ Te ₃ .

The opening and closing of the band gap depends on the positional relationship between the Ge atoms and the Te atom layer of the GeTe thin film layer. Bulk GeTe has long been well known as a ferroelectric, and it is also well known that it is composed of a thin film laminated structure having a σ bond between Ge-Te. There are several methods for stacking atomic layers, and three types of Ge—Te—Te—Ge type, Ge—Te—Ge—Te type, and Te—Ge—Ge—Te type are typical, but Sb ₂ Te ₃ and the film forming temperature for forming the superlattice layer Te-Ge-Ge-Te type and Te-Ge-Te-Ge type is the most stable. The Te-Ge-Ge-Te type (see FIG. 6A) has spatial symmetry in the upper and lower sides and does not show ferroelectricity, but the Te-Ge-Te-Ge type (see FIG. 6B) is It is a ferroelectric material with polarization. Therefore, GeTe sandwiched vertically _Sb 2 Te ₃ layer layer, a band gap in the Te-GeTe-Ge type spatial symmetry is lacking by topological bands and band hybrid from _Sb 2 Te ₃ layer The Te-Ge-Ge-Te type that maintains the spatial symmetry has a feature that the band gap closes with a Dirac cone. Both superlattice structures are stable in terms of energy, and the ferroelectric type can be transformed into a non-ferromagnetic type by applying an external electric field.

That is, if a dielectric thin film is formed on the upper and lower surfaces of a repetitive structure composed of [(GeTe) _x (Sb ₂ Te ₃ ) _y ] _z and a gate electrode is formed thereon, the band gap can be opened and closed. If the source electrode is arranged so that the source current flows through the interface of the superlattice structure, carriers having linear dispersion and high mobility can flow to the drain electrode.

Note that the material forming the channel layer is not necessarily a phase change material that causes a topological phase transition as long as it is a material exhibiting a Dirac electron conduction mechanism. For example, other Dirac electronic materials such as double-layer graphene that opens a band gap by applying an electric field, an armchair graphene nanoribbon having a band gap, and MoS ₂ can be used. What is necessary is just to set suitably the voltage applied to each terminal of a transistor according to a channel layer material so that the conduction mechanism of a Dirac electron system may be exhibited when the transistor is in an on state.

[Method for Manufacturing Field Effect Transistor]
Next, the method for fabricating the field effect transistor according to the present embodiment will be explained with reference to FIGS.

  First, the silicon substrate 10 whose plane orientation is the (100) plane is heated at, for example, a temperature of 950 ° C. in, for example, an oxygen / hydrogen mixed gas stream to form a silicon oxide film having a thickness of, for example, 300 nm on the surface of the silicon substrate 10. Layer 12 is formed.

  Next, a silicon nitride layer 14 having a thickness of, for example, 30 nm is formed on the silicon oxide layer 12 by, eg, CVD (Chemical Vapor Deposition) (FIG. 9A).

  Next, a resist film 16 that covers the active region portion of the device and exposes the element isolation region is formed on the silicon nitride layer 14 by photolithography.

Next, using the resist film 16 as a mask, the silicon nitride layer 14 and the silicon oxide layer 12 are etched by RIE (Reactive Ion etching) method, and the silicon nitride layer 14 and the silicon oxide layer 12 in the element isolation region are etched. It is removed (FIG. 9B). As the etching conditions, for example, the substrate temperature is set to 60 ° C. to 80 ° C., the pressure in the processing chamber is set to 0.1 Pa to 1 Pa, the etching gas is CHF ₃ , CHF ₃ / CF ₄ / He / Ar, etc. It is preferable to stop at the surface of the substrate 10. When the etching selectivity between the silicon oxide layer 12 and the silicon substrate 10 is small, it is possible to perform etching for a time corresponding to the film thickness and to dig the surface of the silicon substrate 10 about several nm.

  Next, ashing is performed at a substrate temperature of 60 ° C. to 150 ° C. in a reduced pressure oxygen plasma environment, and the resist film 16 is removed.

  Next, the substrate from which the resist film 16 has been removed is treated with a mixed solution (SPM (sulfuric acid / hydrogen peroxide) solution: Sulfuric acid-hydrogen Peroxide Mixture) of about sulfuric acid: hydrogen peroxide = 3 to 8: 1 and washed.

Next, using the patterned silicon nitride layer 14 as a mask, the silicon substrate 10 is etched by, for example, RIE to form element isolation grooves 18 in the silicon substrate 10 (FIG. 9C). Etching conditions include, for example, a substrate temperature of 60 ° C. to 80 ° C., a pressure in the processing chamber of 0.1 Pa to 5 Pa, and an etching gas of Cl ₂ , HBr, HBr / O ₂ mixed gas, HBr / He mixed gas. It is desirable to obtain a sufficient selectivity (specifically, 10 or more) with respect to the silicon nitride layer 14 by using a gas system mainly composed of a halogen-based gas such as. The depth of the element isolation groove 18 is desirably about 100 nm to 500 nm. The width of the element isolation groove 18 depends on a desired device size and device layout, but is typically 100 nm to 1 μm.

  Next, cleaning with SPM solution, cleaning with hydrogen peroxide water: ammonia aqueous solution: water = 1: 1: 3 to 8 (APM (ammonia hydrogen peroxide) solution: ammonium hydroxide-hydrogen peroxide mixture) (temperature 70 ° C.) ), Hydrogen peroxide: hydrochloric acid: water = 1: 1: Washing with a mixed solution (HPM (hydrochloric acid perhydrogen) solution: Hydrochloric acid-hydrogen Peroxide Mixture) (temperature 70 ° C.) is sequentially performed.

  Next, a silicon oxide layer 20 is deposited on the entire surface by CVD, for example, using TEOS (Tetraethyl orthosilicate) as a raw material, and the element isolation trench 18 is filled with the silicon oxide layer 20 (FIG. 10A). The deposited film thickness of the silicon oxide layer 20 is at least equal to the film thickness corresponding to at least half of the width of the element isolation groove 18 so as to completely fill the element isolation groove 18.

  Next, the silicon oxide layer 20 on the silicon nitride layer 14 is removed by a CMP (Chemical Mechanical Polishing) method. Thus, an element isolation insulating film 22 made of the silicon oxide layer 20 embedded in the element isolation trench 18 is formed, and active regions 22A and 22B are defined in the silicon substrate 10 (FIG. 10B).

  Next, the substrate is cleaned with an SPM solution, an APM solution, and an HPM solution, and further treated with a diluted hydrofluoric acid solution (49%): water = 1: 20, and the surface of the element isolation insulating film 22 is etched by about 30 nm. At the same time, the SiON film (not shown) on the surface of the silicon nitride layer 14 is removed.

  Next, the silicon nitride layer 14 is removed by treatment with heated phosphoric acid at a temperature of about 120 ° C. to 180 ° C. (FIG. 10C). Since phosphoric acid does not etch silicon and silicon oxide, only the silicon nitride layer 14 can be removed.

Next, dopant impurities are introduced into the surface portion of the silicon substrate 10. The method for introducing the dopant impurity is not particularly limited, but ion implantation is desirable. When the back gate voltage is set to be negative, impurities including acceptor impurities such as B (boron) and BF ₂ (boron fluoride) are ion-implanted to introduce P-type carriers (holes) into the silicon substrate 10. . When the back gate voltage is set to be positive, impurities including donor impurities such as P (phosphorus), As (arsenic), and Sb (antimony) are ion-implanted to introduce N-type carriers (electrons) into the silicon substrate 10. To do.

The ion implantation conditions are set according to the trench depth of the element isolation insulating film 22, the conductivity required for the back gate electrode, and the like. For example, when the trench depth of the element isolation insulating film 22 is 100 nm, if BF ₂ ⁺ ions or As ⁺ ions, the acceleration energy is set to about 40 keV, and ion implantation is performed from a direction off by 7 ° with respect to the substrate normal direction. I do. The implantation dose is about 3 × 10 ¹⁵ cm ⁻² , for example.

  Next, the substrate is washed with an SPM solution, an APM solution, and an HPM solution, and then a heat treatment for diffusing and activating the implanted dopant impurities is performed to form an impurity layer 24 as a back gate electrode (FIG. 11A). ).

In this heat treatment, it is desirable that ion-implanted dopant impurities are diffused deeper than the element isolation insulating film 22. For example, when the trench depth of the element isolation insulating film 22 is 100 nm, heat treatment is performed at 1000 ° C. for about 10 minutes in a nitrogen stream. When the above-described ion implantation conditions are used, this heat treatment forms an impurity layer 24 having a high concentration region of 1 × 10 ²⁰ cm ⁻³ or more over a depth of about 150 nm or more from the surface of the silicon substrate 10.

  Next, treatment with a dilute hydrofluoric acid aqueous solution of hydrofluoric acid (49%): water = 1: 20 is performed to remove the silicon oxide layer 12 on the surface of the silicon substrate 10 (FIG. 11B). At room temperature, the etching time is typically about 1 minute to 2 minutes.

Next, a resist film 26 exposing the active region 22A is formed on the silicon substrate 10 by photolithography. The film thickness of the resist film 26 is desirably about 100 nm to 1 μm. Here, the film thickness is _{d Resist,} the source of the transistor - it is assumed that the width of the opening along the drain direction to form a resist film 26 is _{L AC} (Fig. 12 (a)).

  Next, using the resist film 26 as a mask, film formation is performed from the direction inclined toward the source region side with respect to the normal direction of the silicon substrate 10 by oblique sputtering to form a first gate insulating film 28 (FIG. 12). (B)). Thus, the first gate insulating film 28 whose film thickness gradually increases from the source region side to the drain region side is formed.

The inclination angle of the normal direction of the silicon substrate 10 with respect to the traveling direction of the sputtered molecules (which may be considered as the normal direction of the target surface) is appropriately selected according to the film thickness gradient required for the first gate insulating film 28. Is done. The inclination angle typically represents an angle formed between the traveling direction of the sputtered molecules (which may be generally considered as the normal direction of the target surface) and the normal direction of the silicon substrate 10 (represented by a one-dot chain line in the figure). _{As 1} ,
_{tanθ 1 = (L AC / 2} ) / d resist ~tanθ 1 = L AC / d resist
It is desirable to set it within the range. In the case of a typical device design in which the thickness of the resist film 26 is 1 μm and the width of the opening is 1 μm, the inclination angle θ ₁ should be set in a range of about 26.6 ° ≦ θ ₁ ≦ 45 °. Is desirable. Further, it is desirable not to rotate the silicon substrate 10 during film formation.

The first gate insulating film 28 is not particularly limited as long as it is a material from which a film having good insulating characteristics can be obtained by sputtering. For example, SiO ₂ , HfO ₂ , ZrO ₂ , Al ₂ O ₃ , _{HfAlO x, HfSiO x, Ta 2} O 5, TaHfOx, Y 2 O 3 and the like. Here, as an example, the case where the first gate insulating film 28 made of HfO ₂ is formed will be described as an example.

The first gate insulating film 28 made of HfO _2, for example, using a HfO ₂ target, the power 100W, 0.5 Pa and the deposition chamber pressure, at room temperature, can be deposited by RF magnetron sputtering.

Next, the resist film 26 is selectively removed. In order to remove the resist film 26, a method that causes little damage to the first gate insulating film 28 is appropriately selected according to the material for forming the first insulating film 28. For _{example, SiO 2, HfO 2, ZrO} 2, Al 2 O 3, HfAlO x, HfSiO x, Ta 2 O 5, TaHfOx, if Y 2 _{O 3,} etc., can be used SPM solution. By using the SPM solution, the resist film 26 can be removed without damaging the first gate insulating film 28. Further, the portion of the first gate insulating film 28 attached to the resist film 26 is removed together with the resist film 26 (FIG. 13A).

Next, a phase change material layer 36 to be a channel is formed on the first gate insulating film 28 by, eg, sputtering (FIG. 13B). As the phase change material layer 36, for example, a crystal alloy layer (GeTe layer) made of germanium and tellurium and a crystal alloy layer (Sb ₂ Te ₃ layer) made of antimony and tellurium have a <111> plane axis, respectively. It is possible to apply a superlattice structure laminated so that the c-axis and the c-axis are aligned.

For example, an RF sputtering apparatus in which targets made of pure metals of Ge, Sb, and Te are arranged, Ar is used as a sputtering gas under a pressure of 0.5 Pa, a power of 12.5 W is used as a Te target, and an Sb target is used. A 12.8 W power is appropriately applied to the Ge target, and a 45 W power is appropriately applied to the Ge target, and desired crystal alloy layers are sequentially stacked. It is desirable that the substrate temperature is appropriately selected according to the crystallization phase transition temperature of the crystal alloy layer to be formed. For example, since the crystallization phase transition temperature of Sb ₂ Te ₃ is about 100 ° C. and the crystallization phase transition temperature of GeTe is 230 ° C. at the maximum, the substrate temperature for fabricating the superlattice structure is at least 230 ° C. A high temperature is desirable.

For example, a 1 nm film having a 1: 1 composition of GeTe and a 6 nm film having a Sb ₂ Te ₃ composition (1 nm of Sb ₂ Te ₃ corresponds to 1QL) are repeatedly stacked. As a result, a phase change material layer 36 having a superlattice structure composed of repetition of [(Ge ₂ Te ₂ ) / (Sb ₂ Te ₃ ) ₆ ] is formed. The two different chalcogen compounds have a small lattice constant difference between the GeTe crystal [111] plane composed of cubic crystals distorted in the diagonal direction and the [0001] plane of Sb ₂ Te ₃ having cubic crystals, and share these planes. Thus, a uniaxial crystal oriented hetero superlattice structure can be formed. This superlattice can be easily fabricated by a vacuum film formation method such as sputtering at a temperature of 200 ° C. to 250 ° C.

  Next, a resist film 42 covering the active region 22A is formed by photolithography (FIG. 14A).

  Next, the phase change material layer 36 is dry-etched using the resist film 42 as a mask to selectively leave the phase change material layer 36 on the active region.

  Next, the resist film 42 is removed (FIG. 14B). The removal of the resist film 42 is performed by, for example, combustion peeling in an oxygen plasma at 100 ° C. and subsequent organic cleaning using acetone or the like.

  Note that the patterning step of the phase change material layer 36 may be appropriately performed as necessary, for example, when adjacent elements are separated when forming a plurality of transistors.

Next, a resist film 44 that exposes the active region 22A is formed on the silicon substrate 10 by photolithography. The film thickness of the resist film 44 is desirably about 100 nm to 1 μm. Here, the film thickness is _{d Resist,} the source of the transistor - it is assumed that the width of the opening along the drain direction to form a resist film 44 is _{L AC} (Fig. 15 (a)).

  Next, using the resist film 44 as a mask, the second gate insulating film 46 is formed by oblique sputtering from a direction inclined toward the drain region with respect to the normal direction of the silicon substrate 10 (FIG. 15). (B)). Thereby, the second gate insulating film 46 whose film thickness gradually decreases from the source region side toward the drain region side is formed.

The inclination angle of the normal direction of the silicon substrate 10 with respect to the traveling direction of the sputtered molecules (which may be considered to be the normal direction of the target surface) is appropriately selected according to the film thickness gradient required for the second gate insulating film 46. Is done. The inclination angle is typically represented by θ ₂ as an angle formed between the traveling direction of the sputtered molecules (which can be generally regarded as the normal direction of the target surface) and the normal direction of the silicon substrate 10.
_{tanθ 2 = (L AC / 2} ) / d resist ~tanθ 2 = L AC / d resist
It is desirable to set it within the range. In the case of a typical device design in which the thickness of the resist film 44 is 1 μm and the width of the opening is 1 μm, the inclination angle θ ₂ should be set in the range of about 26.6 ° ≦ θ ₂ ≦ 45 °. Is desirable. Further, it is desirable not to rotate the silicon substrate 10 during film formation.

The inclination angle theta ₂ is, _{| θ 2 | = | θ 1} | it is desirable to necessarily _{| θ 2 | = | θ 1} | and need not be. The film thickness of the second gate insulating film 46 may be the same as or different from the film thickness of the first gate insulating film 28.

  The film thickness and the film thickness gradient of the first gate insulating film 28 and the second gate insulating film 46 are appropriately set so that a desired electric field effect can be obtained from the gate electrode 52 and the back gate electrode (silicon substrate 10). It is desirable.

The second gate insulating film 46 is not particularly limited as long as the first gate insulating film 28 is a material capable of obtaining a film having good insulating characteristics by a sputtering method. For example, SiO ₂ , HfO ₂ , ZrO ₂ , Al ₂ O ₃ , HfAlO _x , HfSiO _x , Ta ₂ O ₅ , TaHfOx, Y ₂ O _{3 and the} like. Here, as an example, the case where the first gate insulating film 28 made of HfO ₂ is formed will be described as an example.

The second gate insulating film 46 made of HfO _2, for example, using a HfO ₂ target, the power 100W, 0.5 Pa and the deposition chamber pressure, at room temperature, it can be deposited by RF magnetron sputtering.

Next, the resist film 44 is selectively removed. In order to remove the resist film 44, a method with little damage to the second gate insulating film 46 is appropriately selected according to the material for forming the second insulating film 46. For _{example, SiO 2, HfO 2, ZrO} 2, Al 2 O 3, HfAlO x, HfSiO x, Ta 2 O 5, TaHfOx, if Y 2 _{O 3,} etc., can be used SPM solution. By using the SPM solution, the resist film 44 can be removed without damaging the second gate insulating film 46. Further, the portion of the second gate insulating film 46 attached to the resist film 44 is removed together with the resist film 44 (FIG. 16A).

  Next, a conductive material to be an electrode, for example, a TiN layer 48 having a film thickness of, for example, about 30 nm is formed on the entire surface by, eg, sputtering. For example, using an RF sputtering apparatus equipped with a pure metal Ti target, for example, sputtering is performed at a power of 1 kW in a gas of 0.1 Pa in which Ar and nitrogen are mixed at 1: 1, thereby forming the TiN layer 48. .

  Next, a resist film 50 having a pattern of the gate electrode 52 to be formed is formed on the TiN layer 48 by photolithography (FIG. 16B).

  Next, the TiN layer 48 is patterned using the resist film 50 as a mask, and a gate electrode 52 made of TiN is formed on the second gate insulating film 46 (FIG. 17A). The channel length is defined by the gate length of the gate electrode 52 formed in this way, but is shorter than the length (inelastic scattering length) in which Dirac electrons are scattered by phonons. Such a channel length is typically about 1 μm or less.

For patterning the TiN layer 48, a dry etching method and a wet etching method can be appropriately selected and used. For example, in the dry etching method, 30 nm of TiN can be etched by performing a treatment for about 30 seconds at 10 W of RF plasma power in a mixed gas of HBr and Ar. Not only this composition but also gas such as Ar or Cl ₂ can be used. In the wet etching method, a mixed solution of HF and H ₂ O ₂ or the like can be used. By performing etching for about 15 minutes with a solution in which hydrofluoric acid, hydrogen peroxide, and water are mixed at a composition of about 1: 1: 10, 30 nm of TiN can be etched.

  Next, the resist film 50 is removed. The removal of the resist film 50 is performed by, for example, combustion peeling in an oxygen plasma at 100 ° C. and subsequent organic cleaning using acetone or the like.

Next, for example, silicon oxide having a film thickness of about 300 nm is deposited on the entire surface by, eg, plasma CVD to form an interlayer insulating film 54 made of silicon oxide. Silicon oxide can be grown at a low temperature of about 200 ° C. to 350 ° C. by using, for example, silane gas and N ₂ O gas activated by plasma.

  Next, a photoresist film 56 exposing the contact region to the impurity layer 24 is formed on the interlayer insulating film 54 by photolithography.

Next, the interlayer insulating film 54 is etched using the photoresist film 56 as a mask, and a contact hole 58 reaching the impurity layer 24 is formed in the interlayer insulating film 54 (FIG. 18). As the etching conditions, for example, the substrate temperature is set to 60 ° C. to 80 ° C., the pressure in the processing chamber is set to 0.1 Pa to 1 Pa, the etching gas is CHF ₃ , CHF ₃ / CF ₄ / He / Ar, etc. It is preferable to stop at the surface of the substrate 10. When the etching selection ratio between the interlayer insulating film 54 made of silicon oxide and the silicon substrate 10 is small, it is possible to perform etching for a time corresponding to the film thickness and to dig the surface of the silicon substrate 10 by about several nm.

  Next, the resist film 56 is removed. The removal of the resist film 56 is performed by, for example, combustion peeling in an oxygen plasma at 100 ° C. and subsequent organic cleaning using acetone or the like.

  Next, a photoresist film 60 exposing the contact region to the gate electrode 52 and the contact region to the source / drain region of the phase change material layer 36 is formed on the interlayer insulating film 54 by photolithography.

Next, the interlayer insulating film 54 is etched using the photoresist film 60 as a mask, and a contact hole 62 reaching the gate electrode 52 and the saw slicing material layer 36 is formed in the interlayer insulating film 60 (FIG. 19A). As etching conditions, for example, the substrate temperature is set to 60 ° C. to 80 ° C., the pressure in the processing chamber is set to 0.1 Pa to 1 Pa, and CHF ₃ or the like is used as an etching gas.

Since TiN forming the gate electrode 54 has difficulty in etching with respect to CHF ₃ , the etching of the contact hole 62 stops on the gate electrode 52. Further, although CHF ₃ has a high etching rate with respect to oxide, the phase change material layer 36 is hardly etched, so that the etching of the contact hole 62 stops on the phase change material layer 36.

  Next, the resist film 60 is removed. The removal of the resist film 60 is performed by, for example, combustion peeling in an oxygen plasma at 100 ° C. and subsequent organic cleaning using acetone or the like. Further, a treatment with a dilute hydrofluoric acid aqueous solution of hydrofluoric acid (49%): water = 1: 20 is performed to remove a natural oxide film or the like on the surface of the silicon substrate 10.

  Next, a conductive film 64 to be a wiring layer is deposited on the entire surface by sputtering (FIG. 19B). The conductive film 64 is not particularly limited. For example, a TiN layer or a laminated structure of Al / TiN (10 nm) / Ti (2 nm) can be applied.

  Next, a photoresist film 66 having an electrode pad pattern is formed on the conductive film 64.

  Next, the conductive film 64 is patterned using the photoresist film 66 as a mask, and wirings 68A, 68B, 68C, and 68D electrically connected to the gate electrode 52, the source and drain regions of the phase change material layer 36, and the impurity layer 24. Is formed (FIG. 20A). Note that the wiring 68B is a source electrode, and the wiring 68C is a drain electrode.

  For example, the conductive layer 64 can be etched only without etching the interlayer insulating film 54 by performing etching with a bias power of 10 W using chlorine gas of 0.3 Pa.

  Next, the resist film 66 is removed. The resist film 66 is removed by, for example, combustion peeling in an oxygen plasma at 100 ° C. and subsequent organic cleaning using acetone or the like (FIG. 20B).

  Thereafter, a predetermined back-end process is performed as necessary to complete the field effect transistor according to the present embodiment.

  Thus, according to the present embodiment, it is possible to realize a high-speed and low power consumption field effect transistor that achieves both high channel mobility and high on / off ratio.

[Second Embodiment]
The field effect transistor and the manufacturing method thereof according to the second embodiment will be described with reference to FIGS. The same components as those of the field effect transistor and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 20 are denoted by the same reference numerals, and description thereof will be omitted or simplified.

  FIG. 21 is a schematic cross-sectional view showing the structure of the field effect transistor according to the present embodiment. 22 to 28 are process cross-sectional views illustrating the method for manufacturing the field effect transistor according to the present embodiment.

[Cross-sectional structure and operation outline of field effect transistor]
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIG.

  An impurity layer 24 is formed on the silicon substrate 10. On the silicon substrate 10 on which the impurity layer 24 is formed, an element isolation insulating film 22 that defines the active regions 22A and 22B is formed.

  On the active region 22A of the silicon substrate 10, a first gate insulating film 34, a phase change material layer 36, and a second gate insulating film 74 are stacked. The phase change material layer 36 is formed of a Dirac electronic material in which topological phase transition occurs. The dielectric constant of the first gate insulating film 34 gradually decreases from the source region side (left side in the figure) to the drain region side (right side in the figure). On the other hand, the dielectric constant of the second gate insulating film 74 gradually increases from the source region side (left side in the figure) to the drain region side (right side in the figure).

  Thereby, the silicon substrate 10 includes an impurity layer 24 functioning as a back gate electrode, a first gate insulating film 28, a phase change material layer 36 functioning as a channel layer, a second gate insulating film 46, and a top gate electrode. A field effect transistor having the gate electrode 52 is formed.

  An interlayer insulating film 54 is formed on the silicon substrate 10 on which the field effect transistor is formed. On the interlayer insulating film 54, wiring 68A connected to the gate electrode 52, wirings 68B (source electrode) and 68C (drain electrode) connected to the phase change material layer 36, and wiring 68D connected to the impurity layer 24 are provided. Is formed.

  As described above, the field effect transistor according to the present embodiment uses the phase change material layer 36 in which the topological phase transition occurs as a channel layer, and the current flowing between the source electrode (wiring 68B) and the drain electrode (wiring 68C) It is controlled by an electric field applied between the gate electrode (impurity layer 24) and the top gate electrode (gate electrode 52).

  In the field effect transistor according to the present embodiment, the first from the source region side toward the drain region side so that a gradient is formed along the channel length direction in the electrostatic potential of the channel layer (phase change material layer 36). The gate insulating film 34 has a low dielectric constant, and the second gate insulating film 74 has a high dielectric constant. By doing so, it is possible to give a gradient to the electrostatic potential in the channel layer along the channel length direction.

  In order to form a gradient along the channel length direction in the electrostatic potential in the channel layer, the capacitance of the first gate insulating film 34 decreases from the source region side toward the drain region side, It is desirable that the capacitance of the second gate insulating film 74 is large. Here, when the area is constant, the parameters for changing the capacitance may be the film thickness and the dielectric constant. Among these, the field effect transistor according to the first embodiment utilizes the change in the thickness of the gate insulating film. In the field effect transistor of this embodiment, a gradient is formed along the channel length direction in the electrostatic potential of the channel layer by utilizing the change in the dielectric constant of the gate insulating film.

  The first gate insulating film 34 and the second gate insulating film 74 are, for example, a first dielectric material having a first dielectric constant and a second dielectric constant having a second dielectric constant larger than the first dielectric constant. It can be realized by forming a mixed crystal with two dielectric materials and gradually changing the composition along the channel length direction.

For example, as the first gate insulating film 34, a film whose composition gradually changes from Al ₂ O ₃ → HfAlO _x → HfO ₂ from the source region side toward the drain region side can be used. As the second gate insulating film 74, a film whose composition gradually changes from HfO ₂ → HfAlO _x → Al ₂ O ₃ from the source region side to the drain region side can be used.

The dielectric material whose dielectric constant varies depending on the composition includes HfAlO _x (HfO ₂ —Al ₂ O ₃ compound), HfSiO _x (HfO ₂ —SiO ₂ compound), ZrArO _x (ZrO ₂ —Al). ₂ O ₃ compound), ZrSiO _x (ZrO ₂ —SiO ₂ compound) and many other dielectric materials.

Also, the dielectric constant of the film can be changed by doping the book layer of dielectric material with a small amount of impurities to change the crystal structure. As such a material system, a system in which HfO ₂ is doped with a small amount (several percent) of Si, Y, or the like can be considered.

  The material for forming the first gate insulating film 34 and the second gate insulating film 74 can be arbitrarily selected from these. The dielectric material forming the first gate insulating film 34 and the dielectric material forming the second gate insulating film 74 may be the same or different.

Also, the dielectric constant of the film can be changed by doping the book layer of dielectric material with a small amount of impurities to change the crystal structure. As such a material system, a system in which HfO ₂ is doped with a small amount (several percent) of Si, Y, or the like can be considered.

[Driving Method of Field Effect Transistor]
The operation of the field effect transistor according to the present embodiment is the same as that of the field effect transistor according to the first embodiment.

[Method for Manufacturing Field Effect Transistor]
Next, the method for fabricating the field effect transistor according to the present embodiment will be explained with reference to FIGS.

  First, for example, in the same manner as in the method of manufacturing the field effect transistor according to the first embodiment shown in FIGS. 9A to 11B, the element isolation insulating film 22 that defines the active regions 22A and 22B on the silicon substrate 10 is used. Then, the impurity layer 24 is formed (FIG. 22A).

Next, a resist film 26 exposing the active region 22A is formed on the silicon substrate 10 by photolithography. The film thickness of the resist film 26 is desirably about 100 nm to 1 μm. Here, the film thickness is the _{d Resist,} the source of the transistor - the width of the opening along the drain direction is assumed to form a resist film 26 is _{L AC} (Fig. 22 (b)).

  Next, the resist film 26 is used as a mask to form a film from a direction inclined to the source region side with respect to the normal direction of the silicon substrate 10 by an oblique sputtering method, and the film thickness increases from the source region side to the drain region side. A gradually increasing low dielectric constant film 30 is formed (FIG. 23A).

The inclination angle of the normal direction of the silicon substrate 10 with respect to the traveling direction of the sputtered molecules (which can be considered as the normal direction of the target surface) is appropriately selected according to the film thickness gradient required for the low dielectric constant film 30. . The inclination angle typically represents an angle formed between the traveling direction of the sputtered molecules (which may be generally considered as the normal direction of the target surface) and the normal direction of the silicon substrate 10 (represented by a one-dot chain line in the figure). _{As 1} ,
_{tanθ 1 = (L AC / 2} ) / d resist ~tanθ 1 = L AC / d resist
It is desirable to set it within the range. In the case of a typical device design in which the thickness of the resist film 26 is 1 μm and the width of the opening is 1 μm, the inclination angle θ ₁ may be set in a range of about 26.6 ° ≦ θ ≦ 45 °. desirable. Further, it is desirable not to rotate the silicon substrate 10 during film formation. The maximum film thickness of the low dielectric constant film 30 is desirably about 2 nm.

When the first gate insulating film to be formed is HfAlO _x , HfSiO _x , ZrArO _x , ZrSiO _x , the low dielectric constant film 30 is formed of Al ₂ O ₃ , SiO ₂ , Al ₂ O ₃ , SiO ₂ , respectively. To do. Further, as an example of changing the dielectric constant by adding impurities to the matrix and changing the crystal structure of the matrix, when doping a small amount (several percent) of Si, Y or the like into HfO ₂ , SiO Deposit ₂ or Y ₂ O ₃ .

In any case of Al ₂ O ₃ , SiO _2, and Y ₂ O ₃ , film formation is performed by RF magnetron sputtering with these oxides as targets and power of 100 W, film formation chamber pressure of 0.5 Pa, and room temperature. be able to.

  Next, a high dielectric constant film 32 is formed by sputtering using the resist film 26 as a mask (FIG. 23B). The high dielectric constant film 32 is desirably deposited perpendicularly to the substrate normal direction, that is, with a uniform film thickness. The film thickness of the high dielectric constant film 32 is preferably about 2 nm to 10 nm.

When the first gate insulating film to be formed is HfAlO _x , HfSiO _x , ZrArO _x , ZrSiO _x , the high dielectric constant film 32 is HfO ₂ , HfO ₂ , ZrO ₂ , ZrO ₂ , respectively. As an example of changing the dielectric constant by adding impurities to the matrix and changing the crystal structure of the matrix, HfO ₂ is doped with a small amount (several percent) of Si, Y, etc. ₂ is deposited.

Next, the resist film 26 is selectively removed. In order to remove the resist film 26, a method with little damage to these films is appropriately selected according to the material for forming the low dielectric constant film 30 and the high dielectric constant film 32. For _{example, SiO 2, HfO 2, ZrO} 2, Al 2 O 3, HfAlO x, HfSiO x, Ta 2 O 5, TaHfOx, if Y 2 _{O 3,} etc., can be used SPM solution. By using the SPM solution, the resist film 26 can be removed without damaging the low dielectric constant film 30 and the high dielectric constant film 32. The portions of the low dielectric constant film 30 and the high dielectric constant film 32 attached to the resist film 26 are removed together with the resist film 26 (FIG. 24A).

Next, heat treatment is performed at 500 ° C. to 1000 ° C. in a nitrogen stream. The heat treatment time depends on the insulating film material, but in the case of HfAlO _x (HfO ₂ —Al ₂ O ₃ ), 500 ° C. to 900 ° C. is desirable. By this heat treatment, a reaction occurs between the low dielectric constant film 30 and the high dielectric constant film 32, or the constituent elements (Si, Y) of the low dielectric constant film 30 are impurities as impurities in the high dielectric constant film 32. To be doped. Thereby, the first gate insulating film 34 having a lower dielectric constant is formed from the source region side toward the drain region side (FIG. 24B).

  Next, a phase change material layer 36 serving as a channel is formed on the first gate insulating film 34 in the same manner as in the method of manufacturing the field effect transistor according to the first embodiment shown in FIG. c)).

  Next, a resist film 42 covering the active region 22A is formed by photolithography.

  Next, the phase change material layer 36 is dry-etched using the resist film 42 as a mask to selectively leave the phase change material layer 36 on the active region 22A (FIG. 25A).

  Next, the resist film 42 is removed. The removal of the resist film 42 is performed by, for example, combustion peeling in an oxygen plasma at 100 ° C. and subsequent organic cleaning using acetone or the like.

  Note that the patterning step of the phase change material layer 36 may be appropriately performed as necessary, for example, when adjacent elements are separated when forming a plurality of transistors.

Next, a resist film 44 that exposes the active region 22A is formed on the silicon substrate 10 by photolithography. The film thickness of the resist film 44 is desirably about 100 nm to 1 μm. Here, the film thickness is _{d Resist,} the source of the transistor - it is assumed that the width of the opening along the drain direction to form a resist film 44 is _{L AC} (Fig. 25 (b)).

  Next, the resist film 44 is used as a mask to form a film from a direction inclined to the drain region side with respect to the normal direction of the silicon substrate 10 by an oblique sputtering method, and the film thickness increases from the drain region side to the source region side. A gradually increasing low dielectric constant film 70 is formed (FIG. 26A).

The inclination angle of the normal direction of the silicon substrate 10 with respect to the traveling direction of the sputtered molecules (which can be considered as the normal direction of the target surface) is appropriately selected according to the gradient of the film thickness required for the low dielectric constant film 70. . The inclination angle typically represents an angle formed between the traveling direction of the sputtered molecules (which may be generally considered as the normal direction of the target surface) and the normal direction of the silicon substrate 10 (represented by a one-dot chain line in the figure). _{2
tanθ 2 = (L AC / 2} ) / d resist ~tanθ 2 = L AC / d resist
It is desirable to set it within the range. In the case of a typical device design in which the thickness of the resist film 44 is 1 μm and the width of the opening is 1 μm, the inclination angle θ ₂ may be set in a range of about 26.6 ° ≦ θ ≦ 45 °. desirable. Further, it is desirable not to rotate the silicon substrate 10 during film formation. The maximum film thickness of the low dielectric constant film 70 is desirably about 2 nm. The inclination angle theta ₂ is, _{| θ 2 | = | θ 1} | it is desirable to necessarily _{| θ 2 | = | θ 1} | and need not be.

  The material selection example of the low dielectric constant film 70 is the same as that of the low dielectric constant film 30.

  Next, a high dielectric constant film 72 is formed by sputtering using the resist film 44 as a mask (FIG. 26B). The high dielectric constant film 72 is preferably deposited perpendicularly to the substrate normal direction, that is, with a uniform film thickness. The film thickness of the high dielectric constant film 72 is preferably about 2 nm to 10 nm.

  The material selection example of the low dielectric constant film 72 is the same as that of the low dielectric constant film 32.

Next, the resist film 44 is selectively removed. In order to remove the resist film 44, a method with little damage to these films is appropriately selected according to the material for forming the low dielectric constant film 70 and the high dielectric constant film 72. For _{example, SiO 2, HfO 2, ZrO} 2, Al 2 O 3, HfAlO x, HfSiO x, Ta 2 O 5, TaHfOx, if Y 2 _{O 3,} etc., can be used SPM solution. By using the SPM solution, the resist film 44 can be removed without damaging the low dielectric constant film 70 and the high dielectric constant film 72. The portions of the low dielectric constant film 70 and the high dielectric constant film 72 attached to the resist film 44 are removed together with the resist film 44 (FIG. 27A).

Next, heat treatment is performed at 500 ° C. to 1000 ° C. in a nitrogen stream. The heat treatment time depends on the insulating film material, but in the case of HfAlO _x (HfO ₂ —Al ₂ O ₃ ), 500 ° C. to 900 ° C. is desirable. By this heat treatment, a reaction occurs between the low dielectric constant film 70 and the high dielectric constant film 72, or the constituent elements (Si, Y) of the low dielectric constant film 70 are used as impurities in the high dielectric constant film 72 as a parent phase. To be doped. Thereby, the second gate insulating film 74 having a higher dielectric constant is formed from the source region side toward the drain region side (FIG. 27B).

  Next, a gate electrode 52 is formed on the second gate insulating film 72 in the same manner as in the method of manufacturing the field effect transistor according to the first embodiment shown in FIGS. 16B to 17A (FIG. 28B). a)).

  Next, in the same manner as in the method of manufacturing the field effect transistor according to the first embodiment shown in FIGS. 17B to 20B, the interlayer insulating film 54 and the wirings 68A, 68B, 68C, and 68D are formed (FIG. 28). (B)).

  Thereafter, a predetermined back-end process is performed as necessary to complete the field effect transistor according to the present embodiment.

  Thus, according to the present embodiment, it is possible to realize a high-speed and low power consumption field effect transistor that achieves both high channel mobility and high on / off ratio.

[Third Embodiment]
The field effect transistor and the method for manufacturing the same according to the third embodiment will be described with reference to FIGS. Constituent elements similar to those of the field effect transistor and the manufacturing method thereof according to the first and second embodiments shown in FIGS. 1 to 28 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  FIG. 29 is a schematic cross-sectional view showing the structure of the field effect transistor according to the present embodiment. 30 and 31 are energy band diagrams for explaining the operation of the field effect transistor according to the present embodiment. 32 to 35 are process cross-sectional views illustrating the method for manufacturing the field effect transistor according to the present embodiment.

[Cross-sectional structure and operation outline of field effect transistor]
First, the structure of the field effect transistor according to the present embodiment will be explained with reference to FIG.

  A first gate insulating film 82 is formed on the silicon substrate 80. A phase change material layer 84 is formed on the first gate insulating film 82. A source electrode 88 and a drain electrode 90 are formed on the first gate insulating film 82 so as to be connected to both ends of the phase change material layer 84. A second gate insulating film 92 is formed on the phase change material layer 84 between the source electrode 88 and the drain electrode 90. On the second gate insulating film 92, gate electrodes 96A, 96B, and 96C are formed.

  As described above, the field effect transistor according to the present embodiment uses the phase change material layer 84 as the channel layer, and converts the current flowing between the source electrode 88 and the drain electrode 90 into the back gate electrode (silicon substrate 10) and the top gate electrode. It is controlled by an electric field applied between (gate electrodes 96A, 96B, 96C).

  In the field effect transistor according to the present embodiment, a plurality of gate electrodes 96A and 96B to which different drive voltages can be applied so that a gradient is formed along the channel length direction in the electrostatic potential of the channel layer (phase change material layer 84). , 96C. By doing so, it is possible to bend the electrostatic potential in the channel layer along the channel length direction and block electron transmission in the band gap in a wide energy region. That is, the size of the energy region where electron transmission is blocked can be increased by increasing the number of top gate electrodes.

[Driving Method of Field Effect Transistor]
Next, the operation of the field effect transistor according to the present embodiment will be explained with reference to FIGS.

  First, preconditions for driving the transistor will be described.

The source is grounded, and its potential V _S is set equal to the Fermi level E _F (V _S = −E _F / e = 0). Further, the back gate electrode by applying a positive voltage, the electrostatic governed sufficiently higher than the bottom of the conduction band and the Fermi level E _F of the source region by (field effect doping), i.e. such that the degenerate extreme (E _F -E _C >> k _B T).

  Next, voltage application conditions for turning off the transistor will be described.

When the transistor is turned off, voltages V _TGA , V _TGB , and V _TGC are applied to the gate electrodes 96A, 96B, and 96C, which are the top gate electrodes, in a relationship of 0> V _TGA > V _TGB > V _TGC , respectively. To do. Further, the positive voltage _VBG is applied to the back gate electrode as described above. The source electrode 88 is grounded, and a positive voltage is applied to the drain electrode 90 so that a predetermined source-drain voltage is applied.

When such a voltage is applied to each terminal of the transistor, an energy band structure in a region from the source region to the drain region through the channel region is as illustrated in FIG. In Figure 30, E _F is the Fermi level, E _C is the band edge of the conduction band, E _V is the band edge of the valence band, U is represents the electrostatic potential.

That is, the back gate electrode, the positive voltage V _BG is applied, the channel region between the source region and the drain region, the electrostatic potential U is lowered than the Fermi level E _F. Fermi level E _F is the source region side is highest by the drain voltage, the drain region side is the lowest.

  Further, by applying a negative driving voltage as described above to the gate electrodes 96A, 96B, 96C, the electrostatic potential U of the channel layer of the gate electrodes 96A, 96B, 96C is raised. The effect of electrostatic control (field effect doping) by the gate electrodes 96A, 96B, and 96C is greater in the gate electrode 96 on the drain region side than on the gate electrode 96 on the source region side, depending on the magnitude of the applied voltage. Therefore, the electrostatic potential U is greatly increased as the gate electrode 96 is closer to the drain region.

In addition to the electrostatic potential U, the band gap is lifted in the channel region under the gate electrodes 96A, 96B, and 96C. This band gap prevents coherent electron transmission and forms a transport gap on the energy axis, so that the transport gap by each top gate overlaps on the energy axis so that no drain current flows. Is convenient. Therefore, a voltage difference between adjacent top gates that minimizes the drain current is obtained, and top gate voltages V _TGA , V _TGB , and V _TGC that satisfy the voltage difference condition are used. desirable.

When the band gap is bent as shown in FIG. 30, in order for the electrons to escape from the source region side to the drain region side, the electrons in the source region are from the energy E _{C at} the bottom of the conduction band lifted by the rightmost top gate. Must be thermally excited to a higher energy level. This is because the energy region from the energy level to the energy E _{C at} the bottom of the conduction band in the source region is covered with the transport gap, and electrons cannot be transmitted. In order for electrons to escape from the source region side to the drain region side in this energy region, they must pass through the band gap. In this transistor, energy is exchanged with phonons in the channel (or by other inelastic scattering). Since the energy of the electrons does not change and is constant, the electrons cannot pass through the channel by band-to-band tunneling by wrapping around where the band gap is thin. Incidentally, the phonon scattering does not occur in the channel region because the transistor is manufactured so that the channel length is shorter than the inelastic scattering length.

  As a result, no drain current flows and the transistor is turned off.

  Next, voltage application conditions for turning on the transistor will be described.

When the transistor is turned on, the gate electrodes 96A, 96B, and 96C, which are the top gate electrodes, have voltages V _TGA , V _TGB , and V that are sufficiently small or 0 V so that the energy band is not lifted by them. Each _TGC is applied. Further, the positive voltage _VBG is applied to the back gate electrode as described above. The source electrode 88 is grounded, and a positive voltage is applied to the drain electrode 90 so that a predetermined source-drain voltage is applied.

When such a voltage is applied to each terminal of the transistor, an energy band structure in a region from the source region to the drain region through the channel region is as illustrated in FIG. In Figure 31, E _F is the Fermi level, E _C is the band edge of the conduction band, E _V is the band edge of the valence band, U is represents the electrostatic potential.

Thus, since the source region to the drain region energy bands leads without causing a step, the Fermi level of the electrons of E _F of the source region, the transmission to the drain region ballistically (or keeping the electrons coherence) As a result, drain current flows and the transistor is turned on.

As you just increase the drain voltage V _DS, the Fermi level E _F of the drain region, pushed down below the Fermi level E _F of the source region. As a result, electrons in the conduction band on the source region side can escape to the open energy level on the drain region side.

A source region of the transistor due to the degeneracy extreme, the drain current is proportional to the difference in the Fermi level E _F the Fermi level E _F and the drain region of the source region. That is, the drain current increases in proportion to the drain voltage ratio. However, the Fermi level E _F of the drain region is smaller than the energy E _C at the bottom of the conduction band of the source region, eventually, the drain current is greater, increasing not (Non-Patent Document 8). That is, the drain current is saturated.

  As described above, the field effect transistor according to the present embodiment can saturate the drain current while maximizing the carrier mobility in the channel region without being blocked by the dilemma of the conventional graphene transistor.

[Method for Manufacturing Field Effect Transistor]
Next, the method for fabricating the field effect transistor according to the present embodiment will be explained with reference to FIGS.

  First, a silicon oxide layer having a thickness of, for example, 10 nm is formed on a silicon substrate 80 having a (100) plane orientation by, for example, thermal oxidation, for example, in an oxygen atmosphere at a temperature of 800 ° C. for 10 minutes. . Thus, a first gate insulating film 82 made of a silicon oxide layer is formed (FIG. 32A). As in the first and second embodiments, the element isolation insulating film 22 and the impurity layer 24 may be provided on the silicon substrate 80.

  The film thickness of the first gate insulating film 82 is desirably selected as appropriate in consideration of electrostatic influences from the gate electrodes 96A, 96B, 96C and the silicon substrate 80 as the back gate electrode. That is, the thinner the film, the stronger the electrostatic control from the back gate electrode in the source and drain regions. The constituent material of the first gate insulating film 82 is not limited to silicon oxide, and other insulating films such as silicon nitride and a high dielectric constant insulating film can be appropriately selected. Further, the film forming method is not particularly limited, and it may be formed by a CVD method, a sputtering method, or the like.

Next, a phase change material layer 84 to be a channel layer is formed on the first gate insulating film 82 by, eg, sputtering (FIG. 32B). The phase change material layer 84, for example, crystalline alloy layer made of germanium and tellurium and (GeTe layer), the crystalline alloy layer consisting of antimony and tellurium _(Sb 2 Te ₃ layer) and a respective having <111> plane axis It is possible to apply a superlattice structure laminated so that the c-axis and the c-axis are aligned.

For example, an RF sputtering apparatus in which targets made of pure metals of Ge, Sb, and Te are arranged, Ar is used as a sputtering gas under a pressure of 0.5 Pa, a power of 12.5 W is used as a Te target, and an Sb target is used. A 12.8 W power is appropriately applied to the Ge target, and a 45 W power is appropriately applied to the Ge target, and desired crystal alloy layers are sequentially stacked. It is desirable that the substrate temperature is appropriately selected according to the crystallization phase transition temperature of the crystal alloy layer to be formed. For example, since the crystallization phase transition temperature of Sb ₂ Te ₃ is about 100 ° C. and the crystallization phase transition temperature of GeTe is 230 ° C. at the maximum, the substrate temperature for fabricating the superlattice structure is at least 230 ° C. A high temperature is desirable.

For example, a 1 nm film having a 1: 1 composition of GeTe and a 6 nm film having a Sb ₂ Te ₃ composition (1 nm of Sb ₂ Te ₃ corresponds to 1QL) are repeatedly stacked. As a result, a phase change material layer 84 having a superlattice structure composed of repetition of [(Ge ₂ Te ₂ ) / (Sb ₂ Te ₃ ) ₆ ] is formed.

  Next, the phase change material layer 84 is patterned into a predetermined shape by photolithography and etching (FIG. 33A). This patterning step may be appropriately performed as necessary, for example, when adjacent elements are separated when forming a plurality of transistors. The phase change material layer 84 is patterned by bringing the source electrode 88 and the drain electrode 90 into contact with the side surface portion of the phase change material layer 84 and injecting carriers directly into the alloy crystal layer having high conductivity from the source side. There is also an advantage that a larger current can be obtained.

  Next, a conductive material to be an electrode, for example, a TiN layer 86 having a film thickness of, for example, about 30 nm is formed on the phase change material layer 84 by, eg, sputtering (FIG. 33B). For example, by using an RF sputtering apparatus equipped with a pure metal Ti target, sputtering is performed at a power of 1 kW in a gas of 0.1 Pa in which Ar and nitrogen are mixed at 1: 1, for example, thereby forming the TiN layer 86. .

Next, the TiN layer 86 is patterned by photolithography and etching to form the source electrode 88 and the drain electrode 90 disposed at both ends of the phase change material layer 84 (FIG. 34A). For etching the TiN layer 86, a dry etching method and a wet etching method can be selected and used as appropriate. For example, in dry etching, 30 nm of TiN can be etched by performing a treatment for about 30 seconds at 1500 W of RF plasma power in a mixed gas of HBr and Ar. Not only this composition but also gas such as Ar or Cl ₂ can be used. In the wet etching method, a mixed solution of HF and H ₂ O ₂ or the like can be used. By performing etching for about 15 minutes with a solution in which hydrofluoric acid, hydrogen peroxide, and water are mixed at a composition of about 1: 1: 10, 30 nm of TiN can be etched.

  The distance between the source electrode 88 and the drain electrode 90 is shorter than the length (inelastic scattering length) in which Dirac electrons are scattered by phonons, but is preferably 1 μm or less.

  Next, a second gate insulating film 92 is formed on the phase change material layer 84 by, for example, a CVD method or a sputtering method (FIG. 34B). The constituent material and film thickness of the second gate insulating film 92 are preferably selected as appropriate in consideration of electrostatic influences from the gate electrodes 96A, 96B, and 96C and the silicon substrate 80 as the back gate electrode. In order to maintain good insulation, the film thickness is desirably 2 nm or more.

In the case where the second gate insulating film 92 is formed by a sputtering method, a material from which a film having good insulating properties can be obtained by the sputtering method, for example, SiO ₂ , HfO ₂ , ZrO ₂ , Al ₂ O ₃ , HfAlO _x , HfSiO _x , Ta ₂ O ₅ , TaHfOx, Y ₂ O _{3 and the} like are desirable. Here, as an example, the case where the second gate insulating film 92 made of HfO ₂ is formed will be described as an example.

The second gate insulating film 92 made of HfO _2, for example, using a HfO ₂ target, the power 100W, 0.5 Pa and the deposition chamber pressure, at room temperature, it can be deposited by RF magnetron sputtering.

  Next, a conductive material, for example, a TiN layer 94, having a thickness of, for example, about 30 nm and serving as the gate electrodes 96A, 96B, 96C is formed on the second gate insulating film 92 by, eg, sputtering (FIG. 35A). . For example, by using an RF sputtering apparatus equipped with a pure metal Ti target, sputtering is performed at a power of 1 kW in a gas of 0.1 Pa in which Ar and nitrogen are mixed at 1: 1, for example, thereby forming the TiN layer 94. .

Next, the TiN layer 94 is patterned by photolithography and etching to form gate electrodes 96A, 96B, and 96C on the second gate insulating film 92 between the source electrode 88 and the drain electrode 90 (FIG. 35B). )). For etching the TiN layer 94, a dry etching method and a wet etching method can be selected and used as appropriate. For example, in dry etching, 30 nm of TiN can be etched by performing a treatment for about 30 seconds at 1500 W of RF plasma power in a mixed gas of HBr and Ar. Not only this composition but also gas such as Ar or Cl ₂ can be used. In the wet etching method, a mixed solution of HF and H ₂ O ₂ or the like can be used. By performing etching for about 15 minutes with a solution in which hydrofluoric acid, hydrogen peroxide, and water are mixed at a composition of about 1: 1: 10, 30 nm of TiN can be etched.

  The interval between the gate electrodes 96A, 96B, and 96C is desirably 30 nm or more so that the fringe effect of the electric field induced by the gate voltage does not become a problem. The gate length is determined from the channel length and the gate electrode interval. The gate lengths of the respective gate electrodes 96A, 96B, and 96C may be formed with different dimensions so as to obtain optimum performance.

  Thereafter, a predetermined back-end process is performed as necessary to complete the field effect transistor according to the present embodiment.

  Thus, according to the present embodiment, it is possible to realize a high-speed and low power consumption field effect transistor that achieves both high channel mobility and high on / off ratio.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, in the first embodiment, the film thickness of the first gate insulating film is gradually increased from the source region side to the drain region side, but the film thickness of the first gate insulating film is necessarily changed. There is no. In the second embodiment, the dielectric constant of the first gate insulating film is gradually decreased from the source region side toward the drain region side. However, the dielectric constant of the first gate insulating film is not necessarily changed. There is no. In order to incline the electrostatic potential of the channel layer, it is sufficient to change the film thickness or the dielectric constant of at least the second gate insulating film, and change both the first gate insulating film and the second gate insulating film. It is not always necessary to make it.

  In the first embodiment, the thicknesses of the first gate insulating film and the second gate insulating film are changed. In the second embodiment, the dielectrics of the first gate insulating film and the second gate insulating film are changed. Although the rate was changed, these may be arbitrarily combined. For example, the film thickness of the first gate insulating film may be changed to change the dielectric constant of the second gate insulating film, or the dielectric constant of the first gate insulating film may be changed to change the second gate insulating film. The thickness of the insulating film may be changed. Further, both the film thickness and the dielectric constant may be changed.

  In the first and second embodiments, the constituent material of the first gate insulating film and the constituent material of the second gate insulating film are the same. However, it is not always necessary to use the same material. You may make it combine.

In the first to third embodiments, as an example of the Dirac electronic material constituting the channel layer, the phase change material in which the topological phase transition is caused by the application of the electric field has been described. It need not be a change material. For example, double-layer graphene that opens a band gap by applying an electric field may be used. Further, in the field effect transistor of the third embodiment, it is not necessary to open a band gap by applying an electric field, so that other Dirac electronic materials such as armchair graphene nanoribbons having a band gap and MoS ₂ are applied. It may be.

  In the first to third embodiments, the phase change material mainly composed of Ge, Te, or Bi is exemplified as the phase change material in which the transition of the topological phase is caused by the application of the electric field. However, the first to third embodiments are applied to the above embodiment. Possible phase change materials are not limited to this. Research on topological insulators has just begun, and various materials may be found in the future. Any material that undergoes a phase transition between a normal insulator and a topological insulator by application of an electric field can be used instead of a phase change material mainly composed of Ge, Te, or Bi.

In the above embodiment, an example in which a phase change material that changes from a normal insulator to a topological insulator by applying an external electric field is used as the material of the channel layer is shown. However, a topological insulator is applied by applying an external electric field. A phase change material that changes from a normal insulator to a normal insulator may be used. For example, in a phase change material having a superlattice structure in which a GeTe layer and an Sb ₂ Te ₃ layer are stacked, an Sb ₂ Te ₃ layer of 4QLs or more may be used. In this case as well, the voltage applied to each terminal of the transistor may be set as appropriate so as to exhibit a Dirac electronic conduction mechanism when the transistor is on.

  In the third embodiment, a field effect transistor having three top gate electrodes is shown. However, the number of top gate electrodes is not limited to this, and can be increased or decreased as appropriate.

  In the third embodiment, the second gate insulating film is formed of a uniform material. However, as in the first or second embodiment, the film thickness is changed or the dielectric constant is changed. Also good.

  In addition, the constituent materials, manufacturing conditions, and the like of each constituent part of the field effect transistor described in the above embodiment are merely examples, and can be appropriately modified or changed according to the common general knowledge of those skilled in the art. .

DESCRIPTION OF SYMBOLS 10,80 ... Silicon substrate 12, 20 ... Silicon oxide layer 14 ... Silicon nitride layer 16, 26, 32, 42, 44, 50, 56, 60, 66 ... Resist film 18 ... Element isolation groove 22 ... Element isolation insulating film 24 ... impurity layer (back gate electrode)
28, 34, 82 ... first gate insulating film 30, 70 ... low dielectric constant film 32, 72 ... high dielectric constant film 36, 84 ... phase change material layer 46, 74, 92 ... second gate insulating film 48, 86, 94: TiN layers 52, 96A, 96B, 96C ... Gate electrodes 54 ... Interlayer insulating films 58, 62 ... Contact holes 64 ... Conductive films 68A, 68B, 68C, 68D ... Wiring 88 ... Source electrodes 90 ... Drain electrodes

Claims (12)

A channel layer made of Dirac electronic material,
A source electrode and a drain electrode connected to the channel layer;
A first gate insulating film formed on a first surface of the channel layer between the source electrode and the drain electrode;
A first gate electrode formed on the first insulating film;
A second gate insulating film formed on a second surface of the channel layer between the source electrode and the drain electrode;
A second gate electrode formed on the second insulating film,
The first gate insulating film is characterized in that the capacitance between the channel layer and the first gate electrode gradually increases from the source electrode side to the drain electrode side. Field effect transistor. The field effect transistor of claim 1, wherein
The second gate insulating film is characterized in that the capacitance between the channel layer and the second gate electrode gradually decreases from the source electrode side toward the drain electrode side. Field effect transistor. The field effect transistor of claim 2, wherein
The field effect transistor according to claim 1, wherein the second gate insulating film is gradually thickened from the source electrode side toward the drain electrode side. The field effect transistor of claim 2, wherein
The dielectric constant of the second gate insulating film is gradually reduced from the source electrode side toward the drain electrode side. The field effect transistor according to any one of claims 1 to 4,
The field effect transistor according to claim 1, wherein the first gate insulating film is gradually thinned from the source electrode side toward the drain electrode side. The field effect transistor according to any one of claims 1 to 4,
The field effect transistor according to claim 1, wherein a dielectric constant of the first gate insulating film gradually increases from the source electrode side toward the drain electrode side. A channel layer made of Dirac electronic material,
A source electrode and a drain electrode connected to the channel layer;
A first gate insulating film formed on a first surface of the channel layer between the source electrode and the drain electrode;
A plurality of first gate electrodes formed on the first insulating film;
A second gate insulating film formed on a second surface of the channel layer between the source electrode and the drain electrode;
A field effect transistor comprising: a second gate electrode formed on the second insulating film. The field effect transistor of claim 7, wherein
The interval between the plurality of first gate electrodes is not less than the interval at which the influence of the fringe effect of the electric field induced by the voltage applied to the plurality of first gate electrodes does not occur and not more than the coherence length of electron conduction. A characteristic field effect transistor. The field effect transistor according to any one of claims 1 to 8,
The field effect transistor, wherein the Dirac electronic material is a phase change material in which a topological phase transition is caused by application of an electric field. The field effect transistor of claim 9,
The phase change material undergoes a phase transition from a normal insulator to a topological insulator by applying an electric field. The field effect transistor according to claim 9 or 10,
The channel layer has a stacked structure of a first crystal layer mainly composed of Te or Bi and a second crystal layer composed mainly of Te or Bi and having a composition different from that of the first crystal layer. A field effect transistor characterized by. The field effect transistor according to any one of claims 1 to 8,
The Dirac electronic material is a graphene nanoribbon or MoS ₂ .

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