CN114762117A

CN114762117A - Ferroelectric memory device containing two-dimensional charge carrier channel and method of fabricating the same

Info

Publication number: CN114762117A
Application number: CN202080082464.5A
Authority: CN
Inventors: P·拉布金; 东谷政昭; A·卡利佐夫
Original assignee: SanDisk Technologies LLC
Current assignee: SanDisk Technologies LLC
Priority date: 2020-02-24
Filing date: 2020-06-22
Publication date: 2022-07-15
Also published as: WO2021173176A1

Abstract

A ferroelectric memory device includes a two-dimensional electron gas channel, a gate electrode, and a ferroelectric element between the gate electrode and the two-dimensional electron gas channel.

Description

Ferroelectric memory device containing two-dimensional charge carrier channel and method of fabricating the same

RELATED APPLICATIONS

Priority is claimed in this application for U.S. non-provisional application No. 16/798,643 and U.S. non-provisional application No. 16/798,686, filed 24/2/2020, which are incorporated herein by reference in their entirety.

Technical Field

The present disclosure relates generally to the field of semiconductor devices, and in particular to ferroelectric memory devices employing two-dimensional charge carrier gas channels and methods of fabricating the same.

Background

A ferroelectric memory device is a memory device containing a ferroelectric material to store information. The ferroelectric material serves as the memory material of the memory device. Depending on the polarity of the electric field applied to the ferroelectric material, the dipole moment of the ferroelectric material is programmed in two different orientations (e.g., "up" or "down" polarization positions based on atomic positions in the crystal lattice, such as oxygen and/or metal atomic positions) to store information in the ferroelectric material. The different orientation of the dipole moment of the ferroelectric material is detectable by an electric field generated by the dipole moment of the ferroelectric material. For example, the orientation of the dipole moment can be detected by measuring the current flowing through a semiconductor channel disposed adjacent to the ferroelectric material in a field effect transistor ferroelectric memory device.

Disclosure of Invention

According to an aspect of the present disclosure, a ferroelectric memory device includes a two-dimensional electron gas channel, a gate electrode, and a ferroelectric element between the gate electrode and the two-dimensional electron gas channel.

According to another aspect of the present disclosure, there is provided a method of forming a single three-dimensional memory device, the method comprising: forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as or subsequently replaced by conductive layers; forming memory openings through the alternating stack; forming ferroelectric memory elements at a periphery of the memory opening at each level of the layer of spacer material; and forming a two-dimensional electron gas channel directly on the ferroelectric memory element in the memory opening.

According to yet another aspect of the present disclosure, there is provided a memory device including: at least one unit layer stack located above the substrate, wherein the unit layer stack includes a metal source layer, a channel level insulating layer, a metal drain layer, and a device isolation level insulating layer; and a plurality of memory openings extending vertically through the at least one cell layer stack; memory opening fill structures within a respective one of the plurality of memory openings, wherein each of the memory opening fill structures comprises a tubular ferroelectric dielectric layer and at least one two-dimensional cylindrical electron gas channel extending vertically between the metal source layer and the metal drain layer of the at least one cell layer stack.

According to still another aspect of the present disclosure, a memory device includes: a two-dimensional electron gas channel located on the substrate; source and drain regions at end portions of the two-dimensional electron gas channel; a two-dimensional Van der Waals ferroelectric material layer on the two-dimensional electron gas channel and comprising a material selected from CuInP₂S₆、a-In₂Se₃A ferroelectric material of g-SbP, g-SbAs, or a group IV monosulfide material having the formula MX, wherein M is selected from Ge, Sn or Pb, and X is selected from S, Se or Te; and at least one gate electrode over the two-dimensional layer of van der waals ferroelectric material.

According to another aspect of the present disclosure, a ferroelectric memory device includes: a channel; a gate electrode; a ferroelectric element between the gate electrode and the channel, wherein the ferroelectric element comprises a two-dimensional van der Waals ferroelectric material layer containing a material selected from CuInP₂S₆、a-In₂Se₃g-SbP, g-SbAs, or group IV monosulfide having the formula MXA material, wherein M is selected from Ge, Sn or Pb, and X is selected from S, Se or Te; and a first interface dielectric layer between the ferroelectric element and the gate electrode.

According to an aspect of the present disclosure, a ferroelectric memory device contains a two-dimensional semiconductor material layer having a band gap of at least 1.1eV and at least one of a thickness of 1 to 5 monolayers of atoms of a semiconductor material; or a two-dimensional charge carrier layer; a source contact contacting a first portion of the two-dimensional semiconductor material layer; a drain contact contacting a second portion of the two-dimensional semiconductor material layer; a ferroelectric memory element located between the source contact and the drain contact and adjacent to the first surface of the two-dimensional semiconductor material layer; and a conductive gate electrode positioned adjacent to the ferroelectric memory element.

According to another aspect of the present disclosure, a method of operating a ferroelectric memory device is provided. The polarization direction of the ferroelectric memory element may be programmed by applying a positive or negative bias voltage to the conductive gate electrode with respect to the two-dimensional layer of semiconductor material. The polarization direction of the ferroelectric memory element can be sensed by measuring the magnitude of the current between the source contact and the drain contact at a read voltage between the source contact and the drain contact.

According to yet another aspect of the present disclosure, a method of fabricating a ferroelectric memory device includes forming a two-dimensional semiconductor material layer; the method includes forming a ferroelectric memory element directly on a first surface of a two-dimensional layer of semiconductor material, forming a conductive gate electrode on the ferroelectric memory element, forming a source contact on a first end portion of the two-dimensional layer of semiconductor material, and forming a drain contact on a second end portion of the two-dimensional layer of semiconductor material.

Drawings

Fig. 1 is a perspective view of a metal-ferroelectric semiconductor structure.

Fig. 2A is a potential diagram of a first polarization state of the metal-ferroelectric semiconductor structure of fig. 1.

Fig. 2B is a potential diagram of a second polarization state of the metal-ferroelectric semiconductor structure of fig. 1.

Fig. 3 is a graph of electrostatic potential at an interface between a ferroelectric material portion and a metal portion as a function of ferroelectric thickness for a metal-ferroelectric semiconductor structure of two selected ferroelectric polarization densities.

Fig. 4 is a graph of conductivity as a function of Fermi (Fermi) level for a two-dimensional generic semiconductor material.

Fig. 5 is a graph of density per atom per electron volt state for pristine graphene and fluorinated graphene calculated within a tight association model.

Fig. 6 is a graph of conductivity as a function of fermi levels of pristine graphene and fluorinated graphene calculated within a tight junction model.

Fig. 7 is a first exemplary structure according to a first embodiment of the present disclosure.

Fig. 8 is a second exemplary structure according to a second embodiment of the present disclosure.

Fig. 9 is a third exemplary structure according to a third embodiment of the present disclosure.

Fig. 10A is a vertical cross-sectional view of a fourth exemplary structure according to a fourth embodiment of the present disclosure.

Fig. 10B is a schematic perspective view of the fourth exemplary structure of fig. 10A.

Fig. 11 shows the calculated density per atom per electron volt state of hexagonal boron nitride according to Density Function Theory (DFT) and a hybridization function.

Figure 12 shows the calculated density per atom per electron volt state of molybdenum disulfide according to Density Function Theory (DFT) and a hybridization function.

FIG. 13A is a graph of conductivity of hexagonal boron nitride as a function of polarization calculated in a tight junction model.

Fig. 13B is a graph of conductivity of fluorinated graphene as a function of polarization calculated in the tight junction model.

Figure 13C is a graph of conductivity of molybdenum disulfide as a function of polarization calculated in a tight junction model.

Figure 13D is a graph of conductivity of single germanium as a function of polarization calculated in a tight junction model.

Fig. 14 is a schematic diagram of a ferroelectric memory device according to an embodiment of the present disclosure.

Fig. 15 is a vertical cross-sectional view of a fifth example structure after forming a field effect transistor and a layer of semiconductor material, according to a fifth embodiment of the present disclosure.

Fig. 16 is a vertical cross-sectional view of a fifth example structure after forming an alternating stack of insulating layers and sacrificial material layers, according to a fifth embodiment of the present disclosure.

Fig. 17 is a vertical cross-sectional view of a fifth example structure after forming a retro-stepped dielectric material portion, according to a fifth embodiment of the present disclosure.

Fig. 18A is a vertical cross-sectional view of a fifth example structure after forming a reservoir opening and a support opening, according to a fifth embodiment of the present disclosure.

Fig. 18B is a top view of a fifth exemplary structure along the vertical plane a-a' of fig. 18A.

Fig. 19A-19J are sequential vertical cross-sectional views of a memory opening during formation of a first exemplary memory opening fill structure, according to a fifth embodiment of the present disclosure.

Fig. 19K is an alternative configuration of a first exemplary memory opening filling structure according to a fifth embodiment of the present disclosure.

Fig. 20A is a diagram illustrating a composition change in a tubular ferroelectric dielectric layer according to a fifth embodiment of the present disclosure.

Fig. 20B is a band diagram of a tubular ferroelectric dielectric layer during an erase operation according to a fifth embodiment of the present disclosure.

Fig. 20C is a band diagram of a tubular ferroelectric dielectric layer during a programming operation according to a fifth embodiment of the present disclosure.

Fig. 21A-21C are sequential vertical cross-sectional views of a memory opening during formation of a second exemplary memory opening fill structure, according to a sixth embodiment of the present disclosure.

Fig. 21D is an alternative embodiment of a second exemplary structure according to a sixth embodiment of the present disclosure.

Fig. 22A is a vertical cross-sectional view of a reservoir opening including a third example reservoir opening fill structure, according to a seventh embodiment of the present disclosure.

Fig. 22B is a vertical cross-sectional view of a reservoir opening including an alternative configuration of a third exemplary reservoir opening filling structure, according to a seventh embodiment of the present disclosure.

Figure 23 is a vertical cross-sectional view of a fourth example structure after forming a memory stack structure, according to an eighth embodiment of the present disclosure.

Figure 24A is a vertical cross-sectional view of a fourth example structure after forming backside trenches, according to an eighth embodiment of the present disclosure.

Fig. 24B is a partial perspective top view of the fourth exemplary structure of fig. 24A. Vertical plane a-a' is the plane of the vertical cross-sectional view of fig. 24A.

Fig. 25 is a vertical cross-sectional view of a fourth example structure after forming a backside recess, according to an embodiment of this disclosure.

Fig. 26A is a vertical cross-sectional view of a fourth exemplary structure after forming a conductive layer according to an eighth embodiment of the present disclosure.

Fig. 26B is an enlarged view of a region surrounding a memory opening fill structure in an alternative implementation of the fourth exemplary structure of fig. 26A.

Fig. 26C is an enlarged view of a region surrounding a memory opening fill structure in another alternative implementation of the fourth exemplary structure of fig. 26A.

Fig. 27 is a vertical cross-sectional view of a fourth example structure after formation of a backside contact via structure, according to an eighth embodiment of the present disclosure.

Fig. 28A is a vertical cross-sectional view of a fourth example structure after forming an additional contact via structure, according to an eighth embodiment of the present disclosure.

Fig. 28B is a partial perspective top view of the fourth exemplary structure of fig. 28A. Vertical plane a-a' is the plane of the vertical cross-sectional view of fig. 28A.

Fig. 29 is a vertical cross-sectional view of a fifth exemplary structure after forming multiple instances of cell layers including a source-level sacrificial layer, a channel-level insulating layer, a drain-level sacrificial layer, and a device isolation level insulating layer, and forming an insulating cap layer over a substrate, according to a ninth embodiment of the present disclosure.

Fig. 30 is a vertical cross-sectional view of a fifth example structure after forming stepped surfaces and retro-stepped dielectric material portions according to a ninth embodiment of the present disclosure.

Fig. 31 is a vertical cross-sectional view of a fifth example structure after forming an array of memory openings, according to a ninth embodiment of the present disclosure.

Fig. 32 is a vertical cross-sectional view of a fifth example structure after forming a channel level recess, according to a ninth embodiment of the present disclosure.

Figure 33 is a vertical cross-sectional view of a fifth exemplary structure after forming a two-dimensional electron gas channel, according to a ninth embodiment of the present disclosure.

Fig. 34A is a vertical cross-sectional view of a fifth example structure after forming a memory opening fill structure, according to a ninth embodiment of the present disclosure.

Fig. 34B is a vertical cross-sectional view of the fifth exemplary structure of fig. 34A.

Figure 35A is a vertical cross-sectional view of a fifth example structure after forming backside trenches, according to a ninth embodiment of the present disclosure.

Fig. 35B is a vertical cross-sectional view of the fifth exemplary structure of fig. 35A.

Fig. 36 is a vertical cross-sectional view of a fifth example structure after forming an active level backside recess, according to a ninth embodiment of the present disclosure.

Fig. 37 is a vertical cross-sectional view of a fifth example structure after formation of a source layer and a drain layer, according to a ninth embodiment of the present disclosure.

Fig. 38A is a vertical cross-sectional view of a fifth example structure after forming a contact via structure, according to a ninth embodiment of the present disclosure.

Fig. 38B is a vertical cross-sectional view of the fifth exemplary structure of fig. 38A.

Fig. 39 is a vertical cross-sectional view of a first configuration of a sixth example structure according to a tenth embodiment of the present disclosure.

Fig. 40 is a vertical cross-sectional view of a second configuration of a sixth example structure according to a tenth embodiment of the present disclosure.

Figure 41 is a vertical cross-sectional view of a third configuration of a sixth example structure according to a tenth embodiment of the present disclosure.

Fig. 42 is a vertical cross-sectional view of a fourth configuration of a sixth example structure according to a tenth embodiment of the present disclosure.

Figure 43 is a top down view of a fifth construction of a sixth example structure according to a tenth embodiment of the present disclosure.

Detailed Description

As discussed above, embodiments of the present disclosure are directed to ferroelectric memory devices employing two-dimensional electron gas ("2 DEG") channels, methods of operating the same, and methods of fabricating the same. In some embodiments, a two-dimensional semiconductor material layer comprising a thickness of 5 monolayers or less (such as 1 to 4 monolayers of atoms of a semiconductor material) comprises a 2DEG channel layer. The ferroelectric state of the ferroelectric memory element induces an order of magnitude change in conductivity in the channel. In some implementations, ferroelectric memory devices can be formed in a three-dimensional memory array having tubular ferroelectric dielectric layers.

The figures are not drawn to scale. Where a single instance of an element is shown, multiple instances of the element may be repeated unless explicitly described or otherwise clearly indicated to be absent from the repetition of the element. The same reference numerals refer to the same or similar elements. Elements having the same reference number are assumed to have the same material composition unless explicitly stated otherwise. Ordinal numbers such as "first," "second," and "third" are used merely to identify similar elements, and different ordinal numbers may be employed throughout the specification and claims of the present disclosure. The term "at least one" element is intended to mean all possibilities including single element possibilities and multiple element possibilities.

As used herein, a first element that is "on" a second element may be located on the outside of a surface of the second element or on the inside of the second element. As used herein, a first element is "directly" on a second element if there is physical contact between a surface of the first element and a surface of the second element. As used herein, a first element is "electrically connected" to a second element if there is a conductive path comprised of at least one conductive material between the first element and the second element. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.

As used herein, "layer" refers to a portion of a material that includes a region having a thickness. A layer may extend over the entirety of an underlying or overlying structure, or may have a range that is less than the range of an underlying or overlying structure. Furthermore, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the first continuous structure. For example, the layer may be positioned between the top surface and the bottom surface of the first continuous structure or between any pair of horizontal planes at the top surface and the bottom surface. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, may include one or more layers therein, or may have one or more layers thereon, above and/or below. As used herein, "stack of layers" refers to a stack of layers. As used herein, "line" or "line structure" refers to a layer having a primary direction of extension (i.e., having a direction that extends most along the layer).

As used herein, "field effect transistor" refers to any semiconductor device having a semiconductor channel through which current flows at a current density modulated by an external electric field. As used herein, "active region" refers to either a source region of a field effect transistor or a drain region of a field effect transistor. "top active region" refers to an active region of a field effect transistor that is located above another active region of the field effect transistor. "bottom active region" refers to an active region of a field effect transistor that is located below another active region of the field effect transistor.

As used herein, "semiconductor material" is meant to have a chemical composition of 1.0X 10^-6S/m to 1.0X 10⁵A material having an electrical conductivity in the range of S/m. As used herein, "semiconductor material" refers to a material having a resistivity of 1.0 x 10 in the absence of an electrical dopant therein^-6A material having an electrical conductivity in the range of S/m to 1.0S/m and capable of being produced when suitably doped with an electrical dopant having an electrical conductivity in the range of 1.0S/m to 1.0 x 10⁵A doping material of a conductivity in the range of S/m. As used herein, "electrical dopant" refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, "conductive material" means having a thickness of greater than 1.0 x 10 ⁵A material having an electrical conductivity of S/m. As used herein, "insulator material" or "dielectric material" is meant to have a thickness of less than 1.0X 10^-6A material having an electrical conductivity of S/m. As used herein, "heavily doped semiconductor material" refers to a material that is doped with an electrical dopant at a sufficiently high atomic concentration to be electrically conductive (i.e., having an atomic concentration greater than 1.0 x 10)⁵S/m conductivity). The "doped semiconductor material" may be a heavily doped semiconductor material, or may be a material including a dopant provided at 1.0 × 10^-6S/m to 1.0X 10⁵A semiconductor material of electrical dopant (i.e., p-type dopant and/or n-type dopant) at a concentration of conductivity in the range of S/m. "intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrical dopant. Thus, the semiconductor material may be semiconducting or conducting, and may be intrinsic or doped semiconductor material. The doped semiconductor material may be semiconducting or conducting, depending on the atomic concentration of the electrical dopant therein.

As used herein, "metallic material" refers to a conductive material including at least one metallic element therein. All conductivity measurements were performed under standard conditions. As used herein, "ferroelectric material" refers to any material that exhibits spontaneous electric polarization that can be reversed by application of an external electric field.

Referring to fig. 1, a metal-ferroelectric semiconductor structure according to an embodiment of the present disclosure is shown. In a ferroelectric memory device to be described hereinafter, a metal-ferroelectric semiconductor structure includes: including a metal portion that is a gate electrode 50, a ferroelectric material portion that includes a gate dielectric/ferroelectric memory element 20, and a semiconductor portion that includes a semiconductor channel 40.

Referring to fig. 2A and 2B, potential diagrams of polarization states of the metal-ferroelectric semiconductor structure of fig. 1 are shown. Fig. 2A shows a first polarization state of the metal-ferroelectric semiconductor structure of fig. 1, wherein the ferroelectric polarization vector P points in a positive polarization direction from the metal portion (such as the gate electrode 50) to the semiconductor portion (such as the semiconductor channel 40). In this case, positive ferroelectric charge is present on the sides of the ferroelectric material portion (such as gate dielectric 20) at the interface with the semiconductor portion (such as semiconductor channel 40), and negative ferroelectric charge is present on the sides of the ferroelectric material portion (such as gate dielectric 20) at the interface with the metal portion (such as gate electrode 50). The iron charge induces a screening charge within the metal portion and within the semiconductor portion. The screening charges are movable charges (such as electrons or holes) that reduce an electric field caused by the ferroelectric charges within the ferroelectric material portion. Positive screening charges are accumulated in a metal portion, such as the gate electrode 50, and negative screening charges are accumulated in a semiconductor portion, such as the semiconductor channel 40.

Fig. 2B shows a second polarization state of the metal-ferroelectric semiconductor structure of fig. 1, wherein the ferroelectric polarization vector P points in a direction from the semiconductor portion (such as semiconductor channel 40) to the metal portion (such as gate electrode 50). In this case, negative ferroelectric charge is present on the sides of the ferroelectric material portion (such as gate dielectric 20) at the interface with the semiconductor portion (such as semiconductor channel 40), and positive ferroelectric charge is present on the sides of the ferroelectric material portion (such as gate dielectric 20) at the interface with the metal portion (such as gate electrode 50). The iron charge induces a screening charge within the metallic portion and within the semiconductor portion. Negative-screening charge accumulates in metal portions, such as gate electrode 50, and positive-screening charge accumulates in semiconductor portions, such as semiconductor channel 40.

By switching parts of the ferroelectric materialTo control the screening potential at the interface between the ferroelectric material portion and the metal portion. Electrostatic potential V varying with distance x from the interface between the metal portion and the ferroelectric material portion_c(x) Decays with a characteristic decay distance, referred to as the Thomas-Fermi (Thomas-Fermi) screening length. If the x-axis is chosen such that the x-coordinate is positive in the ferroelectric-material part having the thickness d as well as in the semiconductor-material part, the electrostatic potential V in the metal part and the semiconductor-material part _c(x) Controlled by the following equation:

where λ is the thomas-fermi screening length within the respective material portion.

The screening length λ between the metal portion (such as the gate electrode 50) and the metal portion_lMuch thicker, and if the semiconductor material portion (such as semiconductor channel 40) is thinner, the electrostatic potential V of the semiconductor material portion_c(x) (i.e., x)>d) The solution of (a) is given by:

where d is the thickness of the ferroelectric material part, P is the ferroelectric polarization of the ferroelectric material part, ε₀Is the dielectric constant in vacuum,. epsilon.is the relative dielectric constant of the ferroelectric material portion (i.e., the ratio of the dielectric constant of the ferroelectric material portion to the dielectric constant in vacuum), and. lambda._lThomas-Fermi screening length, lambda, being the metal part_rIs the Tomas-Fermi screening length of the portion of semiconducting material, l is the thickness of the portion of semiconducting material, and λ'_lGiven by:

according to an aspect of the present disclosure, the electrostatic potential in the interface region of the semiconductor material portion near the ferroelectric material portion may be controlled by reversing the ferroelectric polarization within the ferroelectric material portion. For the positive polarization direction shown in fig. 2A, the screening charge brings the fermi level into the conduction band of the semiconductor material portion. For the negative polarization direction shown in fig. 2B, the screening charge moves the fermi level towards the bandgap. Therefore, the fermi level moves between a position in the semiconductor bandgap and a position in one of the bands (e.g., the conduction band or the valence band) by reversing the ferroelectric polarization direction, which results in a large difference between resistance (e.g., resistivity or resistance) states of the device.

According to an aspect of the disclosure, the semiconductor material portion comprises a two-dimensional semiconductor material providing a higher electrical conductivity in a two-dimensional plane parallel to an interface between the semiconductor material portion and the ferroelectric material portion. As used herein, a two-dimensional semiconductor material refers to a semiconductor material that is 1 to 5 monolayers thick (such as 2 to 3 monolayers of atoms of the semiconductor material), and/or that contains a two-dimensional charge carrier gas, such as a two-dimensional electron gas. In one embodiment, the two-dimensional semiconductor material has a lateral extent along one direction that induces quantum-mechanical modification of the band structure. In one embodiment, the two-dimensional semiconductor material may have a lateral direction of less than 10nm along one direction, which is referred to herein as the thickness direction of the two-dimensional semiconductor material.

According to an aspect of the disclosure, the semiconductor material portion comprises a two-dimensional semiconductor material layer having a thickness of 1 to 5 monolayers and having a band gap of at least 1eV (such as at least 1.15eV, for example 1.15eV to 5.65 eV). Alternatively, the two-dimensional semiconductor material layer may comprise a two-dimensional charge carrier gas (such as a two-dimensional electron gas) layer and a bandgap of at least 1eV (such as at least 1.15eV, for example 1.15eV to 5.65 eV). As used herein, a two-dimensional charge carrier gas refers to a collection of charge carriers in quantum confinement that provides enhanced conductivity in a direction perpendicular to the direction of quantum confinement. For example, the two-dimensional electron gas is a two-dimensional charge carrier gas.

In one embodiment, the semiconductor material portion comprises a two-dimensional semiconductor material selected from the group consisting of: hexagonal boron nitride having a band gap of 5.62eV, graphene fluoride having a band gap of 2.93eV, molybdenum disulphide having a band gap of 2.24eV and single germanium having a band gap of 1.16 eV. The list of possible candidates for the two-dimensional semiconductor material is not limited by the aforementioned materials.

FIG. 3 is an electrostatic potential V at the interface between a ferroelectric material portion and a metal portion_c(0) A plot of the change in ferroelectric thickness d of the metal-ferroelectric semiconductor structure of fig. 1 as calculated in a thomas-fermi model. According to this model, the electrostatic potential V at the interface between the ferroelectric material portion and the semiconductor portion_c(0) Given by:

the first curve 310 corresponds to a ferroelectric polarization of 20 μ C/cm²In the case of (2), the relative dielectric constant of the ferroelectric material portion is 90, the thomas-fermi screening length of the metal portion is 0.2nm, and the thomas-fermi screening length of the semiconductor material portion is 0.2 nm. The second curve 320 corresponds to a ferroelectric polarization of 40 μ C/cm²In the case of (2), the relative dielectric constant of the ferroelectric material portion is 90, the thomas-fermi screening length of the metal portion is 0.2nm, and the thomas-fermi screening length of the semiconductor material portion is 0.2 nm. An electrostatic potential of more than 1.0V and/or more than 1.5V and/or more than 2.0V can be generated at the interface between the ferroelectric material portion and the metal portion by the ferroelectric polarization effect.

Fig. 4 is a graph of conductivity as a function of fermi level for a hypothetical two-dimensional semiconductor material (e.g., for a single layer of semiconductor material). For the purposes of the calculations in fig. 4, a simple model based on a two-band tightly-bonded hamilton (Hamiltonian) two-dimensional semiconductor material is employed. When such a two-dimensional semiconductor material is used for the semiconductor material portion of the device of fig. 1, it is possible to switch the state of the two-dimensional semiconductor material between a conductive state and an insulating state by reversing the direction of ferroelectric polarization, as illustrated in fig. 2A and 2B. In other words, the shift in fermi levels in the device of fig. 1 may be sufficient to provide two distinct resistance states, such as a higher resistance state and a lower resistance state, which may be, for example, a conductive state and an insulating state.

In accordance with embodiments of the present disclosure, the functional dependence of the conductivity on the fermi level shown in fig. 4 may be physically embodied as any suitable two-dimensional semiconductor material, such as hexagonal boron nitride, fluorinated graphene, molybdenum disulfide, monogermanium, or the like.

Table 1 below shows calculated values of band gaps and conduction band in-situ energies for various materials that may be employed in ferroelectric memory devices of the present disclosure. Band gap values were obtained from first principle electronic structure calculations based on hybridization functions, and fit to the tightly bound potential energies to reproduce the calculated band structures.

Table 1: band gap and conduction band in-situ energy of two-dimensional semiconductor material

Two-dimensional semiconductor material	Band gap (eV)	Conduction band potential energy (eV)
			Hexagonal BN	5.62	6.81
MoS₂	2.24	5.12
			Fluorinated graphene	2.93	5.465
Single germanium	1.16	4.58

A list of other suitable highly stable two-dimensional semiconductor materials taken from the following database (https:// cmrdb. fysik. dtu. dk/c2 db/. DFT is known to underestimate the bandgap value and therefore the actual bandgap is expected to be larger.

Table 2: bandgap of additional two-dimensional semiconductor material

Pristine graphene (i.e., graphene without defects or dopants) is an electrical conductor lacking a band gap, while fluorinated graphene is a semiconductor with a band gap. Fig. 5 is a graph of density of states per electron volt per carbon atom of pristine graphene and fluorinated graphene. For the purpose of calculating the density per energy state, a tight junction model is employed. Curve 510 represents the density per carbon atom per electron volt state of the pristine graphene. Curve 520 represents the density per carbon atom per electron volt state of the fluorinated graphene. Pristine graphene provides a state of non-zero density at all energies except zero, and therefore does not provide a voltage at which pristine graphene becomes insulating. The fluorinated graphene provides an energy band with a density of states of zero, and thus provides a voltage range in which the fluorinated graphene acts as an insulating material.

Referring to fig. 6, the calculated conductivities of pristine and fluorinated graphene are plotted as a function of fermi energy. Curve 610 represents the conductivity of pristine graphene and curve 620 represents the conductivity of fluorinated graphene. The fluorinated graphene provides an energy range in which the conductivity is negligible, and acts as an insulating material for a fermi level of 0.5eV or less. In contrast, pristine graphene does not provide an energy range in which pristine graphene can act as an insulating material.

The atomic percent of fluorine in the fluorinated graphene may be in a range of 0.1% to 60%, such as 0.5% to 50%, including a range of 0.1% to 0%. Thus, the fluorinated graphene may include, but is not limited to, fluorinated graphene having a ratio of carbon to fluorine atoms of about 1: 1. The position and width of an energy band in which the density of states in the fluorinated graphene is zero vary with the atomic concentration of fluorine atoms within the fluorinated graphene.

Thus, switching between an insulating state and a conducting state within the device of fig. 1 is possible for a fluorinated graphene semiconductor material acting as part of the semiconductor material. Other semiconductor materials with sufficient band gap, such as molybdenum disulfide, hexagonal boron nitride, or mono germanium, may be employed in place of the fluorinated graphene in the device of fig. 1.

Fig. 7 shows a first exemplary structure 180 according to a first embodiment of the present disclosure. The first ferroelectric memory device 180 includes a transistor 95 including a semiconductor channel 40. The semiconductor channel 40 may be configured to provide a two-dimensional charge carrier layer (such as a 2DEG layer) or a semiconductor material selected from fluorinated graphene, hexagonal boron nitride, molybdenum disulfide, monogermanium, or similar two-dimensional materials with a sufficient band gap. The semiconductor channel 40 may consist of only the two-dimensional charge carrier layer, or may include additional semiconductor material in addition to the two-dimensional charge carrier layer. The two-dimensional charge carrier layer may lie in a two-dimensional Euclidean plane. In one embodiment, the semiconductor channel 40 may have a thickness in the range of 0.3nm to 10nm, such as in the range of 0.6nm to 5 nm. The two-dimensional charge carrier layer serves as a channel within the transistor 95 (e.g., ferroelectric memory cell) of the first ferroelectric memory device 180.

The ferroelectric memory element 21 is positioned adjacent to the semiconductor channel 40, such as on a surface of the semiconductor channel (i.e., on a surface of the two-dimensional charge carrier layer). The ferroelectric memory element 21 acts as the gate dielectric 20 within the transistor 95 of the first ferroelectric memory device 180. The ferroelectric memory element 21 is in contact with a first surface of the semiconductor channel 40. The ferroelectric memory element 21 comprises and/or consists essentially of: at least one ferroelectric material, such as barium titanate (such as BaTiO) ₃(ii) a BT), colemanite (such as Ca)₂B₆O₁₁·5H₂O), bismuth titanates (such as Bi)₁₂TiO₂₀、Bi ₄Ti₃O₁₂Or Bi₂Ti₂O₇) Europium barium titanate, ferroelectric polymers, germanium telluride, potassium magnesium anhydrous alum (such as M)₂M'₂(SO₄)₃Where M is a monovalent metal and M' is a divalent metal), lead scandium tantalum (such as Pb (Sc)_xTa_1-x)O₃) Lead titanate (such as PbTiO)₃(ii) a PT), lead zirconate titanate (such as Pb (Zr, Ti) O₃(ii) a PZT), lithium niobate (such as LiNbO)₃；LN)、(LaAlO₃) Polyvinylidene fluoride (CH), polyvinylidene fluoride (CH)₂CF₂)_nPotassium niobate (such as KNbO)₃) Sodium tartrate (such as KNaC)₄H₄O₆·4H₂O), potassium titanyl phosphate (such as KO)₅PTi), bismuth sodium titanate (such as Na)_0.5Bi_0.5TiO₃Or Bi_0.5Na_0.5TiO₃) Lithium tantalate (such as LiTaO)₃(LT)), lead lanthanum titanate (such as (Pb, La) TiO)₃(PLT)), lead lanthanum zirconium titanates (such as (Pb, La) (Zr, Ti) O₃(PLZT)), ammonium dihydrogen phosphate (such as NH)₄H₂PO₄(ADP)) or monopotassium phosphate (such as KH₂PO₄(KDP)). In one implementation, ferroelectric memory element 21 comprises and/or consists essentially of a ferroelectric dielectric material.

The front side conductive gate electrode 51 is located directly on the ferroelectric memory element 21 on the opposite side of the semiconductor channel 40. The front side conductive gate electrode 51 serves as the gate electrode 50 of the transistor 95 of the first ferroelectric memory device 180. The conductive gate electrode 51 is in contact with the ferroelectric memory element 21. The conductive gate electrode 51 may comprise and/or consist essentially of a metallic material, such as an elemental metal (Ti, Ta or W), an intermetallic alloy of at least two elemental metals, a metal semiconductor compound (such as a metal silicide), or a conductive metal alloy of at least one elemental metal (such as Ti, Ta, W) and a non-metallic element (such as nitrogen and/or oxygen, such as TiN or WN).

The source contact 42 contacts a first portion of the semiconductor channel 40 and the drain contact 44 contacts a second portion of the semiconductor channel. Ferroelectric memory element 21 is located between source contact 42 and drain contact 44. The source contact 42 and the drain contact 44 may comprise and/or consist essentially of respective metal contact materials. The metal contact material may be a metal semiconductor compound, a conductive metal nitride, an elemental metal, or an intermetallic alloy material. In one implementation, the metallic materials that may be used for the conductive gate electrode 51 may also be used for the source contact 42 and the drain contact 44.

In one embodiment, the two-dimensional charge carrier layer is located within 10nm of a two-dimensional euclidean plane including the interface between the semiconductor channel 40 and the ferroelectric memory element 21.

For example, the transistor 95 of the first exemplary structure 180 may be formed by forming a semiconductor channel 40 over the substrate 10, by forming the ferroelectric memory element 21 directly on a first surface over the semiconductor channel 40, by forming the conductive gate electrode 51 on the ferroelectric memory element 21, by forming the source contact 42 on a first portion of the semiconductor channel 40, and by forming the drain contact 44 on a second portion of the semiconductor channel 40. The substrate 10 has a planar top surface 11 contacting the bottom surface of the semiconductor channel 40. In the implementation shown in fig. 7, the direction between the semiconductor channel 40 and the conductive gate electrode 51 is perpendicular to the planar top surface 11 of the substrate 10. Alternatively, in the implementation shown in fig. 8, the transistor 95 may be rotated 90 degrees relative to the transistor 95 shown in fig. 7 such that the direction between the semiconductor channel 40 and the conductive gate electrode 51 is parallel to the plane of the planar top surface 11 of the substrate 10. The substrate 10 may comprise any suitable supporting substrate, such as a semiconductor wafer, an insulating substrate, or a conductive substrate containing an insulating layer over its planar top surface 11.

During programming, a variable gate bias voltage V may be applied with respect to the semiconductor channel 40_gIs applied to the conductive gate electrode 51 to program the polarization of the ferroelectric memory element 21. During sensing, a source-drain bias voltage is applied between (e.g., across) source contact 42 and drain contact 44, and by applying a gate sense bias voltage to conductive gate electrode 51. The sensing circuitry 584 may measure the source-drain current while applying a source-drain bias voltage between (e.g., across) the source contact 42 and the drain contact 44.

Referring to fig. 8, a second exemplary structure 180 according to a second embodiment of the present disclosure may be derived from the first exemplary structure 180 of fig. 7 by providing a backside ferroelectric memory element 22 in contact with a second surface of the semiconductor channel 40. The backside ferroelectric memory element 22 is an additional ferroelectric material portion that acts as an additional gate dielectric 20. The backside ferroelectric memory element 22 is located on a second surface of the semiconductor channel 40, which is parallel to the first surface of the semiconductor channel 40 and located on an opposite side of the first surface of the semiconductor channel 40. Backside ferroelectric memory elements 22 may have the same thickness as ferroelectric memory elements 21 and may comprise any ferroelectric material that may be used for ferroelectric memory elements 21.

A conductive backside gate electrode 52 is disposed on the backside ferroelectric memory element 22. Conductive backside gate electrode 52 may be in contact with backside ferroelectric memory element 22. The conductive backside gate dielectric 52 can include any material that can be used for the conductive gate electrode 51. A conductive path connects the conductive backside gate electrode with the conductive gate electrode, electrically shorting the conductive backside gate electrode 52 to the conductive gate electrode 51.

In one implementation, the polarization of the ferroelectric memory elements 21 and the polarization of the backside ferroelectric memory elements 22 may be directed in opposite directions. Thus, the polarization of the ferroelectric memory element 21 and the polarization of the backside ferroelectric memory element 22 may be directed towards the semiconductor channel 40 in the first ferroelectric memory state, and the polarization of the ferroelectric memory element 21 and the polarization of the backside ferroelectric memory element 22 may be directed away from the semiconductor channel 40 in the second ferroelectric memory state. Thus, positive ferroelectric charge is present in the ferroelectric memory element 21 and the backside ferroelectric memory element 22 near the interface with the semiconductor channel 40 in the first ferroelectric memory state inducing negative screening charges (mobile electrons) in the two-dimensional charge carrier layer near the interface with the ferroelectric memory element 21 and the backside ferroelectric memory element 22. Alternatively, if a semiconductor layer is used instead of a two-dimensional charge carrier layer, the induced charge will serve to shift the fermi energy and change the conductive state of the semiconductor layer. Likewise, negative ferroelectric charge is present in the ferroelectric memory element 21 and the backside ferroelectric memory element 22 proximate the interface with the semiconductor channel 40 in the second ferroelectric memory state that induces positive screening charge (holes, i.e., absence of electrons) in the two-dimensional charge carrier layer proximate the interface with the ferroelectric memory element 21 and the backside ferroelectric memory element 22. When a voltage is applied to the front side conductive gate electrode 51, the second exemplary structure 180 may be operated by applying the same voltage (e.g., same polarity voltage pulse) to the conductive backside gate electrode 52.

The thickness of the semiconductor channel 40 in the second exemplary structure 180 may be the same as the thickness of the semiconductor channel in the first exemplary structure 180. Alternatively, the thickness of the semiconductor channel 40 in the second exemplary structure 180 may be in the range of 1.0 times the thickness of the semiconductor channel 40 in the first exemplary structure 180 to 2.0 times the thickness of the semiconductor channel in the first exemplary structure 180. The increased thickness window of the semiconductor channel 40 in the second exemplary structure 180 is due to a double gate configuration, in which the screening charge is additively induced by two different ferroelectric polarizations.

The transistor 95 of the second exemplary structure 180 can be formed by modifying the method used to form the transistor 95 of the first exemplary structure 180. In addition to the processing steps used to form the various components of the first exemplary structure 180, a backside ferroelectric memory element 22 may be formed on the second surface of the semiconductor channel 40, and a conductive backside gate electrode 52 may be formed on the backside ferroelectric memory element 22.

In one embodiment, the transistor 95 of the second exemplary structure 180 may be supported by the substrate 10 having a planar top surface 11 that is perpendicular to the plane of the interface between the semiconductor channel 40 and the ferroelectric memory element 21 and parallel to the direction of current flow in the semiconductor channel 40 (i.e., the direction between the source contact 42 and the drain contact 44) during the sensing operation.

Alternatively, the transistor 95 shown in fig. 8 may be rotated 90 degrees to have a similar configuration to that shown in fig. 7. In this alternative configuration, a conductive backside gate electrode 52 is formed over the substrate 10, a backside ferroelectric memory element 22 is formed over the conductive backside gate electrode 52, a semiconductor channel 40 is formed over the backside ferroelectric memory element 22, a ferroelectric memory element 21, a source contact 42, and a drain contact 44 are formed over the semiconductor channel 40, and a front side conductive gate electrode 51 is formed over the ferroelectric memory element 21.

Referring to fig. 9, a transistor 95 of a third exemplary structure that may be derived from the first exemplary structure 180 by forming the backside contact electrode 53 directly on the second surface of the semiconductor channel 40 is shown, according to an embodiment of the present disclosure. A two-dimensional semiconductor material layer 40G within the semiconductor channel 40 is explicitly shown. The two-dimensional semiconductor material layer 40G described above may include the entire semiconductor channel 40 or only a portion of the semiconductor channel 40. The two-dimensional semiconductor material layer 40G may have a bandgap of at least 1.1eV, may comprise a thickness of 1 to 5 monolayers of atoms of the semiconductor material, and/or may comprise a two-dimensional charge carrier layer. The second surface of the semiconductor channel 40 is located on an opposite side of the first surface of the semiconductor channel 40. Accordingly, the backside contact electrode 53 may be in contact with the second surface of the semiconductor channel 40. The backside contact electrode 53 may apply a backside bias voltage to the semiconductor channel 40 during programming of the ferroelectric polarization of the ferroelectric memory element 21. Optionally, a front gate contact 81 and/or a back gate contact 83 may be formed on the conductive gate electrode 51 and on the backside contact electrode 53, respectively, to facilitate application of a bias voltage employed during operation of the transistor 95 of the third exemplary structure. In alternative embodiments, layer 51 and/or layer 53 shown in fig. 9 may comprise a gate insulating layer, and contact 81 and/or contact 83 may comprise a front conductive gate electrode and a back contact electrode (e.g., a back gate), respectively.

Referring to fig. 10A and 10B, a transistor 95 of a fourth exemplary structure according to a fourth embodiment of the present disclosure is shown. In the transistor 95 of the fourth exemplary structure, the ferroelectric memory element 20 and/or the gate electrode 50 may have a tubular configuration surrounding the semiconductor channel 40. In other words, gate electrode 50 may be a wrapped-gate electrode 54 wrapped around ferroelectric memory element 20, which may be wrapped around ferroelectric memory element 23. The wrapped ferroelectric memory element 23 wraps around (i.e., wraps around) the semiconductor channel 40.

In this embodiment, the semiconductor channel 40 may be a vertical column or a vertical shell surrounding a vertical column that extends longitudinally perpendicular to the planar top surface 11 of the substrate 10, as shown in fig. 10B. The wrapped ferroelectric memory element 23 may be an inner shell wrapped around (i.e., wrapped around) the semiconductor channel 40. A wrap gate electrode 54 wraps around a middle portion of the wrap ferroelectric memory element 23. Source and drain contacts (42,44) contact opposite ends of the semiconductor channel 40 on opposite sides of the wrapped-around gate electrode 54. The source and drain contacts (42,44) may also wrap around the semiconductor channel 40, or they may contact only a portion of the outer perimeter of the semiconductor channel 40.

In general, the various ferroelectric memory devices 180 of embodiments of the present disclosure may operate by programming the polarization direction of the ferroelectric memory element 21, by applying a positive or negative bias voltage to the conductive gate electrode 51 relative to the semiconductor channel 40, and by sensing the polarization direction of the ferroelectric memory element 21 by sensing the magnitude of the current between the source contact 42 and the drain contact 44 while applying a read voltage (i.e., measuring the bias voltage) between the source contact 42 and the drain contact 44. If a backside ferroelectric memory element 22 is included, the ferroelectric polarization direction of the backside ferroelectric memory element 22 is opposite to the ferroelectric polarization direction of the ferroelectric memory element 21. The thickness and/or material composition of the backside ferroelectric memory element 22 may be the same as or different from the thickness and/or material composition of the ferroelectric memory element 21. In other words, the polarizations of the ferroelectric memory element 21 and the backside ferroelectric memory element 22 are anti-parallel to each other and are simultaneously flipped during programming.

If a conductive back-side gate electrode 52 is included, the voltage applied to the conductive back-side gate electrode 52 may be the same as the voltage applied to the front-side conductive gate electrode 51. A read voltage may be applied to the conductive gate electrode 51 while sensing the polarization direction of the ferroelectric memory element 21, and optionally the polarization direction of the backside ferroelectric memory element 22.

The devices of the embodiments of the present disclosure provide advantages over ferroelectric raw graphene memory elements based on tunneling resistance (TER) which has poor polarization retention and requires a thicker ferroelectric barrier to stabilize polarization. However, a thicker barrier results in lower tunneling current and, therefore, greatly reduces the signal (e.g., read current) in TER-based devices. In contrast, the read current does not flow through the ferroelectric material in the devices of embodiments of the present disclosure. Thus, thicker ferroelectric layers can be used in devices of embodiments of the present disclosure without reducing read current, and the problem of polarization retention is reduced or overcome in devices of embodiments of the present disclosure, as compared to prior art TER-based devices.

Without wishing to be bound by a particular theory and to demonstrate the advantages of the devices of the embodiments of the present disclosure, the inventors calculated the ferroelectric polarization controlled on-off ratio over the band gap of the semiconductor in finite size nanostructures at room temperature. The inventors developed quantum mechanical calculations based on the electrical conductivity of ballistic electron transport through a limited size semiconductor and two metal contacts attached to a ferroelectric material. The inventors' calculations are based on the green functional form within a two-band tight-coupling Hamiltonian model. In contrast, the first principle electronic structure calculates the density and band gap to obtain the states of the two-dimensional semiconductor material.

In particular, the structure of FIG. 1 was modeled using rectangular device dimensions (i.e., the area of each interface between adjacent layers) of 10nm by 5 nm. The thickness d of the ferroelectric material portion is 5nm and the distance between the ferroelectric material portion and each metal contact is 1 nm. The electrostatic potential in the portion of semiconductor material underlying the portion of ferroelectric material is controlled by reversing the ferroelectric polarization.

The results of the simulation by the inventors are shown in fig. 11, fig. 12, and fig. 13A to 13D. The accuracy of the conductivity simulation is limited by the numerical precision. Less than 10^-2(Ohm·m)^-1Is outside the range of reliable numerical accuracy and, therefore, the calculation is limited to the range of ferroelectric polarization, which results in a conductivity value of at least 10-²(Ohm·m)-¹。

Referring to fig. 11, the calculated density per atom per electron volt state for hexagonal boron nitride is shown. This calculation is based on Density Function Theory (DFT) and a hybridization function.

Referring to fig. 12, the calculated density per atom per electron volt state for molybdenum disulfide is shown. This calculation is based on Density Function Theory (DFT) and a hybridization function.

Fig. 13A-13D show calculated conductivities (at 10) for the transistor 95 of the ferroelectric memory device of embodiments of the present disclosure at room temperature (20 degrees Celsius (Celsius)) ⁷In units of Ohm m) as a function of ferroelectric polarization. Fig. 13A shows the calculated conductivity for the case where the ferroelectric memory element is composed of hexagonal boron nitride. Fig. 13B shows the calculated conductivity for the case where the ferroelectric memory element is composed of fluorinated graphene. FIG. 13C shows a memory cell for a ferroelectric memory thereinCalculated conductivity for the case where the reservoir element consists of molybdenum disilicide. Fig. 13D shows the calculated conductivity for the case where the ferroelectric memory element is comprised of a single germanium.

Fig. 13A-13D show that the conductivity of all semiconductor channels of embodiments of the present disclosure increases (or decreases) exponentially with ferroelectric polarization for the ferroelectric polarization in the positive (or negative) direction. This allows fitting the calculated conductivity σ (P) to a fitting function comprising the ferroelectric polarization P as a variable. Furthermore, the ON/OFF ratio ON/OFF (i.e. the ratio of the conductivity in the ON state to the conductivity in the OFF state) can be fitted to have another variable P_maxThe variable is the maximum of the ferroelectric polarization required to push the fermi level of the two-dimensional semiconductor into the conduction band. The functional form of σ (P) and ON/OFF is given by:

σ(P)＝σ₀e^aPand are each selected from

Wherein sigma₀σ (P ═ 0) is the conductivity of the semiconductor channel for the paraelectric case. Table 3 lists the best fit values for the fitting parameters for σ (P) and ON/OFF.

Ferroelectric material	Optimum value of a in cm²/. mu.C is unit)	P_max(in μ C/cm)²Is a unit)
			Hexagonal BN	0.61	75
MoSi₂	0.49	30
			Fluorinated graphene	0.50	40
Single germanium	0.44	10

While the defect state may limit the value of the ON/OFF ratio in practice, various two-dimensional semiconductor materials provide a generally higher ON/OFF ratio. Simulations have shown that higher ON/OFF ratios are possible with wider band gap two-dimensional semiconductor materials, and that thicker ferroelectric materials can be used in combination with such two-dimensional semiconductor materials. The higher operating voltage is expected to increase the thickness of the ferroelectric material in the ferroelectric memory device 180 of embodiments of the present disclosure.

According to an aspect of the present disclosure, a ferroelectric memory array may include an array of memory cells (e.g., transistors) 95 of an implementation of the present disclosure. Referring to fig. 14, a schematic diagram of a ferroelectric memory array including transistors 95 in an array configuration is shown. The ferroelectric memory array may be configured as a random access memory device 501. As used herein, "random access memory device" refers to a memory device that includes memory cells that allow random access, i.e., access to any selected memory cell pursuant to a command for reading the contents of the selected memory cell.

The random access memory device 501 of the present disclosure includes a memory array region 550 containing an array of respective ferroelectric memory cells 180 located at the intersections of word lines (which may include first electrically conductive lines 30 as shown or second electrically conductive lines 90 in an alternative configuration) and bit lines (which may include second electrically conductive lines 90 as shown or first electrically conductive lines 30 in an alternative configuration). For example, word line 30 may be electrically connected to and/or may comprise gate electrode 50 of transistor 95 in the array, while bit line 90 may be electrically connected to and/or may comprise a source or drain contact (42,44) of transistor 95 in the array.

The random access memory device 501 may also contain a row decoder 560 connected to word lines, sensing circuitry 570 (e.g., sense amplifiers and other bit line control circuitry) connected to bit lines, a column decoder 580 connected to bit lines, and a data buffer 590 connected to the sensing circuitry. Multiple instances of ferroelectric memory cells (e.g., ferroelectric memory transistors) 95 are provided in an array configuration forming a random access memory device 501. As such, each of ferroelectric memory cells 95 may be a two-terminal device including a respective first electrode and a respective second electrode. It should be noted that the location and interconnection of elements is illustrative and that elements may be arranged in different configurations. Furthermore, the ferroelectric memory cell 95 may be fabricated as a discrete device, i.e., a single isolation device.

Embodiments of the present disclosure provide a ferroelectric controlled conductivity non-volatile memory element based on a two-dimensional semiconductor material or a two-dimensional charge carrier gas layer, such as 2DEG layer 40G. Information can be written and stored by applying electrical pulses that reverse the ferroelectric polarization and in turn induce surface charges in the semiconductor or in the two-dimensional charge carrier layer. Information can be read by measuring the resistance of a semiconductor channel comprising a two-dimensional charge carrier layer.

The devices of embodiments of the present disclosure provide a significant increase in the difference in resistance of the two-dimensional semiconductor material layer, which may have a bandgap of at least 1.1eV, by replacing gapless pristine graphene (i.e., a bandgap of zero) with the two-dimensional semiconductor material layer, as compared to previously known three-terminal ferroelectric-graphene structures. The device of embodiments of the present disclosure may greatly improve the stability of ferroelectric polarization compared to previously known two-terminal vertical tunnel junction devices because the thickness of the ferroelectric material portion may be increased without signal loss. The devices of embodiments of the present disclosure are non-volatile memory devices capable of non-volatile storage of information, which is not provided by High Electron Mobility Transistors (HEMTs) or hetero-junction field effect transistors (HFETs) known in the art. The device of embodiments of the present disclosure is capable of low power sensing because the in-plane geometry allows for low current operation during the sensing step.

Referring to fig. 15, a fifth exemplary structure according to a fifth embodiment of the present disclosure is shown, which may be used, for example, to fabricate a device structure containing a vertical NAND memory device. A fifth exemplary structure includes a substrate, which may be a semiconductor substrate. The substrate may include a substrate semiconductor layer 109. The substrate semiconductor layer 109 is a layer of semiconductor material and may include at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, and/or other semiconductor materials known in the art. The substrate may have a major surface 7, which may be, for example, the topmost surface of the substrate semiconductor layer 109. The main surface 7 may be a semiconductor surface. In one embodiment, the major surface 7 may be a monocrystalline semiconductor (e.g., silicon) surface. The substrate may be, for example, a single crystal silicon wafer. Optionally, at least one doped well (not explicitly shown) may be formed within the substrate semiconductor layer 109.

At least one semiconductor device 700 of the peripheral circuitry may be formed on a portion of the substrate semiconductor layer 109. The at least one semiconductor device may comprise a field effect transistor, for example. For example, the at least one shallow trench isolation structure 120 may be formed by etching a portion of the substrate semiconductor layer 109 and depositing a dielectric material therein. A gate dielectric layer, at least one gate conductor layer, and a gate capping dielectric layer may be formed over the substrate semiconductor layer 109, and may then be patterned to form at least one gate structure (150,152,154,158), each of which may include a gate dielectric 150, a gate electrode (152,154), and a gate capping dielectric. The gate electrode (152,154) may comprise a stack of a first gate electrode portion 152 and a second gate electrode portion 154. At least one gate spacer 156 may be formed around the at least one gate structure (150,152,154,158) by depositing and anisotropically etching a conformal dielectric layer. The active region 130 may be formed in an upper portion of the substrate semiconductor layer 109, for example, by introducing ions that use the at least one gate structure (150,152,154,158) as a mask structure. Additional masks may be employed as desired. The active region 130 may include a source region and a drain region of a field effect transistor. First dielectric liner 161 and second dielectric liner 162 may optionally be formed. Each of the first and second dielectric pads (161,162) may include a silicon oxide layer, a silicon nitride layer, and/or a dielectric metal oxide layer. In an illustrative example, the first dielectric liner 161 may be a silicon oxide layer and the second dielectric liner 162 may be a silicon nitride layer. At least one semiconductor device of the peripheral circuitry may contain a driver circuit for a memory device to be subsequently formed, which may include at least one NAND device.

A dielectric material, such as silicon oxide, may be deposited over the at least one semiconductor device and may then be planarized to form a planarized dielectric layer 170. In one embodiment, the planarized top surface of the planarized dielectric layer 170 may be coplanar with the top surfaces of the dielectric pads (161, 162). Subsequently, the planarizing dielectric layer 170 and the dielectric liner (161,162) can be removed from a region to physically expose the top surface of the substrate semiconductor layer 109.

An optional semiconductor material layer 110 may be formed on the top surface of the substrate semiconductor layer 109 by depositing a single crystal semiconductor material, such as by selective epitaxy. The deposited semiconductor material may be the same as or different from the semiconductor material of the substrate semiconductor layer 109. The deposited semiconductor material may be any material that may be used for the substrate semiconductor layer 109 as described above. The single crystal semiconductor material of the semiconductor material layer 110 may be epitaxially aligned with the single crystal structure of the substrate semiconductor layer 109. Portions of the deposited semiconductor material above the top surface of the planarization dielectric layer 170 may be removed, for example, by Chemical Mechanical Planarization (CMP). In this case, the semiconductor material layer 110 may have a top surface that is coplanar with a top surface of the planarization dielectric layer 170. The semiconductor material layer 110 may be doped with a p-type dopant or an n-type dopant. The doping type of the semiconductor material layer 110 is referred to herein as a first conductivity type. In the case where the semiconductor material layer 110 is not formed, the substrate semiconductor layer may be doped with a p-type dopant or an n-type dopant, and the doping type of the substrate semiconductor layer 109 is referred to as a first conductive type. In one embodiment, the first conductivity type may be p-type.

Referring to fig. 16, an alternating stack of insulating layers 132 and spacer material layers may be formed over a substrate, which may include an optional semiconductor material layer 110 and a substrate semiconductor layer 109. The layer of spacer material may be formed as a conductive layer, or may be formed as a layer of sacrificial material 142 that is subsequently replaced by a conductive layer.

In one embodiment, a stack of alternating layers of a plurality of first material (which may be insulating layers 132) and second material (which are layers of spacer material located between the layers of first material 132, and which may be sacrificial material layers 142) is formed over the top surface of the substrate. For example, a stack of alternating pluralities of first and second material layers may be formed on the top surface of the semiconductor material layer 110. As used herein, "layer of material" refers to a layer comprising material throughout its entirety. As used herein, the alternating pluralities of fifth elements and second elements refers to structures in which instances of the fifth elements and instances of the second elements alternate. Each instance of the fifth element that is not an end element of the alternating plurality of elements is adjoined on both sides by two instances of the second element, and each instance of the second element that is not an end element of the alternating plurality of elements is adjoined on both ends by two instances of the fifth element. The fifth elements may have the same thickness therebetween, or may have different thicknesses. The second elements may have the same thickness therebetween, or may have different thicknesses. The alternating plurality of first material layers and second material layers may begin with an instance of a first material layer or an instance of a second material layer and may end with an instance of a first material layer or an instance of a second material layer. In one embodiment, the instances of the fifth element and the instances of the second element may form a unit that repeats periodically within alternating multiple elements.

Each first material layer includes a first material, and each second material layer includes a second material different from the first material. In one embodiment, each first material layer may be an insulating layer 132 and each second material layer may be a sacrificial material layer. In this case, the stack may include a plurality of insulating layers 132 and sacrificial material layers 142 alternating, and constitute a prototype stack including alternating layers of insulating layers 132 and sacrificial material layers 142. As used herein, a "prototype" structure or "in-process" structure refers to a transient structure that is subsequently modified in the shape or composition of at least one component therein.

The stack of alternating layers is referred to herein as an alternating stack (132, 142). In one embodiment, the alternating stack (132,142) may include insulating layers 132 composed of a first material and sacrificial material layers 142 composed of a second material that is different than the material of the insulating layers 132. The first material of the insulating layer 132 may be at least one insulating material. As such, each insulating layer 132 may be a layer of insulating material. Insulating materials that may be used for the insulating layer 132 include, but are not limited to, silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric materials, dielectric metal oxides commonly referred to as high dielectric constant (high-k) dielectric oxides (e.g., aluminum oxide, hafnium oxide, etc.) and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials. In one embodiment, the first material of the insulating layer 132 may be silicon oxide and/or organosilicate glass.

The second material of the sacrificial material layer 142 is a sacrificial material that is selectively removable with respect to the first material of the insulating layer 132. As used herein, the removal of a first material is "selective" to a "second material" if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the "selectivity" of the removal process for the first material relative to the second material.

The sacrificial material layer 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the sacrificial material layer 142 may then be replaced with a conductive electrode, which may, for example, serve as a control gate electrode for a vertical NAND device. Non-limiting examples of the second material include silicon nitride, amorphous semiconductor materials (such as amorphous silicon), and polycrystalline semiconductor materials (such as polysilicon). In one embodiment, the sacrificial material layer 142 may be a spacer material layer comprising silicon nitride or a semiconductor material comprising at least one of silicon and germanium. Alternatively, a permanent conductive layer may be employed in place of the sacrificial material layer 142. The permanent conductive layer may comprise a conductive material such as a metal, polysilicon, metal silicide (e.g., NiSi). In this case, the permanent conductive layer is not replaced with a different material and serves as the control gate electrode for the vertical NAND device.

In one embodiment, the insulating layer 132 may comprise silicon oxide and the sacrificial material layer may comprise a silicon nitride sacrificial material layer. The first material of the insulating layer 132 may be deposited, for example, by Chemical Vapor Deposition (CVD). For example, if silicon oxide is used for insulating layer 132, tetraethyl orthosilicate (TEOS) may be employed as a precursor material for a CVD process. The second material of the sacrificial material layer 142 may be formed, for example, CVD or Atomic Layer Deposition (ALD).

The thickness of insulating layer 132 and sacrificial material layer 142 may be in the range of 20nm to 50nm, and smaller and larger thicknesses may be used for each insulating layer 132 and each sacrificial material layer 142. The number of repetitions of the pair of insulating layer 132 and sacrificial material layer (e.g., control gate electrode or sacrificial material layer) 142 may be in the range of 2 to 1,024, and typically in the range of 8 to 256, although greater numbers of repetitions may also be employed. The top gate electrode and the bottom gate electrode in the stack may be used as select gate electrodes. In one embodiment, each sacrificial material layer 142 in the alternating stack (132,142) may have a uniform thickness that is substantially constant within each respective sacrificial material layer 142.

Optionally, an insulating cap layer 70 may be formed over the alternating stack (132, 142). The insulating cap layer 70 includes a dielectric material different from the material of the sacrificial material layer 142. In one embodiment, the insulating cap layer 70 may comprise a dielectric material that may be used for the insulating layer 132 as described above. The insulating cap layer 70 may have a greater thickness than each of the insulating layers 132. The insulating cap layer 70 may be deposited by, for example, chemical vapor deposition. In one embodiment, the insulating cap layer 70 may be a silicon oxide layer.

Referring to fig. 17, a stepped cavity may be formed within the stepped region 300, and optionally within the peripheral device region 200. The stepped cavity may have various stepped surfaces such that the horizontal cross-sectional shape of the stepped cavity varies stepwise with vertical distance from the top surface of the substrate (109, 110). In one embodiment, the stepped cavity may be formed by repeatedly performing a set of processing steps. The set of processing steps may include, for example, a first type of etching process that vertically increases the cavity depth by one or more levels and a second type of etching process that laterally extends the region to be vertically etched in a subsequent etching process of the first type. As used herein, a "level" of a structure comprising alternating layers is defined as the relative position of a pair of first and second material layers within the structure.

After forming the stepped cavities, the remaining peripheral portions of the alternating stacks (132,142) can have stepped surfaces. As used herein, "stepped surface" refers to a set of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface abuts a first vertical surface extending upward from a first edge of the horizontal surface, and abuts a second vertical surface extending downward from a second edge of the horizontal surface. "stepped cavity" refers to a cavity having a stepped surface.

The inversely stepped dielectric material portion 65 (i.e., the insulating fill material portion) may be formed in the stepped cavity by depositing a dielectric material therein. For example, a dielectric material such as silicon oxide may be deposited in the stepped cavity. Excess portions of the deposited dielectric material may be removed from over the top surface of the insulating cap layer 70, for example, by Chemical Mechanical Planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes a retrograde stepped dielectric material portion 65. As used herein, a "retro-stepped" element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases with vertical distance from the top surface of the substrate on which the element is present. If silicon oxide is used for the retro-stepped dielectric material portion 65, the silicon oxide of the retro-stepped dielectric material portion 65 may or may not be doped with dopants, such as B, P and/or F.

Referring to fig. 18A and 18B, a stack of photolithographic material (not shown) including at least a photoresist layer may be formed over the insulating cap layer 70 and the alternating stack (132,142), and may be lithographically patterned to form openings therein. The pattern in the stack of photolithographic material can be transferred through the insulating layer 70 and through the entire alternating stack (132,142) by at least one anisotropic etch that employs the patterned stack of photolithographic material as an etch mask. Portions of the alternating stacks (132,142) underlying the openings in the patterned stack of photolithographic material are etched to form memory openings 49. In other words, the pattern transfer in the patterned stack of photolithographic material forms memory openings 49 extending through the alternating stack (132, 142). The chemical nature of the anisotropic etching process used to etch through the material of the alternating stack (132,142) may be alternated to optimize the etching of the first and second materials in the alternating stack (132, 142). The anisotropic etch may be, for example, a series of reactive ion etches. The sidewalls of the reservoir opening 49 may be substantially vertical, or may be tapered. The patterned stack of photolithographic material can then be removed, for example, by ashing.

In one implementation, an overetch of the layer of semiconductor material 110 may optionally be performed after the top surface of the layer of semiconductor material 110 is physically exposed at the bottom of each memory opening 49. The overetch may be performed before or after the removal of the stack of photolithographic materials. In other words, the recessed surface of the semiconductor material layer 110 may be vertically offset from the unprocessed top surface of the semiconductor material layer 110 by a recess depth. The recess depth may be, for example, in the range of 1nm to 50nm, although smaller and larger recess depths may also be employed. The over-etching is optional and may be omitted. If no over-etching is performed, the bottom surface of each memory opening 49 may be coplanar with the topmost surface of the layer of semiconductor material 110. Each of the memory openings 49 may include a sidewall (or sidewalls) that extends substantially perpendicular to a topmost surface of the substrate. The region in which the array of memory openings 49 is formed is referred to herein as the device region. The substrate semiconductor layer 109 and the semiconductor material layer 110 together constitute a substrate (109,110), which may be a semiconductor substrate. Alternatively, the semiconductor material layer 110 may be omitted and the memory opening 49 may extend to the top surface of the substrate semiconductor layer 109.

Various implementations of the present disclosure may be employed to form a memory stack structure in each of the memory openings. Fig. 19A-19K illustrate sequential vertical cross-sectional views of a memory opening within a fifth exemplary structure during formation of a fifth exemplary memory opening filling structure, according to a fifth embodiment of the present disclosure. The formation of the exemplary memory opening filling structure may be performed within each of the memory opening 49 and the support opening 19 in the fifth exemplary structure shown in fig. 18A and 18B.

Referring to fig. 19A, a memory opening 49 in the fifth exemplary structure of fig. 18A and 18B is shown. The memory opening 49 extends through the insulating cap layer 70, the alternating stacks (132,142), and optionally into an upper portion of the semiconductor material layer 110. The recess depth of the bottom surface of each memory opening relative to the top surface of the layer of semiconductor material 110 may be in the range of 0nm to 30nm, although greater recess depths may also be employed. Optionally, sacrificial material layer 142 may be partially laterally recessed, such as by isotropic etching, to form lateral recesses (not shown).

Referring to fig. 19B, an optional pedestal channel portion 111 may be formed at a bottom portion of each memory opening 49, such as by selective epitaxy. Each pedestal channel portion 111 comprises a single crystal semiconductor material that is epitaxially aligned with the single crystal semiconductor material of the layer of semiconductor material 110. In one embodiment, the base channel portion 111 may be doped with ions of the same conductivity type as the semiconductor material layer 110. In one implementation, the top surface of each pedestal channel portion 111 may be formed above a horizontal plane that includes the top surface of the sacrificial material layer 142. In this case, at least one source select gate electrode may then be formed by replacing each sacrificial material layer 142 located below the horizontal plane including the top surface of the pedestal channel portion 111 with a respective conductive material layer. The pedestal channel portion 111 may be a portion of the transistor channel that extends between a source region to be subsequently formed in the substrate (109,110) and a drain region to be subsequently formed in an upper portion of the memory opening 49. A cavity 49' exists in the unfilled portion of the memory opening 49 above the pedestal channel portion 111. In one embodiment, the base channel portion 111 may comprise monocrystalline silicon. In one embodiment, the pedestal channel portion 111 may have a doping of a first conductivity type that is the same as the conductivity type of the semiconductor material layer 110 with which the pedestal channel portion is in contact. If the layer of semiconductor material 110 is not present, the pedestal channel portion 111 may be formed directly on the substrate semiconductor layer 109, which may have a doping of the first conductivity type.

Optionally, a ferroelectric side interface dielectric layer can be formed by conformal deposition of a dielectric material in the memory openings, as will be discussed in more detail below with respect to fig. 26B. The ferroelectric side interface dielectric layer (if present) includes a dielectric material that improves the interface quality and improves the ferroelectric properties of the ferroelectric material layer and the gate electrode to be subsequently formed by replacing the sacrificial material layer 142 with a conductive layer. The ferroelectric-side interfacial dielectric layer 1 comprises hafnium aluminum oxide, hafnium oxide, or aluminum oxide. The thickness of the channel side interface dielectric layer may be in a range of 1nm to 2 nm.

Referring to fig. 19C, at least one ferroelectric dielectric layer (504,506) may be formed in each of the memory openings 49, in each of the support openings 19, and over the insulating cap layer 70. If an optional ferroelectric side interface dielectric layer is present in the opening (19,49), at least one ferroelectric dielectric layer (504,506) may be formed directly on the ferroelectric side interface dielectric layer. The at least one ferroelectric dielectric layer (504,506) may comprise any ferroelectric dielectric materialAnd (5) feeding. In one embodiment, the at least one ferroelectric dielectric layer (504,506) includes only one ferroelectric dielectric layer 504. The ferroelectric dielectric layer may comprise hafnium oxide (such as hafnium oxide containing at least one dopant selected from Al, Zr, and Si and having a ferroelectric non-centrosymmetric orthorhombic phase), zirconium oxide, hafnium zirconium oxide, bismuth ferrite, barium titanate (such as BaTiO) ₃(ii) a BT), colemanite (such as Ca)₂B₆O₁₁·5H₂O), bismuth titanates (such as Bi)₄Ti₃O₁₂) Europium barium titanate, ferroelectric polymers, germanium telluride, potassium magnesium anhydrous alum (such as M)₂M'₂(SO₄)₃Where M is a monovalent metal and M' is a divalent metal), lead scandium tantalum (such as Pb (Sc)_xTa_1-x)O₃) Lead titanate (such as PbTiO)₃(ii) a PT), lead zirconate titanate (such as Pb (Zr, Ti) O₃(ii) a PZT), lithium niobate (such as LiNbO)₃；LN)、(LaAlO₃) Polyvinylidene fluoride (CH), polyvinylidene fluoride (CH)₂CF₂)_nPotassium niobate (such as KNbO)₃) Sodium tartrate (such as KNaC)₄H₄O₆·4H₂O), potassium titanyl phosphate (such as KO)₅PTi), bismuth sodium titanate (such as Na)_0.5Bi_0.5TiO₃Or Bi_0.5Na_0.5TiO₃) Lithium tantalate (such as LiTaO)₃(LT)), lead lanthanum titanate (such as (Pb, La) TiO)₃(PLT)), lead lanthanum zirconium titanates (such as (Pb, La) (Zr, Ti) O₃(PLZT)), ammonium dihydrogen phosphate (such as NH)₄H₂PO₄(ADP)) or monopotassium phosphate (such as KH₂PO₄(KDP))。

In another embodiment, the at least one ferroelectric dielectric layer (504,506) includes a first ferroelectric dielectric layer 504 deposited first and a second dielectric layer 506 (which may be a ferroelectric dielectric layer or a non-ferroelectric dielectric layer) deposited on the first ferroelectric dielectric layer 504. The first ferroelectric dielectric layer 504 is also referred to as an outer ferroelectric dielectric layer and the second dielectric layer 506 is also referred to as an inner dielectric layer, which may be a ferroelectric or non-ferroelectric dielectric layer. Each of the at least one ferroelectric dielectric layer (504,506) may be deposited by a respective conformal deposition process, such as an Atomic Layer Deposition (ALD) process or a Chemical Vapor Deposition (CVD) process. In this embodiment, the at least one ferroelectric dielectric layer (504,506) may comprise a layer stack configured to reduce electron tunneling from the channel into the at least one ferroelectric dielectric layer (504,506) and to improve the quality of the interface with the channel to be deposited in a subsequent step. In this case, the first ferroelectric dielectric layer 504 can have a first band gap energy and the second dielectric layer 506 can have a second band gap energy greater than the first band gap energy to reduce electron tunneling from the channel into the layer 504. For example, both dielectric layers may comprise hafnium aluminum oxide, which may optionally be doped with zirconium. First ferroelectric dielectric layer 504 may have a greater thickness and a higher atomic ratio of hafnium to aluminum than second dielectric layer 506. In this case, hafnium-rich first ferroelectric dielectric layer 504 may be used to store data based on its ferroelectric state, while aluminum-rich second dielectric layer 506 may be used to improve the interface with the channel and reduce electron tunneling from the channel into layer 504. If the aluminum atomic fraction of the second dielectric layer 506 is high enough, this layer may lose its ferroelectric properties and act as an interfacial layer to improve the quality of the interface with the channel. Additionally, layer 506 may be a ferroelectric dielectric layer.

In an illustrative example, the first ferroelectric dielectric layer 504 may have Hf_1.5(1-α-β)Zr_1.5βAl_2αO₃Wherein α is in the range of 0.01 to 0.2 (such as 0.025 to 0.05) and β is in the range of 0 to 0.2. The second dielectric layer 506 may have Hf_1.5γZr_1.5δAl_2(1-γ-δ)O₃Wherein γ is in the range of 0 to 0.2 (such as 0.05 to 0.15) and δ is in the range of 0 to 0.2. For example, first ferroelectric dielectric layer 504 can be hafnium aluminum oxide with an aluminum mole fraction of 0.05 to 0.08 (i.e., aluminum doped orthorhombic ferroelectric hafnium oxide), while second dielectric layer 506 can have an aluminum mole fraction of 0.6 to 1 (i.e., it can consist essentially of aluminum oxide that is not ferroelectric or hafnium doped aluminum oxide).

The thickness of the first ferroelectric dielectric layer 504 may be in the range of 6nm to 16nm, such as in the range of 8nm to 12 nm. The thickness of the second dielectric layer 506 may be in the range of 0.5nm to 3nm (such as 1nm to 2nm), although lesser and greater thicknesses may also be employed.

Where an aluminum doped hafnium oxide layer is used for first ferroelectric dielectric layer 504 and second dielectric layer 506, the mole fraction of aluminum atoms within each of first ferroelectric dielectric layer 504 and second dielectric layer 506 can be provided by adjusting the cycling ratio of the hafnium deposition cycle to the aluminum deposition cycle. The cycling ratio may be in a range of 20:1 to 10:1 for the deposition of the first ferroelectric dielectric layer 504 and in a range of 1:1.5 to 1:10 for the deposition of the second dielectric layer 506.

A sacrificial capping material layer 508 may be formed over at least one ferroelectric dielectric layer (504, 506). The sacrificial cover material layer 508 comprises a thin layer of sacrificial material that protects the at least one ferroelectric dielectric layer (504,506) during a subsequent anisotropic etch process and that can be selectively removed with respect to the material of the at least one ferroelectric dielectric layer (504, 506). For example, the sacrificial capping material layer 508 may include amorphous silicon and may have a thickness in a range of 1nm to 5 nm. A thermal annealing process, such as Rapid Thermal Annealing (RTA), at a temperature of at least 1,000 degrees celsius may be performed for 1 to 2 seconds to induce crystallization of the at least one ferroelectric dielectric layer (504,506), thereby inducing ferroelectricity in the at least one ferroelectric dielectric layer (504, 506).

Referring to fig. 19D, an anisotropic etch process may be performed to remove horizontal portions of the sacrificial cover material layer 508 and the at least one ferroelectric dielectric layer (504, 506). The anisotropic etch process may comprise a reactive ion etch process including a first step with an etch chemistry that etches the material of the sacrificial cover material layer 508 and a second step with an etch chemistry that etches the material of the at least one ferroelectric dielectric layer (504, 506). A central portion of each pedestal channel portion 111 may be laterally recessed by an anisotropic etch process. A tubular ferroelectric dielectric layer 500 comprising a cylindrical remainder of the first ferroelectric dielectric layer 504, a cylindrical remainder of the second ferroelectric dielectric layer 506 may be formed in each memory opening 49 and in each support opening 19 after anisotropically etching the first ferroelectric dielectric layer 504 and the second ferroelectric dielectric layer 506.

Referring to fig. 19E, the sacrificial cover material layer 508 may be removed selective to the at least one ferroelectric dielectric layer (504,506) by an isotropic etch process. For example, a wet etch process utilizing thermal trimethyl-2 hydroxyethylammonium hydroxide ("thermal TMY") or tetramethylammonium hydroxide (TMAH) may be employed to selectively remove the sacrificial capping material layer 508 for the at least one ferroelectric dielectric layer (504, 506).

Referring to fig. 19F, a two-dimensional electron gas ("2 DEG") channel layer, such as a metal dichalcogenide layer 60L, is deposited on the physically exposed surfaces of the pedestal channel portion 111, the tubular ferroelectric dielectric layer 500, and the insulating cap layer 70. In one embodiment, the metal dichalcogenide in the metal dichalcogenide layer 60L may comprise a transition metal dichalcogenide, i.e., a dichalcogenide of a transition metal. For example, the transition metal dichalcogenide may comprise Mo_1-xW_xS_2-ySe_yWherein x is a number in the range of 0 (and including 0) to 1 (and including 1), and y is a number in the range of 0 (and including 0) to 2 (and including 2). Thus, the transition metal dichalcogenide may comprise MoS₂、WS₂、MoSe₂、WSe₂Or a ternary or quaternary alloy thereof.

In one embodiment, the metal dichalcogenide layer 60L may have a composition that may be Mo _1-xW_xS_2-ySe_yA thickness in the range of 1 monolayer to 5 monolayers. In one embodiment, the metal dichalcogenide layer 60L may have Mo at 0.6nm to 4nm_1-xW_xS_2-ySe_yA substantially uniform thickness within the range of (a). In one embodiment, the metal dichalcogenide layer 60L may have a composition of Mo_1-xW_xS_2-ySe_yA thickness in the range of 1 monolayer to 3 monolayers. Within such thickness ranges, the metal dichalcogenide layer 60L can provide a two-dimensional electron gas with quantum confinement along a radial direction of the memory opening (i.e., quantum confinement in a direction of the thickness of the metal dichalcogenide layer 60L). In the case where the pedestal channel portion 111 is formed at the lower end of the memory openingNext, the metal dichalcogenide layer 60l may be formed directly on the top surface of the pedestal channel portion.

In one embodiment, Mo of the two-dimensional electron gas channel layer 60L_1-xW_xS_2-ySe_yThe material can pass through Mo_1-xW_xO_yDeposition and chalcogenization (e.g., sulfidation) of a thin film of an alloy (i.e., molybdenum oxide, tungsten oxide, or molybdenum tungsten oxide) is formed directly on the tubular ferroelectric dielectric layer 500, where x ranges from 0 to 1 and y ranges from 2 to 3. Mo_1-xW_xO_yThe alloy thin film may be deposited using a super-cyclic Atomic Layer Deposition (ALD) process, where one super-cycle includes n MoOs _xDeposition cycle and m WO₃Deposition cycles, as described, for example, in J.Song et al, Nature Communications, 6:7817 (2015). Mo is mixed with_1-xW_xO_yChalcogenization of alloy thin films to form Mo_1-xW_xS_2-ySe_yThe material may be formed by one or two step anneals in chalcogen (e.g., sulfur-and/or selenium-containing ambient). For example, to form Mo_1-xW_xS₂Film of argon and H₂Mo is mixed at a temperature of 600 to 850 ℃ in an environment of S_1-xW_xO_yThe alloy film is annealed for 30 to 60 minutes. Optionally, a second annealing step using Rapid Thermal Processing (RTP) at a higher temperature of 950 to 1050 ℃ or a 15 to 30 minute furnace anneal in the same ambient may also be performed after the initial anneal.

Can be controlled by MoO_xWith WO₃Optimizing Mo by ALD cycle ratio between atomic layer depositions_1-xW_xS_2-ySe_yComposition and number of atomic layers of the alloy. Mo_1-xW_xS_2-ySe_yThe band gap of the alloys can be precisely controlled as a function of the composition and number of layers of each respective alloy. Mo_1-xW_xS_2-ySe_yThe Vertical Composition Control (VCC) multilayer stack of (a) may be formed using a sequential super-cyclic atomic layer deposition process. For example, for each super-cycle, atoms may be employed at different cycle ratios5 successive super-cycles of the layer deposition step. VCC Mo synthesized by the method _1-xW_xS_2-ySe_yThe multilayer stack may have a higher density than by transferring Mo alone_1-xW_xS_2- _ySe_ySingle layer and produced VCC Mo_1-xW_xS_2-ySe_yStronger interlayer coupling within the multilayer stack.

Thus, in one embodiment, the two-dimensional electron gas channel layer 60L may be formed by: multiple successive cycles of the molybdenum oxide layer deposition step and multiple successive cycles of the tungsten oxide layer deposition step are performed, followed by chalcogenization at high temperature.

The metal dichalcogenide material of the two-dimensional electron gas channel layer 60L may be deposited As a crystalline semiconductor material or an amorphous semiconductor material that may be subsequently annealed to convert into the crystalline semiconductor material As used herein, "crystalline material" refers to a material that is either monocrystalline or polycrystalline. In one embodiment, the metal dichalcogenide material of the two-dimensional electron gas channel layer 60L may be formed as or may be converted to a polycrystalline material during an annealing process. The two-dimensional semiconductor channel material of the two-dimensional electron gas channel layer 60L is formed directly on the physically exposed surface of the tubular ferroelectric dielectric layer 500.

The non-single crystal semiconductor film may be crystallized to various degrees. For example, a polycrystalline semiconductor film is composed of "grains". Within each grain, the material is in a crystalline phase. That is, within each grain, the crystal structure is oriented in the same manner. However, the crystal orientation may be different in different grains. Polycrystalline semiconductor material, as the term is used herein, includes nanocrystals, microcrystals, or even larger crystals. The term depends on the grain size. The nanocrystals have a size of about one nanometer (1 × 10) ^-9Meters) to several hundred nanometers. The microcrystals have a size of one micron (1X 10)^-6Meters) to several hundred microns. Thus, polycrystalline semiconductor material may have a higher atomic order than amorphous semiconductor material. Therefore, the density of defect states of the polycrystalline semiconductor film is lower than that of the amorphous semiconductor filmThe defect state density of (2).

Referring to fig. 19G, a channel side interface dielectric layer 522 may be optionally formed on an inner sidewall of the two-dimensional electron gas channel layer 60L. The channel side interface dielectric layer 522 comprises a dielectric material that improves interface quality and reduces the well density of the two-dimensional electron gas channel layer 60L at the interface with the channel side interface dielectric layer 522, thereby improving charge carrier mobility in the two-dimensional electron gas channel layer 60L. In one embodiment, the channel side interface dielectric layer 522 comprises hafnium aluminum oxide, hafnium oxide, or aluminum oxide. The thickness of the channel side interface dielectric layer 522 may be in the range of 1nm to 2 nm.

Referring to fig. 19H, a dielectric core 62 is formed within each cavity 49' laterally surrounded by a channel side interface dielectric layer 522. For example, a dielectric material, such as silicon oxide or organosilicate glass, may be deposited in each cavity 49' by a conformal deposition method, such as Low Pressure Chemical Vapor Deposition (LPCVD), or by a self-planarizing deposition process, such as spin-on coating.

Horizontal portions of the dielectric material, optional channel side interface dielectric layer 522 (if present), and the two-dimensional electron gas channel layer 60L may be removed from over the top surface of the insulating cap layer 70 by a planarization process. A planarization process may be employed, such as by recess etching or chemical mechanical planarization. Each remaining portion of the two-dimensional electron gas channel layer 60L constitutes a two-dimensional electron gas channel 60 extending through the memory opening and located inside the tubular ferroelectric dielectric layer 500. Each remaining portion of the dielectric material constitutes a dielectric core 62 that is located within the two-dimensional electron gas channel 60 and the optional channel-side interface dielectric layer 522.

Referring to fig. 19I, the top surface of the remainder of the dielectric core layer may be recessed, such as by a recess etch, to a depth between the top surface of the insulating cap layer 70 and the bottom surface of the insulating cap layer 70 to form a recess region within each memory opening 49. The top surface of the dielectric core 62 is located between a first horizontal plane including the top surface of the insulating cap layer 70 and a second horizontal plane including the bottom surface of the insulating cap layer 70.

Referring to fig. 19J, a semiconductor can be formed by doping a semiconductorA material is deposited in each recessed region above dielectric core 62 to form a doped semiconductor drain portion 630. The doped semiconductor drain portion 630 is a drain region comprising a doped semiconductor material. The doped semiconductor material may be, for example, doped polysilicon or a doped compound semiconductor material. In one embodiment, the atomic concentration of the dopant of the second conductivity type in the doped semiconductor material may be at 1.0 x 10 ¹⁹/cm³To 2.0X 10²¹/cm³But smaller and larger atomic concentrations may also be used. The dopant may be introduced in-situ during growth and/or ex-situ after growth by ion implantation.

Excess portions of the deposited semiconductor material may be removed from over the top surface of the insulating cap layer 70, for example by Chemical Mechanical Planarization (CMP) or a recess etch, to form a doped semiconductor drain portion 630 embedded within the two-dimensional electron gas channel 60. In one embodiment, the top surface of the doped semiconductor drain portion 630 may be coplanar with the top surface of the insulating cap layer 70. In one embodiment, the top surfaces of the doped semiconductor drain portion 630, the optional channel side interface dielectric layer 522, the two-dimensional electron gas channel 60, and the tubular ferroelectric dielectric layer 500 may be coplanar with the top surface of the insulating cap layer 70. A doped semiconductor drain portion 630 comprising a doped semiconductor material portion may be formed directly on the sidewalls of the two-dimensional electron gas channel 60.

Due to the two-dimensional or pseudo-two-dimensional nature of the two-dimensional electron gas channel 60, a two-dimensional electron gas may be formed in the two-dimensional electron gas channel 60. The two-dimensional electron gas may be a cylindrically confined electron gas. As used herein, "cylindrical confinement" refers to a two-dimensional confinement in which the global topology of the two-dimensional space is isomorphic to the sidewall surface that is a cylinder. As used herein, "cylindrically confined electron gas" refers to a cylindrically confined electron gas. Quantum confinement (e.g., quantization) of electrons occurs in the channel. The electron current can flow vertically with higher mobility in the cylindrically confined electron gas.

Each successive combination of a tubular ferroelectric dielectric layer 500 and a two-dimensional electron gas channel 60 within a memory opening 49 constitutes a memory stack structure 55. The collection of all material portions filling the memory opening 49 constitutes a memory opening filling structure 58. Fig. 19J shows a first exemplary memory opening fill structure 58 that includes an optional pedestal channel portion 111, a memory stack structure 55, an optional channel side interface dielectric layer 522, a dielectric core 62, and a drain region 63.

Referring to fig. 19K, an alternative embodiment of a first exemplary memory opening fill structure 58 is shown. An alternative implementation of the first exemplary memory opening fill structure 58 may be derived from the structure of fig. 19I or the structure of fig. 3J by implanting ions, such as n-type dopants, into an upper portion of the two-dimensional electron gas channel 60. The implanted upper portion of the two-dimensional electron gas channel 60 is converted into a doped cyclic metal dichalcogenide portion referred to herein as the cyclic doped metal dichalcogenide drain portion 631. Each drain region 63 may include a set of ring-shaped doped metal dichalcogenide drain portions 631 and doped semiconductor drain portions 630. In one embodiment, ion implantation may be performed after the processing step of fig. 19I and before the processing step of fig. 19J. In another embodiment, ion implantation may be performed after the processing step of fig. 19J. In this case, the doped semiconductor drain portion 630 may be formed directly on the inner sidewall of the ring-shaped doped metal dichalcogenide drain portion 631 as another component of the drain region 63.

In general, a vertical stack of ferroelectric memory elements may be formed at the periphery of each memory opening 49 at each level of a layer of spacer material (which may be a layer of sacrificial material 142). Ferroelectric memory elements may be formed by conformal deposition and anisotropic etching of at least one ferroelectric dielectric layer (504, 506). The ferroelectric memory element comprises respective portions of tubular ferroelectric dielectric layers 500 at the level of the respective sacrificial material layers 142. A two-dimensional electron gas channel 60 is formed inside each tubular ferroelectric dielectric layer 500. A dielectric core 62 may be formed inside each two-dimensional electron gas channel 60.

Referring to fig. 20A, a tubular ferroelectric dielectric layer 500 is shown as being a vertical axis from a geometric center through a memory opening fill structure 58The composition of the function of the radial distance R varies. The interface between the sacrificial material layer 142 and the tubular ferroelectric dielectric layer 500 corresponds to the interface between a gate electrode to be subsequently formed and a ferroelectric memory element. The interface between the tubular ferroelectric dielectric layer 500 and the two-dimensional electron gas channel 60 corresponds to the interface between the ferroelectric memory element and the semiconductor channel of the transistor. The portion of the tubular ferroelectric dielectric layer 500 comprising the first ferroelectric dielectric layer 504 may have Hf _1.5(1-α-β)Zr_1.5βAl_2αO₃Wherein α is in the range of 0.01 to 0.2, and β is in the range of 0 to 0.2. The portion of the tubular ferroelectric dielectric layer 500 comprising the second dielectric layer 506 may have Hf_1.5γZr_1.5δAl_2(1-γ-δ)O₃Wherein γ is in the range of 0.05 to 0.2, and δ is in the range of 0 to 0.2. Thus, the first ferroelectric dielectric layer 504 includes a first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer, and the second dielectric layer 506 includes a second hafnium aluminum oxide or hafnium zirconium aluminum oxide layer having a higher aluminum concentration than the first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer.

Referring to fig. 20B and 20C, band diagrams of the tubular ferroelectric dielectric layer 500 are shown for the following cases: wherein the first ferroelectric dielectric layer 504 has Hf_1.35Al_0.2O₃And the second dielectric layer 506 has a material composition with a higher atomic ratio of aluminum to hafnium than the first ferroelectric dielectric layer 504. As shown in fig. 20B, for an exemplary gate bias voltage of 4 to 8V applied during an erase operation, electron tunneling from the two-dimensional electron gas channel 60 into the first ferroelectric dielectric layer 504 may be due to Hf in the second dielectric layer 506_1.35Al_0.2O₃Is reduced by the wider band gap.

As shown in FIG. 20C, for an exemplary gate bias voltage of-4 to-8V applied during a program operation, hole tunneling from the two-dimensional electron gas channel 60 into the first ferroelectric dielectric layer 504 may also be due to Hf in the second dielectric layer 506 _1.35Al_0.2O₃Is reduced.

Fig. 21A to 21C illustrate a process of forming a second exemplary memory opening fill structure according to a sixth embodiment. Referring to fig. 21A, the first exemplary memory opening fill structure of fig. 19I may be modified by forming a ring-shaped doped metal dichalcogenide drain portion 631. The annular doped metal dichalcogenide drain portion 631 may be formed, for example, by implanting ions into an upper portion of the two-dimensional electron gas channel 60 using an ion implantation process or a plasma doping process. The upper portion of the two-dimensional electron gas channel 60 is converted into a ring-shaped doped metal dichalcogenide drain portion 631. Thus, the ring-shaped doped metal dichalcogenide drain portion 631 contacts an upper end of the remaining portion of the two-dimensional electron gas channel 60. The ring-shaped doped metal dichalcogenide drain portion 631 is part of the drain region.

Referring to fig. 21B, a metal material layer may be directly deposited on the ring-shaped metal-doped dichalcogenide drain portion 631. The metallic material layer may comprise and/or may consist of: a nickel layer, a nickel silicide layer, a heavily N + doped polysilicon layer, a stack of a titanium layer and a gold layer, or a stack of a nickel layer and a gold layer. In an illustrative example, the stack of titanium layer 632 and gold layer 634 may be deposited directly on the annular doped metal dichalcogenide drain portion 631. Titanium layer 632 may consist essentially of titanium and may have a thickness in the range of 1nm to 30nm, although lesser and greater thicknesses may also be employed. The gold layer 634 may consist essentially of gold and may have a thickness in the range of 1nm to 30nm, although lesser and greater thicknesses may also be employed. A recessed region may be present above the dielectric core 62 and within the sidewalls of the stack of titanium layer 632 and gold layer 634.

Referring to fig. 21C, a doped semiconductor material, such as N-doped polysilicon, may be deposited within the recessed regions. The doped semiconductor material can be deposited to form the doped semiconductor drain portion 630 using the same deposition method employed at the processing step of fig. 19J. In one embodiment, the atomic concentration of the dopant of the second conductivity type in the doped semiconductor material may be at 1.0 × 10¹⁹/cm³To 2.0X 10²¹/cm³But smaller and larger atomic concentrations may also be used. The dopant may be introduced in-situ during growth and/or ex-situ after growth by ion implantation.

The portions of the doped semiconductor material, the gold layer 634 and the titanium layer 632 that are above a horizontal plane that includes the top surface of the insulating cap layer 70 may be removed by a planarization process, which may include at least one recess etch and/or chemical mechanical planarization. Each remaining portion of doped semiconductor material is a doped semiconductor drain region 630. Each remaining portion of gold layer 634 may include a cylindrical portion and a horizontal bottom portion. Each remaining portion of titanium layer 632 may include a cylindrical portion and a horizontal bottom portion. Each drain region 63 may include a ring-shaped doped metal dichalcogenide drain portion 631, a titanium layer 632 contacting the ring-shaped doped metal dichalcogenide drain portion 631, a gold layer 634 contacting the titanium layer 632, and a doped semiconductor drain portion 630 embedded within and laterally surrounded by the stack of the titanium layer 632 and the gold layer 634. Thus, a doped semiconductor drain portion 630 is formed within a cavity laterally surrounded by the stack of titanium layer 632 and gold layer 634. A second exemplary memory opening fill structure 58 is disposed within each memory opening 49.

Referring to fig. 21D, an alternative embodiment of the second exemplary memory opening fill structure 58 may be derived from the second exemplary memory opening fill structure 58 by omitting the formation of the halo-doped metal dichalcogenide drain portion 631. In this case, the titanium layer 632 may be directly formed on the sidewall of the two-dimensional electron gas channel 60. The doped semiconductor drain portion 630 may be formed by in situ doping of the deposited semiconductor material.

Referring to fig. 22A, a memory opening 49 is shown including a third exemplary memory opening fill structure 58 according to a seventh embodiment. The third example memory opening fill structure 58 may be derived from the second example memory opening fill structure 58 of fig. 21B by: the thicknesses of the titanium layer 632 and the gold layer 634 are selected so that the entire cavity above the dielectric core 62 is filled with the stack of titanium layer 632 and gold layer 634, and a planarization process is employed to remove portions of the stack of titanium layer 632 and gold layer 634 from above a horizontal plane including the top surface of the insulating cap layer 70. In this case, each drain region 63 may include a ring-shaped doped metal dichalcogenide drain portion 631, a titanium layer 632, and a gold layer 634.

Referring to fig. 22B, an alternative embodiment of the third exemplary memory opening fill structure 58 is shown that may be derived from the third exemplary memory opening fill structure 58 of fig. 22A by omitting the formation of the halo-doped metal dichalcogenide drain portion 631. In this case, the titanium layer 632 may be directly formed on the sidewall of the two-dimensional electron gas channel 60.

Multiple instances of any of the exemplary memory opening fill structures 58 described above may be formed in the fifth exemplary structure shown in fig. 18A and 18B. Fig. 23 illustrates a fourth exemplary structure incorporating multiple instances of an exemplary memory opening fill structure 58, which may be any of the exemplary memory opening fill structures of fig. 19J, 19K, 21C, 21D, 22A, or 22B.

Referring to fig. 24A and 24B, a contact level dielectric layer 73 may be formed over the alternating stack (132,142) of insulating layers 132 and sacrificial material layers 142 and over the memory opening fill structures 58 and support post structures 24. The contact level dielectric layer 73 comprises a dielectric material that is different from the dielectric material of the sacrificial material layer 142. For example, the contact level dielectric layer 73 may comprise silicon oxide. The contact level dielectric layer 73 may have a thickness in the range of 50nm to 500nm, although lesser and greater thicknesses may also be employed.

A photoresist layer (not shown) may be applied over the contact level dielectric layer 73 and lithographically patterned to form openings in the regions between the clusters of memory stack structures 55. The pattern in the photoresist layer may be transferred using an anisotropic etch through the contact level dielectric layer 73, the alternating stacks (132,142), and/or the retro-stepped dielectric material portions 65 to form a backside trench 79 that extends vertically from the top surface of the contact level dielectric layer 73 at least to the top surface of the substrate (109,110) and laterally through the memory array region 1100 and the step region 300.

In one embodiment, the backside grooves 79 may extend laterally along the first horizontal direction hd1 and may be laterally spaced apart from each other along the second horizontal direction hd2, which is perpendicular to the first horizontal direction hd 1. The memory stack structures 55 may be arranged in rows extending along the first horizontal direction hd 1. The drain select level isolation structure 72 may extend laterally along the first horizontal direction hd 1. Each backside groove 79 may have a uniform width that is constant along the longitudinal direction (i.e., along the first horizontal direction hd 1). Each drain select level isolation structure 72 may have a uniform vertical cross-sectional profile along a vertical plane perpendicular to the first horizontal direction hd1 that does not vary with translation along the first horizontal direction hd 1. Multiple rows of memory stack structures 55 may be located between adjacent pairs of backside trenches 79 and drain select level isolation structures 72, or between adjacent pairs of drain select level isolation structures 72. In one implementation, the backside trench 79 may include a source contact opening where a source contact via structure may be subsequently formed. The photoresist layer may be removed, for example, by ashing.

Dopants of the second conductivity type may be implanted into portions of the layer of semiconductor material 110 below the backside trenches 79 to form source regions 61. The atomic concentration of the dopant of the second conductivity type in the source region 61 may be 5.0 × 10 ¹⁹/cm³To 2.0X 10²¹/cm³But smaller and larger atomic concentrations may also be used. A surface portion of the layer of semiconductor material 110 extending between each source region 61 and an adjacent memory opening fill structure 58 includes a horizontal semiconductor channel 59.

Referring to fig. 25, an etchant may be introduced into the backside trench 79, for example, using an etching process, which etches the second material of the sacrificial material layer 142 selectively to the first material of the insulating layer 132. Backside recesses 143 are formed in the volume from which sacrificial material layer 142 is removed. The removal of the second material of the sacrificial material layer 142 may be selective to the first material of the insulating layer 132, the material of the retro-stepped dielectric material portion 65, the semiconductor material of the semiconductor material layer 110, and the material of the outermost layer of the ring-shaped ferroelectric dielectric layer 500. In one embodiment, the sacrificial material layer 142 may comprise silicon nitride, and the material of the insulating layer 132 and the retro-stepped dielectric material portion 65 may be selected from silicon oxide and dielectric metal oxide.

The etching process of selectively removing the second material with respect to the first material and the outermost layer of the ring-shaped ferroelectric dielectric layer 500 may be a wet etching process using a wet etching solution, or may be a vapor phase (dry) etching process of introducing an etchant into the backside trench 79 in a vapor phase. For example, if the sacrificial material layer 142 comprises silicon nitride, the etching process may be a wet etching process that immerses the exemplary structure in a wet etch bath comprising phosphoric acid, which etches silicon nitride selectively to silicon oxide, silicon, and various other materials employed in the art. The support pillar structures 24, the inversely stepped dielectric material portions 65, and the memory opening fill structures 58 provide structural support when the backside recesses 143 are present within the volume previously occupied by the sacrificial material layer 142.

Each backside recess 143 can be a laterally extending cavity having a lateral dimension greater than a vertical extent of the cavity. In other words, a lateral dimension of each backside recess 143 may be greater than a height of the backside recess 143. A plurality of backside recesses 143 can be formed in the volume of the second material from which the sacrificial material layer 142 is removed. The memory openings in which the memory stack structures 55 are formed are referred to herein as front openings or front cavities, in contrast to the backside recesses 143. In one implementation, the memory array region 1100 includes a single three-dimensional array of NAND strings having multiple device levels disposed above a substrate (109, 110). In this case, each backside recess 143 can define a space for receiving a respective word line of a single three-dimensional NAND string array.

Each backside recess of the plurality of backside recesses 143 may extend substantially parallel to a top surface of the substrate (109, 110). The backside recess 143 may be vertically defined by a top surface of the lower insulating layer 132 and a bottom surface of the cover insulating layer 132. In one implementation, each backside recess 143 is to have a uniform height throughout.

The optional pedestal channel portion 111 and the physically exposed surface portion of the semiconductor material layer 110 can be converted into a dielectric material portion by thermally and/or plasma converting the semiconductor material into a dielectric material. For example, thermal conversion and/or plasma conversion may be employed to convert a surface portion of each pedestal channel portion 111 into a tubular dielectric spacer 116 and to convert each physically exposed surface portion of the layer of semiconductor material 110 into a planar dielectric portion 616. In one embodiment, each tubular dielectric spacer 116 may be topologically homeomorphic, i.e., generally annular. As used herein, an element is topologically homeomorphic to a torus if the shape of the element can continue to stretch without breaking the void or forming a new void into the shape of the torus. The tubular dielectric spacers 116 comprise a dielectric material comprising the same semiconductor element as the pedestal channel portion 111 and additionally comprising at least one non-metallic element, such as oxygen and/or nitrogen, such that the material of the tubular dielectric spacers 116 is a dielectric material. In one implementation, the tubular dielectric spacers 116 may comprise a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material of the pedestal channel portion 111. Likewise, each planar dielectric portion 616 comprises a dielectric material comprising the same semiconductor element as the layer of semiconductor material and additionally comprises at least one non-metallic element, such as oxygen and/or nitrogen, such that the material of the planar dielectric portion 616 is a dielectric material. In one implementation, the planar dielectric portion 616 may comprise a dielectric oxide, a dielectric nitride, or a dielectric oxynitride of the semiconductor material layer 110. The dopants in the drain region 63 and the source region 61 may be activated during the annealing process that forms the planar dielectric portion 616 and the tubular dielectric spacers 116. Alternatively, an additional annealing process may be performed to activate ions in the drain region 63 and the source region 61.

Referring to fig. 26A, at least one metallic material may be deposited in the backside recesses 143 by at least one conformal deposition process. The at least one metallic material may comprise, for example, a metallic barrier metal filler material. The metal barrier layer comprises a conductive metallic material that can act as a diffusion barrier and/or adhesion promoting layer for the metallic filler material to be subsequently deposited. The metal barrier layer may comprise a conductive metal nitride material, such as TiN, TaN, WN, or a stack thereof; or may comprise a conductive metal carbide material such as TiC, TaC, WC, or a stack thereof. In one embodiment, the metallic barrier layer may be deposited by a conformal deposition process such as Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD). The thickness of the metallic barrier layer may be in the range of 2nm to 8nm, such as 3nm to 6nm, although lesser and greater thicknesses may also be employed. In one embodiment, the metallic barrier layer may consist essentially of a conductive metal nitride such as TiN.

A layer of metallic fill material can then be deposited over the metallic barrier layer by a conformal deposition process, which can be, for example, Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), electroless plating, electroplating, or combinations thereof. In one embodiment, the metallic filler material layer may consist essentially of at least one elemental metal. The at least one elemental metal of the metallic fill material layer may be selected from, for example, tungsten, cobalt, ruthenium, titanium, and tantalum. In one embodiment, the metallic filler material layer may consist essentially of a single elemental metal. In one embodiment, a layer of metallic filler material may be used such as WF ₆Is deposited using a fluorine-containing precursor gas. In one embodiment, the metallic filler material layer may be a tungsten layer including a residual content of fluorine atoms as impurities. The layer of metallic fill material is spaced apart from the insulating layer 132 and the memory opening fill structure 58 by a metallic barrier layer that can block diffusion of fluorine atoms therefrom.

A plurality of conductive layers 146 may be formed in the plurality of backside recesses 143, and a continuous layer of conductive material may be formed on the sidewalls of each backside trench 79 and over the contact level dielectric layer 73. Each conductive layer 146 includes a portion of a metal barrier layer and a portion of a metal fill material layer located between a vertically adjacent pair of dielectric material layers, such as a pair of insulating layers 132. The continuous layer of conductive material includes a continuous portion of a metallic barrier layer and a continuous portion of a metallic fill material layer located in the backside trench 79 or over the contact level dielectric layer 73.

Each sacrificial material layer 142 may be replaced by a conductive layer 146. There is a backside cavity in the portion of each backside trench 79 that is not filled with the continuous layer of conductive material. A tubular dielectric spacer 116 laterally surrounds the pedestal channel portion 111. In forming the conductive layer 146, the bottommost conductive layer 146 laterally surrounds each tubular dielectric spacer 116.

The deposited metal material of the continuous layer of conductive material is etched back from the sidewalls of each backside trench 79 and from above the contact level dielectric layer 73, such as by isotropic wet etching, anisotropic dry etching, or combinations thereof. Each remaining portion of the deposited metal material in the backside recesses 143 constitutes a conductive layer 146. Each conductive layer 146 may be a conductive line structure. Thus, sacrificial material layer 142 is replaced by conductive layer 146. The planar dielectric portion 616 may be removed during the removal of the continuous layer of conductive material. A backside cavity exists within each backside trench 79.

Each of the intermediate conductive layers 146 may serve as a combination of a plurality of control gate electrodes at the same level and a word line electrically interconnected (i.e., electrically shorted) with a plurality of control gate electrodes at the same level. The plurality of control gate electrodes within each conductive layer 146 are control gate electrodes of a vertical memory device that includes memory stack structure 55. In other words, each conductive layer 146 may be a word line that serves as a common control gate electrode for multiple vertical memory devices.

The at least one topmost conductive layer 146 may serve as a drain side select gate electrode (SGD). The at least one bottommost conductive layer 146 may serve as a source side select gate electrode (SGS). Optionally, at least one conductive layer 146 located between the SGD and the word line may include a drain-side dummy word line to mitigate impact on drain-side edge memory cells in the memory string. Optionally, at least one additional conductive layer 146 located between the SGS and the word line may include a source side dummy word line to mitigate impact on source side edge memory cells in the memory string.

Referring to fig. 26B and 26C, an alternative embodiment of a region of the fourth exemplary structure containing ferroelectric side interface dielectric layer 530 surrounding memory opening fill structure 58 is shown that can be derived from the fourth exemplary structure shown in fig. 26A. In the implementation of fig. 26B, ferroelectric side interface dielectric layer 530 is formed in memory opening 49 prior to the formation of tubular ferroelectric dielectric layer 500. In the implementation of fig. 26C, prior to forming conductive layer 146, ferroelectric side interface dielectric layer 530 is formed directly on the physically exposed cylindrical outer sidewall sections of tubular ferroelectric dielectric layer 500 of each memory opening fill structure 58 on backside recess 143 and directly on the physically exposed horizontal surfaces of insulating layer 132 and insulating cap layer. Ferroelectric side interface dielectric layer 530 comprises a dielectric material that improves the interface quality and improves the ferroelectric properties of tubular ferroelectric dielectric layer 500 and conductive layer 146. Ferroelectric side interfacial dielectric layer 530 comprises hafnium aluminum oxide, hafnium oxide, or aluminum oxide. The thickness of the channel side interface dielectric layer 522 may be in the range of 1nm to 2 nm.

Referring to fig. 27, a layer of insulating material may be formed in the backside trench 79 and over the contact level dielectric layer 73 by a conformal deposition process. Exemplary conformal deposition processes include, but are not limited to, chemical vapor deposition and atomic layer deposition. The layer of insulating material comprises an insulating material such as silicon oxide, silicon nitride, a dielectric metal oxide, an organosilicate glass, or a combination thereof. In one embodiment, the layer of insulating material may comprise silicon oxide. The layer of insulating material may be formed, for example, by Low Pressure Chemical Vapor Deposition (LPCVD) or Atomic Layer Deposition (ALD). The thickness of the layer of insulating material may be in the range of 1.5nm to 60nm, but lesser and greater thicknesses may also be employed.

An anisotropic etch is performed to remove horizontal portions of the layer of insulating material from over the contact level dielectric layer 73 and the bottom of each backside trench 79. Each remaining portion of the layer of insulating material constitutes an insulating spacer 74. A backside cavity exists within the volume surrounded by each insulating spacer 74. The top surface of the layer of semiconductor material 110 may be physically exposed at the bottom of each backside trench 79.

An upper portion of the layer of semiconductor material 110 extending between the source region 61 and the plurality of pedestal channel portions 111 constitutes the horizontal semiconductor channels 59 of the plurality of field effect transistors. The horizontal semiconductor channels 59 are connected to the plurality of metal dichalcogenide channels 60 by respective pedestal channel portions 111. The horizontal semiconductor channel 59 contacts the source region 61 and the plurality of pedestal channel portions 111. Each source region 61 is formed in an upper portion of a substrate (109, 110). A semiconductor channel (59,111,60) extends between each source region 61 and a respective set of drain regions 63. The semiconductor channel (59,111,60) includes the two-dimensional electron gas channel 60 of the memory stack structure 55.

Backside contact via structures 76 may be formed within each backside cavity. Each contact via structure 76 may fill a respective backside cavity. The contact via structure 76 may be formed by depositing at least one conductive material in the remaining unfilled volume of the backside trench 79 (i.e., the backside cavity). For example, the at least one conductive material may include a conductive pad 76A and a conductive fill material portion 76B. The conductive pad 76A may comprise a conductive metal pad such as TiN, TaN, WN, TiC, TaC, WC, alloys thereof, or stacks thereof. The thickness of the conductive pad 76A may be in the range of 3nm to 30nm, although lesser and greater thicknesses may also be employed. The conductive filler material portion 76B may comprise a metal or metal alloy. For example, the conductive fill material portion 76B may comprise W, Cu, Al, Co, Ru, Ni, alloys thereof, or stacks thereof.

The at least one conductive material may be planarized using the contact level dielectric layer 73 overlying the alternating stack (132,146) as a stop layer. If a Chemical Mechanical Planarization (CMP) process is employed, the contact level dielectric layer 73 may serve as a CMP stop layer. Each remaining continuous portion of the at least one conductive material in the backside trench 79 constitutes a backside contact via structure 76. The backside contact via structure 76 extends through the alternating stack (132,146) and contacts the top surface of the source region 61.

Referring to fig. 28A and 28B, additional contact via structures (88,86,8P) may be formed through the contact level dielectric layer 73 and optionally through the retrograde dielectric material portion 65. For example, a drain contact via structure 88 may be formed through the contact level dielectric layer 73 on each drain region 63. Word line contact via structures 86 may be formed on conductive layer 146 through contact level dielectric layer 73 and through retrograde stepped dielectric material portion 65. The peripheral device contact via structures 8P may be formed directly on the corresponding nodes of the peripheral devices through the retro-stepped dielectric material portions 65.

Referring to all embodiments of the present disclosure, a ferroelectric memory device includes a two-dimensional electron gas channel 60, a gate electrode (46,146), and a ferroelectric memory element (21,22,23,500) located between the gate electrode and the two-dimensional electron gas channel.

Each construction of the second through fourth example structures of the present disclosure may include an alternating stack of insulating layers 132 and conductive layers 146 (one of which includes the gate electrode mentioned above) over a substrate (109,110), a memory opening 49 extending vertically through the alternating stack, a two-dimensional electron gas channel 60 located inside the memory opening, a ferroelectric memory element (e.g., a portion of layer 500) located between the channel 60 and the conductive layer 146, and a dielectric core 62 surrounded by the channel.

In one embodiment, the two-dimensional electron gas channel 60 comprises a metal dichalcogenide channel. In one implementation, the ferroelectric memory element includes a portion of the tubular ferroelectric dielectric layer 500 that extends vertically through the alternating stacked conductive layers 146.

In one embodiment, the tubular ferroelectric dielectric layer 500 comprises: a first ferroelectric dielectric layer 504 having a first band gap energy; and a second dielectric layer 506 having a second band gap energy greater than the first band gap energy and located between the first ferroelectric dielectric layer 504 and the metal dichalcogenide channel.

In one embodiment, the first ferroelectric dielectric layer 504 comprises a first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer; and the second dielectric layer 506 comprises a second hafnium aluminum oxide or hafnium zirconium aluminum oxide layer having a higher aluminum concentration than the first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer. In one embodiment, the first ferroelectric dielectric layer 504 has Hf _1.5(1-α-β)Zr_1.5βAl_2αO₃Wherein α is in the range of 0.01 to 0.2, and β is in the range of 0 to 0.2; and the second dielectric layer 506 has Hf_1.5γZr_1.5δAl_2(1-γ-δ)O₃Wherein γ is in the range of 0.05 to 0.2, and δ is in the range of 0 to 0.2.

In one embodiment, the metal dichalcogenide channel has a thickness in a range of 1 monolayer to 5 monolayers. In one embodiment, the metal dichalcogenide channel comprises a metal having Mo_1-xW_xS_2-ySe_yA material of composition, wherein x is in the range of 0 to 1, and y is independent of x and in the range of 0 to 2.

In one embodiment, the substrate (109,110) includes a layer of semiconductor material 110. The bottom end of the metal dichalcogenide channel is electrically connected to the layer of semiconductor material. In one embodiment, a single three-dimensional memory device includes a pedestal channel portion 111 at a bottom end of the memory opening 49 and epitaxially aligned with the layer of semiconductor material 110, wherein the metal dichalcogenide channel contacts a top surface of the pedestal channel portion 111.

In one embodiment, a single three-dimensional memory device includes a drain region 63 contacting an upper end of a metal dichalcogenide channel. In one embodiment, the drain region 63 includes a ring-shaped metal-doped dichalcogenide drain portion 631. In one embodiment, the drain region 63 further comprises a stack of nickel, nickel silicide, N + doped polysilicon, titanium and gold layers, or nickel and gold layers, such as a stack of titanium 632 and gold 634 embedded within the ring-shaped doped metal dichalcogenide drain portion 631; and a doped semiconductor drain portion 630 embedded within the stack of titanium layer 632 and gold layer 634. The drain region 63 includes a doped semiconductor drain portion 630 that contacts the inner sidewall of the annular doped metal dichalcogenide drain portion 631. In one embodiment, drain region 63 includes a stack of titanium layer 632 and gold layer 634; and titanium layer 632 contacts the sidewalls of the metal dichalcogenide channel.

In one implementation, the ferroelectric memory element is in direct contact with conductive layer 146. In one embodiment, the memory device of the present disclosure may be a single three-dimensional memory device including a vertical NAND device located over a substrate (109,110), and conductive layer 146 may include or be electrically connected to a respective word line of the vertical NAND device. The substrate (109,110) may comprise a silicon substrate. A vertical NAND device can include a single three-dimensional array of NAND strings over a silicon substrate. At least one memory cell in a first device level of the three-dimensional NAND string array is located above another memory cell in a second device level of the three-dimensional NAND string array. The silicon substrate may contain integrated circuitry including driver circuitry for the memory devices positioned thereon.

A single three-dimensional NAND string array can include multiple metal dichalcogenide channels. At least one end portion of each metal dichalcogenide channel of the plurality of metal dichalcogenide channels extends substantially perpendicular to a top surface of the substrate (109, 110). In one embodiment, the plurality of metal dichalcogenide channels may be connected in a parallel connection with a common horizontal semiconductor channel portion that is a portion of the semiconductor material layer 110 extending between the source region 61 and the pedestal channel portion 111. A single three-dimensional NAND string array can include multiple memory elements (e.g., memory cells including portions of the tubular ferroelectric dielectric layer 500 present within each memory stack structure 55). Each memory element may be located adjacent a respective one of a plurality of metal dichalcogenide channels (i.e., two-dimensional electron gas channels 60). A single three-dimensional NAND string array may include a plurality of control gate electrodes having a stripe shape extending substantially parallel to a top surface of a substrate (109, 110).

The two-dimensional metal dichalcogenide channel can have a thickness of no greater than five atomic layers, and even more preferably no greater than three atomic layers. Such thin metal dichalcogenide materials exhibit the characteristic of a two-dimensional channel providing high charge carrier mobility. For example, MoS₂The channel may have up to about 200cm²Field-limited mobility of/Vs. This is more than an order of magnitude higher than the field-limited mobility in conventional polysilicon channels.

The higher electron mobility transport may be advantageously used to increase the on-current of the memory stack structure and increase the signal-to-noise ratio during a read operation of the memory stack structure. Low leakage and low gate induced drain leakage ("GIDL") can cause lower power and less program and read disturb. Lower leakage, therefore, better boosting and less program disturb can result in less power consumption. Additionally or alternatively, the operating voltage may be reduced, thus cutting power consumption.

According to another aspect of the present disclosure, any of the ferroelectric memory elements of the present disclosure, such as ferroelectric memory element 21, backside ferroelectric memory element 22, wound ferroelectric memory element 23, and/or ferroelectric dielectric layer 504 may comprise two-dimensional van der waals ferroelectric material. This material provides a van der waals heterostructure with two-dimensional electron-gas channels 60. Due to the two-dimensional nature of the materials therein, such structures may provide an ideal insulator/semiconductor interface without dangling bonds (with reduced dangling bonds) and improve device reliability. The smaller thickness of the ferroelectric memory element and the semiconductor channel improves device scalability. At the same time, higher mobility of the two-dimensional semiconductor channel may provide higher cell current and enhanced performance. The thickness of the two-dimensional ferroelectric material may have a thickness in the range of a single monolayer to 5 monolayers.

Non-limiting examples of two-dimensional ferroelectric materials include CuInP₂S₆、a-In₂Se₃g-SbP, g-SbAs, and a group IV monosulfide material having the formula MX, wherein M is selected from Ge, Sn, or Pb, and X is selected from S, Se or Te.

For example, α -In₂Se₃Is a ferroelectric substance and has a van der waals structure, maintains ferroelectric characteristics in a single monolayer having a thickness of about 1nm, maintains ferroelectric characteristics in a multilayer structure, and has a rhombus R3m structure, the rhombus R3m structure being non-centrosymmetric and supporting polarization switchable by an external electric field.

In another example, γ -SbX (X ═ As, P) may be formed As a van der waals two-dimensional ferroelectric film having a thickness of a single monolayer or 2 to 3 monolayers. Based on first principle calculations, ferroelectric memory devices of the present disclosure employing γ -SbX (X ═ As, P) are expected to exhibit about 3.80 × 10^-10C m^-1(for. gamma. -SbAs) or 3.47X 10^-10C m^-1Excellent two-dimensional ferroelectricity for polarization (for γ -SbP). In addition, γ -SbX (X ═ As, P) can operate at very high temperatures. For example, the ferroelectricity of a single layer of γ -SbAs or γ -SbP remains good over a temperature range of up to 600K or 700K. Thus, γ -SbX can be used as a robust ferroelectric material in a two-dimensional ferroelectric material-two-dimensional semiconductor material heterostructure to form Various non-volatile memory devices of the present disclosure may include a three-dimensional NAND memory device or a three-dimensional NOR memory device.

In yet another example, the two-dimensional van der waals ferroelectric material may include cunnp₂S₆(CIPS). In one example, the CIPS may be deposited by chemical vapor deposition or conformal atomic layer deposition, for example using corresponding stoichiometric element precursors. The thickness of the CIPS may be in the range of 2nm to 6 nm. The deposited film may be annealed at a high temperature in a temperature range of 650 degrees celsius to 750 degrees celsius for a duration in a range of 10 minutes to 30 minutes.

In one implementation, an optional ferroelectric side interface dielectric layer 530 may be formed between the gate or word line and the two-dimensional van der waals ferroelectric material. Ferroelectric side interface dielectric layer 530 can comprise aluminum oxide. For example, if two-dimensional van der waals ferroelectric material is used as ferroelectric dielectric layer 504 in the three-dimensional NAND device shown in fig. 28A, ferroelectric side interface dielectric layer 530 may be formed inside backside recess 143 shown in fig. 25, as shown in fig. 26A, prior to depositing conductive layer 146 in backside recess 143 on the dielectric intermediate layer. Accordingly, a structure similar to that of fig. 26C can be formed. Alternatively, ferroelectric side interface dielectric layer 530 may be formed in memory opening 49 before tubular ferroelectric dielectric layer 500 is formed into a structure similar to that of fig. 26B.

Referring to fig. 29, a fifth exemplary structure according to a ninth embodiment of the present disclosure is shown, which may be derived from the fifth exemplary structure of fig. 15. In this case, the semiconductor material layer 110 may or may not be employed. An insulating substrate may be used instead of the substrate semiconductor layer 109. At least one instance of a unit layer stack including the device isolation level insulating layer 332, the source level sacrificial layer 342, the channel level insulating layer 232, and the drain level sacrificial layer 442 may be formed over the substrate semiconductor layer 109. Multiple instances of a cell layer stack may be formed over a substrate. The total number of cell layer stacks may be in the range of 1 to 512, such as 2 to 128, although fewer and greater numbers of cell layer stacks may also be employed.

Each source-level sacrificial layer 342 and each drain-level sacrificial layer 442 comprises a sacrificial material that is selectively removable with respect to the material of the device isolation level insulating layer 332 and the channel level insulating layer 232. Further, each channel-level insulating layer 232 comprises a material that provides a higher etch rate in an etchant that selectively etches each device isolation level insulating layer 332 for each source-level sacrificial layer 342 and each drain-level sacrificial layer 442.

In one embodiment, a vertical stack comprising multiple instances of a cell layer stack may be derived from the alternating stack (132,142) of the fifth exemplary structure by employing each odd-numbered (as counted from the bottom with an integer 1) sacrificial material layer 142 as a source-level sacrificial layer 342, by employing each even-numbered sacrificial material layer 142 as a drain-level sacrificial layer 442, and by modifying the material composition of each even-numbered insulating layer 132 to provide a higher etchant etch rate than each odd-numbered insulating layer 132. In this case, the odd insulating layer 132 in the fifth exemplary structure may be the device isolation level insulating layer 332 in the fifth exemplary structure, and the even insulating layer 132 in the fifth exemplary structure may be the channel level insulating layer 232.

Alternatively, the positions of the source-level sacrificial layer 342 and the drain-level sacrificial layer 442 may be reversed. In this case, each odd-numbered (as counted from the bottom with an integer of 1) sacrificial material layer 142 in the fifth exemplary structure may serve as the source-level sacrificial layer 342 in the fifth exemplary structure, and each even-numbered sacrificial material layer 142 may serve as the drain-level sacrificial layer 442 in the fifth exemplary structure.

In an illustrative example, the source level sacrificial layer 342 and the drain level sacrificial layer 442 may comprise silicon nitride, the device isolation level insulating layer 332 may comprise undoped silicate glass (such as TEOS oxide), and the channel level insulating layer 232 may comprise doped silicate glass (such as borosilicate glass, borophosphosilicate glass, or fluorosilicate glass) or organosilicate glass. In this case, the channel-level insulating layer 232 may have an etch rate of at least 5 times (such as 10 times to 1,000 times) the etch rate of the undoped silicate glass in 100:1 dilute hydrofluoric acid.

In general, at least one instance of a cell layer stack may be formed over a substrate. The cell layer stack may include, from bottom to top or from top to bottom, a device isolation level insulating layer 332, a source level sacrificial layer 342, a channel level insulating layer 232, and a drain level sacrificial layer 442. In one embodiment, the at least one instance of the cell layer stack includes a vertical stack of multiple instances of the cell layer stack. An insulating cap layer 70 may be formed over at least one instance of the cell layer stack.

Referring to fig. 30, the processing steps of fig. 17 may be performed to form a stepped surface and a reverse stepped dielectric material portion 65.

Referring to fig. 31, the processing steps of fig. 18A and 18B may be performed to form the memory openings 49 and the support openings 19. The formation of the drain select level isolation structure 72 may be omitted.

Referring to fig. 32, an isotropic etching process is performed, which etches the material of the channel-level insulating layer 232 at a higher etch rate than the material of the device isolation level insulating layer 332 and selective to the materials of the source-level sacrificial layer 342 and the drain-level sacrificial layer 442. If the source-level sacrificial layer 342 and the drain-level sacrificial layer 442 comprise silicon nitride, if the device isolation level insulating layer 332 comprises undoped silicate glass, and if the channel-level insulating layer 232 comprises doped silicate glass, a wet etch process with dilute hydrofluoric acid (such as 100:1 dilute hydrofluoric acid) may be performed to laterally recess the cylindrical sidewall segments of the channel-level insulating layer 232 selective to the source-level sacrificial layer 342, the drain-level sacrificial layer 442, and the device isolation level insulating layer 332.

The channel level recess 249 is formed by selectively laterally recessing the channel level insulating layer 232 for each source level sacrificial layer 342, each drain level sacrificial layer 442, and each device isolation level insulating layer 332. A channel level recess 249 is formed around each memory opening 49 and around each support opening 19 at each level of the channel level insulating layer 232. The channel level recess 249 comprises a cylindrical void from which material of the channel level insulating layer 232 is removed. In one embodiment, the lateral recess distance of the isotropic etching process is selected in the range of 1 monolayer to 5 monolayers of the two-dimensional electron gas channel material to be subsequently deposited.

Referring to fig. 33, a two-dimensional electron gas channel 60 can be formed within the volume of the channel level recess 249 by depositing a metal dichalcogenide layer having a thickness in the range of 1 monolayer to 5 monolayers, and by anisotropically etching a portion of the metal dichalcogenide layer that is outside the volume of the channel level recess 249. The metal dichalcogenide layer may be deposited using any of the methods described above. After the anisotropic etching process, each remaining cylindrical portion of the metal chalcogenide layer constitutes a two-dimensional electron-gas channel 60, which may be a cylindrical two-dimensional electron-gas channel. A vertical stack of two-dimensional cylindrical electron gas channels 60 may be formed within each memory opening 49.

In one implementation, each of the two-dimensional cylindrical electron gas channels 60 comprises a metal dichalcogenide channel. In one implementation, each of the at least one two-dimensional cylindrical electron gas channel within each memory opening 49 has a lateral thickness in the range of 1 monolayer to 5 monolayers, and includes a two-dimensional electron gas therein. In one implementation, each of the at least one two-dimensional cylindrical electron gas channel in each memory opening 49 includes a channel having Mo _1-xW_xS_2-ySe_yA material of composition, wherein x is in the range of 0 to 1, and y is independent of x and in the range of 0 to 2.

Referring to fig. 34A and 34B, a tubular ferroelectric dielectric layer 500 may be formed by conformally depositing at least one ferroelectric dielectric material on the physically exposed sidewalls of the two-dimensional cylindrical electron gas channel 60, the source level sacrificial layer 342, the drain level sacrificial layer 442, and the device isolation level insulating layer 332. A tubular ferroelectric dielectric layer 500 may be formed over the inner cylindrical sidewall of the two-dimensional cylindrical electron gas channel 60.

The tubular ferroelectric dielectric layer 500 may comprise any of the constructions described above and may be formed in any of the manners described above. In one implementation, tubular ferroelectric dielectric layer 500 can comprise a layer stack of first ferroelectric dielectric layer 504 and second dielectric layer 506 such that second dielectric layer 506 is deposited directly on the inner cylindrical sidewall of the vertical stack of two-dimensional cylindrical electron gas channels 60 in each memory opening 49 and first ferroelectric dielectric layer 504 is deposited on second dielectric layer 506. The thickness and material composition of the second dielectric layer 506 may be the same as previously described embodiments. The thickness and material composition of the first ferroelectric dielectric layer 504 may be the same as previously described embodiments.

In one implementation, each of the tubular ferroelectric dielectric layers 500 includes a first ferroelectric dielectric layer 504 having a first band gap energy, and a second dielectric layer 506 having a second band gap energy greater than the first band gap energy and located between the first ferroelectric dielectric layer 504 and the two-dimensional electron gas channel 60 within the same memory opening 49. In one embodiment, the first ferroelectric dielectric layer 504 comprises a first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer; and the second dielectric layer 506 comprises a second hafnium aluminum oxide or hafnium zirconium aluminum oxide layer having a higher aluminum concentration than the first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer. In one embodiment, the first ferroelectric dielectric layer 504 may have Hf_1.5(1-α-β)Zr_1.5βAl_2αO₃Wherein α is in the range of 0.01 to 0.2 and β is in the range of 0 to 0.2, and the second dielectric layer 506 may have Hf_1.5γZr_1.5δAl_2(1-γ-δ)O₃Wherein γ is in the range of 0.05 to 0.2, and δ is in the range of 0 to 0.2.

In another implementation, each tubular ferroelectric dielectric layer 500 comprises a two-dimensional layer of van der waals ferroelectric material comprising a material selected from the group consisting of cunnp₂S₆、a-In₂Se₃g-SbP, g-SbAs, or a group IV monosulfide material having the formula MX, wherein M is selected from Ge, Sn or Pb, and X is selected from S, Se or Te.

Ferroelectric side interface dielectric layer 530 can optionally be formed by conformal deposition of a dielectric material. The ferroelectric-side interface dielectric layer 530 (if present) comprises a dielectric material that improves the quality of the interface. Ferroelectric side interfacial dielectric layer 530 comprises hafnium aluminum oxide, hafnium oxide, or aluminum oxide. The thickness of the ferroelectric side interface dielectric layer 530 may be in the range of 1nm to 2 nm.

Word line 546 may be formed over the inner cylindrical sidewalls of tubular ferroelectric dielectric layer 500 within each memory opening 49 (e.g., on ferroelectric side interface dielectric layer 530, if layer 530 is omitted, or directly on tubular ferroelectric dielectric layer 500). A wordline 546 may extend vertically through each source level sacrificial layer 342 and each drain level sacrificial layer 442 within at least one instance of the cell layer stack. The word line may include a metal material such as titanium nitride, tantalum nitride, tungsten nitride, titanium, tantalum, tungsten, molybdenum, ruthenium, cobalt, copper, or any other transition metal element or alloy thereof. The wordlines 546 may be formed by conformal deposition of at least one metallic material. The lateral thickness of each wordline 546 may be in the range of 6nm to 100nm, although lesser and greater thicknesses may also be employed.

Where there is a cavity in each memory opening 49 after the word line 546 is formed, dielectric material may be deposited in the remaining volume of the memory opening 49. For example, silicon oxide may be deposited in the cavity within the memory opening 49 by a conformal deposition process. The dielectric material, the metallic material of the word lines 546, the optional ferroelectric-side interface dielectric layer 530, and the excess portions of the tubular ferroelectric dielectric layer 500 may be removed from above a horizontal plane including the top surface of the insulating cap layer 70 by a planarization process. The planarization process may include a Chemical Mechanical Planarization (CMP) process and/or a recess etch process. Each remaining portion of the dielectric material constitutes a dielectric core 62.

The collection of all material portions that fill the memory openings 49 constitutes the memory opening fill structures 358. The collection of all material portions filling the support openings 19 constitutes a support post structure 324. Each memory opening fill structure 358 and each support pillar structure 324 can comprise a vertical stack of two-dimensional cylindrical electron gas channels 60, tubular ferroelectric dielectric layer 500, optional ferroelectric side interface dielectric layer 530, word lines 546, and optional dielectric cores 62.

Referring to fig. 35A and 35B, the processing steps of fig. 24A-24B may be performed to form a contact level dielectric layer 73 and backside trenches 79.

Referring to fig. 36, an isotropic etching process may be performed to selectively etch the source-level sacrificial layer 342 and the drain-level sacrificial layer 442 with respect to the device isolation level insulating layer 332 and the channel level insulating layer 232. For example, if the source-level sacrificial layer 342 and the drain-level sacrificial layer 442 include silicon nitride, if the device isolation level insulating layer 332 includes undoped silicate glass, and if the channel-level insulating layer 232 includes doped silicate glass, a wet etching process using hot phosphoric acid may be performed to etch the source-level sacrificial layer 342 and the drain-level sacrificial layer 442. An active level backside recess (343,443) is formed in the volume from which the source level sacrificial layer 342 and the drain level sacrificial layer 442 are removed. The active level backside recess (343,443) includes a source level backside recess 343 formed in the volume from which the source level sacrificial layer 342 is removed, and a drain level backside recess 443 formed in the volume from which the drain level sacrificial layer 442 is removed.

Referring to fig. 37, the processing steps of fig. 26A and 26B may be performed to deposit at least one conductive material in the active level backside recesses (343,443) and to remove excess portions of the at least one conductive material from within the backside trenches 79 and over the contact level dielectric layer 73. The at least one conductive material may include a metal nitride liner (346A,446A) comprising a metal nitride material, such as TiN, TaN, and/or WN, and a metal fill material portion (346B,446B) comprising a metal fill material, which may comprise an elemental metal, such as W, Mo, Ru, Co, Cu, or any other transition metal, or an intermetallic alloy. A metal source layer 346 is formed in each source level backside recess 343 and a metal drain layer 446 is formed in each drain level backside recess 443. Each metal source layer 346 may include a source level metal nitride liner 346A and a source level metal fill material portion 346B. Each metal drain layer 446 may include a drain level metal nitride liner 446A and a drain level metal fill material portion 446B.

Each source level sacrificial layer 342 and each drain level sacrificial layer 442 may be replaced by a metal source layer and a metal drain layer, respectively. Each metal source layer 346 and each metal drain layer 446 may be formed directly on the annular horizontal surface of a respective subset of the two-dimensional cylindrical electron gas channel 60, the respective subset being located directly on a respective one of the channel level insulating layers 232. In one implementation, each metal source layer 346 and each metal drain layer 446 may be formed directly on the annular horizontal surface of all two-dimensional cylindrical electron gas channels 60 that contacts the same channel level insulating layer 232 between an adjacent pair of backside trenches 79.

Referring to fig. 38A and 38B, a dielectric material may be deposited in the backside trench 79 to form the dielectric wall structure 376. Contact via structures (588,583,585,8P) may be formed through the contact level dielectric layer 73, and optionally through the retro-stepped dielectric material portion 65. For example, word line contact via structures 588 may be formed through the contact level dielectric layer 73 on each word line 546. A source contact via structure 583 may be formed on metal source layer 346 through contact level dielectric layer 73 and through retrograde stepped dielectric material portion 65. A drain contact via structure 585 may be formed on the metal drain layer 446 through the contact level dielectric layer 73 and through the retro-stepped dielectric material portion 65. The peripheral device contact via structures 8P may be formed directly on the corresponding nodes of the peripheral devices through the retro-stepped dielectric material portions 65.

In an alternative embodiment, instead of replacing the source level sacrificial layer 342 and the drain level sacrificial layer 442 with respective metal source layer 346 and metal drain layer 446, conductive source and drain layers (346,446) are formed as part of the initial cell layer stack (232,332,346,446). In this alternative implementation, each conductive source and drain layer may comprise a heavily doped polysilicon layer. If desired, a thinner (e.g., 1nm to 2nm thick) optional metal interface improvement layer can be formed in contact with the heavily doped polysilicon layer.

Each two-dimensional cylindrical electron gas channel 60 is located between and contacts a vertically adjacent pair of metal source and drain layers 346, 446. Each two-dimensional cylindrical electron gas channel 60 is controlled by a gate electrode comprising an adjacent portion of one of the wordlines 546. The wordlines 546 are independently controlled. The portions of the tubular ferroelectric dielectric material layer 500 located adjacent to a set of two-dimensional cylindrical electron gas channels 60 can be independently programmed to provide a two-dimensional ferroelectric NOR array. The vertical stack of two-dimensional ferroelectric NOR arrays located between adjacent pairs of dielectric wall structures 376 constitutes a three-dimensional ferroelectric NOR array.

Referring to all structures related to the fifth exemplary structure of the present disclosure, a memory device is provided, the memory device comprising at least one cell layer stack located over a substrate, wherein the cell layer stack comprises a metal source layer 346, a channel level insulating layer 232, a metal drain layer 446 and a device isolation layer 332; a plurality of memory openings 49 extending vertically through at least one cell layer stack (346,232,436,332); and memory opening fill structures 358 within respective ones of the plurality of memory openings 49, wherein each of the memory opening fill structures 358 comprises a tubular ferroelectric dielectric layer 500 and at least one two-dimensional cylindrical electron gas channel 60 extending vertically between the metal source layer 346 and the metal drain layer 446 of at least one cell layer stack (346,232,436,332).

In one embodiment, each channel-level insulating layer 232 contacts the outer cylindrical sidewall of a respective two-dimensional cylindrical electron gas channel 60.

In one implementation, tubular ferroelectric dielectric layer 500 contacts the cylindrical surface of each of metal source layers 346 and the cylindrical surface of each of metal drain layers 446.

In one implementation, word lines 546 may be formed over the inner cylindrical sidewalls of tubular ferroelectric dielectric layer 500 within each memory opening 49. A word line 546 may extend vertically through each metal source layer 346 and each metal drain layer 446 within at least one cell layer stack (346,232,436,332).

In one embodiment, the at least one cell layer stack (346,232,436,332) includes a vertical stack of multiple cell layer stacks (346,232,436,332).

In one embodiment, each of the at least one two-dimensional cylindrical electron gas channel 60 comprises a metal dichalcogenide channel.

In one embodiment, each of the at least one two-dimensional cylindrical electron gas channel 60 has a lateral thickness in the range of 1 monolayer to 5 monolayers and includes a two-dimensional electron gas therein; and each of the at least one two-dimensional cylindrical electron gas channel 60 comprises a channel having Mo _1-xW_xS_2-ySe_yA material of and/or consisting essentially of said material, wherein x is in the range of 0 to 1, and y is independent of x and in the range of 0 to 2. In one embodiment, the tubular ferroelectric dielectric layer 500 comprises a two-dimensional van der waals ferroelectric material layer comprising a material selected from the group consisting of cunnp₂S₆、a-In₂Se₃A ferroelectric material of g-SbP, g-SbAs, or a group IV single chalcogenide material having the formula MX, wherein M is selected from Ge, Sn, or Pb, and X is selected from S, Se or Te.

Referring to fig. 39, a first configuration of a sixth exemplary structure according to a tenth embodiment of the present disclosure is shown. The sixth exemplary structure includes a semiconductor substrate 709 including a semiconductor material layer. The layer of semiconductor material may comprise a layer of monocrystalline semiconductor material or polycrystalline semiconductor material. The semiconductor substrate 709 may comprise at least one elemental semiconductor material, such as silicon, germanium, or a silicon-germanium alloy; or may comprise a compound semiconductor material such as a III-V compound semiconductor material or a II-V compound semiconductor material.

The two-dimensional electron gas channel layer 60L may be formed on the top surface of the semiconductor substrate 709. The two-dimensional electron gas channel layer 60L may include any of the materials used for the two-dimensional electron gas channel layer 60L described above, and may have the same thickness as the two-dimensional electron gas channel layer 60L described above.

A layer stack of a two-dimensional van der waals ferroelectric material layer 740, an optional ferroelectric side interface dielectric layer 530, and a gate electrode material layer 746 may be sequentially deposited over the two-dimensional electron gas channel layer 60L and may be photolithographically patterned to form the gate stack. A two-dimensional van der Waals ferroelectric material layer 740 formed on the second layerAnd a dimensional electron gas channel 60. The two-dimensional van der waals ferroelectric material layer 740 may have the same thickness and the same material composition as any of the two-dimensional van der waals ferroelectric material layers described above. In one embodiment, the two-dimensional van der waals ferroelectric material layer 740 comprises and/or consists essentially of: selected from CuInP₂S₆、a-In₂Se₃g-SbP, g-SbAs, or a group IV monosulfide material having the formula MX, wherein M is selected from Ge, Sn or Pb, and X is selected from S, Se or Te.

The ferroelectric-side interfacial dielectric layer 530 may have the same material composition and the same thickness as in the previously described embodiments. In one embodiment, the ferroelectric side interface dielectric layer 530 comprises and/or consists essentially of: hafnium aluminum oxide, hafnium oxide, or aluminum oxide, and contacts the two-dimensional van der waals ferroelectric material layer 740 and the gate electrode 746.

The remaining patterned portion of the gate electrode material layer includes a gate electrode 746, which may comprise a doped semiconductor material or at least one metal material, such as a metal nitride material (e.g., TiN, TaN, and/or WN); and/or at least one elemental metal or intermetallic alloy.

Dopants may be implanted into end portions of the two-dimensional electron gas channel layer 60L and underlying portions of the semiconductor substrate 709 using the gate electrode 746 as a mask to form a source region 732 and a drain region 738. Each of the source region 732 and the drain region 738 may include a respective doped portion of the two-dimensional electron gas channel layer 60L and a doped portion of the semiconductor substrate 709. The portion of the two-dimensional electron gas channel layer 60L that does not belong to the source region 732 or the drain region 738 constitutes the two-dimensional electron gas channel 60.

A planarization dielectric layer 760 comprising a dielectric material, such as silicon oxide and/or silicon nitride, may be deposited over gate electrode 746 and may be planarized to provide a planar top surface. A contact via structure (782,785,788) may be formed through the planarization dielectric layer 760. The contact via structures (782,785,788) may include a source contact via structure 782 that contacts the top surface of source region 732, a drain contact via structure 788 that contacts the top surface of drain region 738, and a gate contact via structure 785 that contacts the top surface of gate electrode 746.

Referring to fig. 40, a second configuration of the sixth exemplary structure is shown, which can be derived from the first configuration of the sixth exemplary structure shown in fig. 39 by using the insulating substrate 719 instead of the semiconductor substrate 701. In this case, the source region 732 and the drain region 738 may be confined within the two-dimensional electron gas channel layer 60L.

Referring to fig. 41, a third configuration of a sixth exemplary structure is shown that may be derived from the second configuration of the sixth exemplary structure shown in fig. 40 by forming a channel side interface dielectric layer 522. The channel side interfacial dielectric layer 522 may have the same material composition and the same thickness as in the previously described embodiments. The channel-side interface dielectric layer 522 may comprise and/or may consist essentially of: hafnium aluminum oxide, hafnium oxide, or aluminum oxide, and may contact a substrate, such as insulating substrate 719, and two-dimensional electron gas channel 60.

Referring to fig. 42, a fourth configuration of the sixth exemplary structure may be derived from any of the first, second, and third configurations of the sixth exemplary structure by forming a plurality of gate stacks (740,530,746) arranged in a direction connecting the source region 732 and the drain region 738, instead of a single gate stack (740,530,746) over the two-dimensional electron gas channel 60. Gate electrode 746 can be independently controlled to provide a NAND ferroelectric memory string.

Referring to fig. 43, a fifth configuration of the sixth exemplary structure may be derived from the first, second, and third configurations of the sixth exemplary structure by forming a plurality of gate stacks (740,530,746) arranged perpendicular to the direction connecting the source and drain

regions

732, 738 instead of a single gate stack (740,530,746) over the two-dimensional electron gas channel 60. Gate electrode 746 can be independently controlled to provide a NOR ferroelectric memory string. The two-dimensional electron gas channel 60 may include a plurality of channel regions (C1, C2, C3) connected in parallel connection between the source region 732 and the drain region 738.

Referring to all figures relating to the sixth exemplary structure, there is provided a memory device comprising: a two-dimensional electron gas channel 60 on the substrate; (709,719); a source region 732 and a drain region 738 at end portions of the two-dimensional electron gas channel 60; a two-dimensional van der Waals ferroelectric material layer 740 on the two-dimensional electron gas channel 60 and comprising a material selected from CuInP₂S₆、a-In₂Se₃A ferroelectric material of g-SbP, g-SbAs, or a group IV monosulfide material having the formula MX, wherein M is selected from Ge, Sn or Pb, and X is selected from S, Se or Te; and at least one gate electrode 746 located over the two-dimensional layer of van der waals ferroelectric material 740.

In one embodiment, the memory device includes a ferroelectric side interface dielectric layer 530 comprising hafnium aluminum oxide, hafnium oxide, or aluminum oxide and contacting the two-dimensional van der waals ferroelectric material layer 740 and at least one gate electrode 746.

In one embodiment, substrate 709 includes a layer of semiconductor material; and the source region 732 and the drain region 738 comprise respective doped portions of the layer of semiconductor material 709. In another implementation, the substrate 719 includes a dielectric material.

In one embodiment, the source region 732 and the drain region 738 comprise respective portions of the two-dimensional electron gas channel layer 60L that comprise the material of the two-dimensional electron gas channel 60 and additionally comprise dopant atoms; source contact via structure 782 contacts the top surface of source region 732; and the drain contact via structure 788 contacts the top surface of the drain region 738.

In one embodiment, the at least one gate electrode 746 comprises a plurality of gate electrodes 746, and the plurality of gate electrodes 746 are arranged in a direction connecting the source region 732 and the drain region 738 to provide a NAND memory device, or in a direction perpendicular to the direction connecting the source region 732 and the drain region 738 to provide a NOR memory device.

In general, various embodiments of the present disclosure may provide ferroelectric memory devices having superior device characteristics compared to prior art ferroelectric memory devices. For example, the two-dimensional channel has an improved interface with the ferroelectric material with reduced or no dangling bonds. The improved interface quality improves device reliability. This interface is further improved if two-dimensional van der waals ferroelectric materials are used. In addition, the smaller thickness of both the two-dimensional channel and the ferroelectric material also improves device scalability, while the higher mobility of the two-dimensional channel results in higher cell current and therefore better device performance.

While the foregoing refers to certain preferred embodiments, it is to be understood that the disclosure is not so limited. Various modifications to the disclosed embodiments will be apparent to those skilled in the art, and such modifications are intended to be within the scope of the present disclosure. Where embodiments employing specific structures and/or configurations are shown in the present disclosure, it is understood that the present disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent, provided that such substitutions are not explicitly prohibited or otherwise considered to be impossible by one of ordinary skill in the art. All publications, patent applications, and patents cited herein are incorporated by reference in their entirety.

Claims

1. A ferroelectric memory device comprising:

a two-dimensional electron gas channel;

a gate electrode; and

a ferroelectric element located between the gate electrode and the two-dimensional electron gas channel,

wherein the memory device comprises a single three-dimensional memory device comprising:

an alternating stack of insulating layers and conductive layers formed over the substrate, wherein the gate electrode comprises one of the conductive layers;

a reservoir opening extending vertically through the alternating stack;

the two-dimensional electron gas channel is positioned inside the opening of the memory; and

a dielectric core surrounded by the channel.

2. The ferroelectric memory device of claim 1, wherein the ferroelectric memory element located between the gate electrode and the two-dimensional electron gas channel comprises one of a plurality of ferroelectric memory elements located between the channel and the conductive layer.

3. The unitary three-dimensional memory device of claim 2, wherein the two-dimensional electron gas channel comprises a metal dichalcogenide channel.

4. The single three-dimensional memory device of claim 3, wherein:

The ferroelectric memory element comprises a portion of a tubular ferroelectric dielectric layer extending vertically through the alternating stack of conductive layers; and is provided with

The tubular ferroelectric dielectric layer includes:

a first ferroelectric dielectric layer having a first band gap energy; and

a second dielectric layer having a second band gap energy greater than the first band gap energy and located between the first ferroelectric dielectric layer and the metal dichalcogenide channel.

5. The single three-dimensional memory device of claim 4, wherein:

the first ferroelectric dielectric layer comprises a first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer; and is provided with

The second dielectric layer includes a second hafnium aluminum oxide or hafnium zirconium aluminum oxide layer having a higher aluminum concentration than the first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer.

6. The unitary three-dimensional memory device of claim 3, wherein the metal dichalcogenide channel has a thickness in a range of 1 monolayer to 5 monolayers and includes the two-dimensional electron gas therein.

7. The unitary three-dimensional memory device of claim 6, wherein the metal dichalcogenide channel comprises a metal having Mo_1-xW_xS_2-ySe_yA material of composition, wherein x is in the range of 0 to 1, and y is independent of x and in the range of 0 to 2.

8. The single three-dimensional memory device of claim 3, wherein:

the substrate comprises a semiconductor material layer; and is provided with

The bottom end of the metal dichalcogenide channel is electrically connected to the layer of semiconductor material.

9. The unitary three-dimensional memory device of claim 3, further comprising a drain region contacting an upper end of the metal dichalcogenide channel.

10. The unitary three-dimensional memory device of claim 9, wherein the drain region comprises a ring-shaped doped metal dichalcogenide drain portion.

11. The unitary three-dimensional memory device of claim 9, the drain region comprising a doped semiconductor drain portion.

12. The unitary three-dimensional memory device of claim 9, wherein the drain region comprises a nickel layer, a nickel silicide layer, an N + doped polysilicon layer, a stack of titanium and gold layers, or a stack of nickel and gold layers.

13. The single three-dimensional memory device of claim 1, wherein the ferroelectric memory element comprises a two-dimensional van der waals ferroelectric element.

14. The unitary three-dimensional memory device of claim 13, wherein the ferroelectric memory element comprises a material selected from cunnp₂S₆、a-In₂Se₃g-SbP, g-SbAs, or a group IV monosulfide material having the formula MX, wherein M is selected from Ge, Sn, or Pb, and X is selected from S, Se or Te.

15. A method of forming a single three-dimensional memory device, comprising:

forming an alternating stack of insulating layers and spacer material layers over a substrate, wherein the spacer material layers are formed as or subsequently replaced by conductive layers;

forming memory openings through the alternating stack;

forming ferroelectric memory elements at a periphery of the memory opening at each level of the layer of spacer material; and

a two-dimensional electron-gas channel is formed directly on the ferroelectric memory element in the memory opening.

16. The method of claim 15, wherein the ferroelectric memory element is formed by conformal deposition and anisotropic etching of at least one ferroelectric dielectric layer.

17. The method of claim 16, wherein the at least one ferroelectric dielectric layer comprises:

a first ferroelectric dielectric layer having a first band gap energy;

a second dielectric layer having a second band gap energy greater than the first band gap energy and deposited on the first ferroelectric dielectric layer;

the first ferroelectric dielectric layer comprises a first hafnium aluminum oxide or hafnium zirconium aluminum oxide layer; and is

18. The method of claim 15, wherein the ferroelectric memory element comprises a two-dimensional van der waals ferroelectric element.

19. The method of claim 15, wherein:

the two-dimensional electron gas channel comprises a metal dichalcogenide channel having a thickness in a range of 1 monolayer to 5 monolayers and including a two-dimensional electron gas therein;

the metal dichalcogenide channel comprises a metal having Mo_1-xW_xS_2-ySe_yA material of composition, wherein x is in the range of 0 to 1, and y is independent of x and in the range of 0 to 2.

20. The method of claim 19, wherein the metal dichalcogenide channel is formed by: atomic layer deposition of a metal oxide layer comprising molybdenum oxide, tungsten oxide, or molybdenum tungsten oxide followed by chalcogenization of the metal oxide layer.

21. A memory device, comprising:

at least one cell layer stack over a substrate, wherein the cell layer stack comprises a metal source layer, a channel level insulating layer, a metal drain layer, and a device isolation level insulating layer;

a plurality of memory openings extending vertically through the at least one cell layer stack; and

A memory opening fill structure located within a respective one of the plurality of memory openings,

wherein each of the memory opening fill structures comprises a tubular ferroelectric dielectric layer and at least one two-dimensional electron gas channel extending vertically between the metal source layer and the metal drain layer of the at least one cell layer stack.

22. The memory device of claim 21, wherein the channel level insulating layer contacts an outer cylindrical sidewall of a respective one of the at least one two-dimensional cylindrical electron gas channel.

23. The memory device of claim 21, wherein the tubular ferroelectric dielectric layer contacts a cylindrical surface of the metal source layer and a cylindrical surface of the metal drain layer.

24. The memory device of claim 21, wherein each of the memory opening fill structures comprises a word line located over an inner cylindrical sidewall of the tubular ferroelectric dielectric layer and extending vertically through each metal source layer and each metal drain layer within the at least one cell layer stack.

25. The memory device of claim 21, wherein the at least one cell layer stack comprises a vertical stack of a plurality of the cell layer stacks.

26. The memory device of claim 21, wherein the tubular ferroelectric dielectric layer comprises:

a first ferroelectric dielectric layer having a first band gap energy; and

a second dielectric layer having a second band gap energy greater than the first band gap energy and located between the first ferroelectric dielectric layer and the two-dimensional electron gas channel.

27. The memory device of claim 26, wherein:

28. The memory device of claim 21, wherein the tubular ferroelectric dielectric layer comprises a two-dimensional layer of van der waals ferroelectric material including a material selected from cunnp₂S₆、a-In₂Se₃g-SbP, g-SbAs, or a group IV monosulfide material having the formula MX, wherein M is selected from Ge, Sn or Pb, and X is selected from From S, Se or Te.

29. The memory device of claim 21, wherein the at least one two-dimensional cylindrical electron gas channel comprises a metal dichalcogenide channel.

30. The memory device of claim 29, wherein:

the at least one two-dimensional cylindrical electron gas channel has a lateral thickness in the range of 1 monolayer to 5 monolayers and includes the two-dimensional electron gas therein; and is

The at least one two-dimensional cylindrical electron gas channel comprises Mo_1-xW_xS_2-ySe_yA material of composition, wherein x is in the range of 0 to 1, and y is independent of x and in the range of 0 to 2.

31. A memory device, comprising:

a two-dimensional electron gas channel located on the substrate;

a source region and a drain region at end portions of the two-dimensional electron gas channel;

a two-dimensional layer of van der Waals ferroelectric material on the two-dimensional electron gas channel and comprising a material selected from CuInP₂S₆、a-In₂Se₃A ferroelectric material of g-SbP, g-SbAs, or a group IV monosulfide material having the formula MX, wherein M is selected from Ge, Sn or Pb, and X is selected from S, Se or Te; and

at least one gate electrode over the layer of two-dimensional van der Waals ferroelectric material.

32. The memory device of claim 31, further comprising a channel side interface dielectric layer comprising hafnium aluminum oxide, hafnium oxide, or aluminum oxide contacting the substrate and the two-dimensional electron gas channel.

33. The memory device of claim 31, further comprising a ferroelectric-side interfacial dielectric layer comprising hafnium aluminum oxide, hafnium oxide, or aluminum oxide contacting the two-dimensional van der waals ferroelectric material layer and the at least one gate electrode.

34. The memory device of claim 31, wherein:

the substrate comprises a semiconductor material layer; and is

The source region and the drain region comprise respective doped portions of the layer of semiconductor material.

35. The memory device of claim 31, wherein:

the source and drain regions comprise respective portions of a two-dimensional electron gas channel layer, the respective portions comprising material of the two-dimensional electron gas channel and additionally comprising dopant atoms;

a source contact via structure contacting a top surface of the source region; and is

A drain contact via structure contacts a top surface of the drain region.

36. The memory device of claim 31, wherein the at least one gate electrode comprises a plurality of gate electrodes arranged along a direction connecting the source and drain regions to provide a NAND memory device or arranged along a direction perpendicular to the direction connecting the source and drain regions to provide a NOR memory device.

37. A ferroelectric memory device, comprising:

a channel;

a gate electrode;

a ferroelectric element between the gate electrode and the channel, wherein the ferroelectric element comprises a two-dimensional van der Waals ferroelectric material layer comprising a material selected from CuInP₂S₆、a-In₂Se₃、g-SbP、g-a ferroelectric material of SbAs, or a group IV monothio-metal material having the formula MX, wherein M is selected from Ge, Sn or Pb, and X is selected from S, Se or Te; and

a first interfacial dielectric layer between the ferroelectric element and the gate electrode.

38. The ferroelectric memory device of claim 37, wherein the first interfacial dielectric layer comprises hafnium aluminum oxide, hafnium oxide, or aluminum oxide.

39. The ferroelectric memory device of claim 37, wherein the memory device comprises a single three-dimensional memory device comprising:

An alternating stack of insulating layers and conductive layers over a substrate, wherein the gate electrode comprises one of the conductive layers;

a memory opening extending vertically through the alternating stack, wherein the channel comprises a two-dimensional electron gas channel located inside the memory opening;

a ferroelectric memory element located between the channel and the conductive layer, wherein the ferroelectric element comprises one of the ferroelectric elements; and

a dielectric core surrounded by the channel.

40. The ferroelectric memory device of claim 39, further comprising a second interfacial dielectric layer contacting the two-dimensional electron gas channel and the dielectric core and comprising hafnium aluminum oxide, hafnium oxide, or aluminum oxide.