KR100659815B1 - Fabrication Method of Programmable Single Electron Device - Google Patents

Abstract

The present invention relates to a method of manufacturing a new programmable single-electron device combining a conventional single-electron transistor and a memory function, which can be applied to a low power consumption, multi-function logic circuit. The present invention provides a process for forming a conventional source, drain and tens of nanometer wide conduction channel on a silicon on insulator (SOI) substrate, and then forming a side wall on the gate oxide layer, and a control gate in a direction perpendicular thereto. And forming a quantum dot, a tunnel junction, and a floating quantum dot simultaneously on the conducting channel by appropriate reactive ion etching and wet etching.

SOI, single electron transistor, memory, nanolithography, side wall, tunnel junction, floating quantum dot, multifunction logic device

Description

Fabrication Method of Programmable Single Electron Device

1 is a representative view after the core process of the programmable single-electron transistor according to the present invention is completed,

2 is a perspective view illustrating a drain connected to a source and a conductive channel in an upper silicon layer of an SOI;

3 is a perspective view illustrating side walls formed on both sidewalls of a conductive channel;

4 is a perspective view illustrating a process of forming a control gate after patterning the control gate electron beam;

5 is a perspective view illustrating the device after removing the side wall other than the floating quantum dot and removing the control gate electron beam pattern;

6 is a perspective view illustrating an ion doping process for metallization of the remaining portions except for the quantum dots and the floating quantum dots.

Explanation of symbols for the main parts of the drawings

1: silicon substrate

2: silicon oxide film

3: source and drain

4: conduction channel

5: gate oxide film

6: first polysilicon layer

7: side wall

8: trench

9: interlayer insulation film

10: second polysilicon layer

11: control gate electron beam pattern

12: control gate

13: Ion Doping

14: floating quantum dots

15: QD

16: tunnel junction

The recent trend of memory development speed is expected in 2010, the emergence of ultra-small low-voltage memory devices and logic devices that realize 1-bit information with less than 10 electrons. In particular, in the case of single-electron logic devices, the results of the present studies show that the nanochannels randomly form quantum dots and conduction channels and operate at room temperature [Uchida et al., IEDM (2000)]. Fabrication of a single-electron device in the form of a nonvolatile MOS memory that can be reproduced by effective control of quantum dot potential [Chou et al, Appl, Phys, Lett. 70, 850 (1997). However, in the case of the former, the achievement of room temperature operation was achieved by the generation of quantum dots of only a few nanometers, but the reproducibility was difficult due to the random generation of conduction channels and quantum dots. It only means to be seen. On the other hand, in the latter case, the intended generation of the quantum dots and the independent control can achieve the intended characteristics of the operating characteristics, but due to the characteristics of the proposed structure, it is difficult to achieve integration on the wafer scale. On the other hand, in this latter case, the present application proposes a new method different from the conventional method for integration and intended logical operation of each device.

The present invention corresponds to the above technical requirements, and relates to a unit device manufacturing process essential for the development of a large-capacity, low-power, ultra-high-density programmable multifunction logic device. By applying the conventional CMOS process and electron beam lithography method, two side walls are formed on both sides of dozens of nano-conducting channels, tunnel junction formation process of quantum dots electrically coupled with them, and at the same time, control gate The process of creation is essential. In addition, it is necessary to control the thickness of the silicon oxide film to achieve effective coupling between the quantum dots and the side wall, and to acquire the parameters to achieve the coulomb vibration of the quantum dots by the control gate and the electron capture of the side walls.

The programmable single-electron transistor of the present invention is formed on a silicon-on-insulator (SOI) substrate, and the structure of the device is a conducting channel (4) of several tens of nanometers of source and drain (3) in top-Si. And a floating quantum dot (FD) 14 surrounded by the gate oxide film 5 and the interlayer insulating film 9 on both sidewalls of the center portion of the conductive channel, and the control gate 12 above the floating quantum dot. ) Is the structure formed in the direction perpendicular to the conduction channel. In addition, two tunnel junctions 16 are formed at the intersection of the control gate and the conduction channel, thereby generating the quantum dots 15. After that, the conventional doping process, the activation process, the contacting and the metallization process are completed, and the programmable single-electron transistor of the present invention is completed.

Referring to the accompanying drawings, a method for manufacturing a programmable single-electron transistor of the present invention will be described in detail as follows.

The upper part of the SOI substrate used for manufacturing a programmable single-electron transistor (hereinafter, referred to as a single-electron device) is upper layer silicon. First, a source, a drain, and a source-drain are connected by electron-beam direct writing. After patterning a portion of the conducting channel 4 of several tens of nanometers wide,

Reactive ion etching (RIE) is used to remove all remaining upper silicon (Figure 2).

After the gate oxide film 5 is grown to several nanometers,

When the first polysilicon layer 6, which is a material that will form the side walls, is deposited and then RIEed, only the polysilicon of both sidewalls of the conducting channel remains. The polysilicon lines formed along both sidewalls of the channel are commonly referred to as side walls 7 (Fig. 3).

After this side wall (7) is formed, half the thickness of the center portion of the conducting channel (calculated) is formed to form a tunnel junction in the conduction channel having a resistance of several tens of times the quantum resistance (25.8 k5.8). The above etching is performed to form the trench 8 (Fig. 4). In addition, by reducing the core conduction channel and the side wall of the trehch portion already formed on both sidewalls, the size of the floating quantum dots can be reduced. (Figure 4)

Thereafter, when the silicon double oxide film is grown by the thermal oxidation method as the interlayer insulating film 9 between the floating quantum dot and the control gate, the thermally grown silicon oxide film 9 is again formed by penetrating the side wall 7 in the depth direction. The size (thickness) is reduced once more (Fig. 5).

After depositing the second polysilicon layer 10, which is a material to form the control gate on the oxide film (Fig. 6),

In order to create a control gate 12 for controlling the coupling between the electrical potential of the quantum dots 15 and the floating quantum dots 14, patterning 11 using an electron beam direct drawing method in the direction perpendicular to the conduction channel and then resting the rest After removing the second polysilicon layer 10 by dry etching using RIE, the control gate electron beam pattern 11 is not removed.

When the first interlayer insulation film used for wet etching and dry etching under appropriate conditions is removed, the side wall 7 is exposed (FIG. 7).

Subsequently, the control gate electron beam pattern 11 is used as a mask to remove sidewalls 7 of the unwanted portions exposed by the above process (Fig. 4) by wet etching with an appropriate solvent.

In this process, by using the isotropy of wet etching, a trench 8 is formed by etching one or more floating quantum dots in the longitudinal direction (calculated) in the longitudinal direction (Fig. 4). In addition, by reducing the core conduction channel and the side wall of the trench portion already formed on both sidewalls, the size of the floating quantum dots to be generated later can be reduced. (Figure 4)

Thereafter, when the silicon double oxide film is grown by thermal oxidation with the interlayer insulating film 9 between the floating quantum dot and the control gate, the thermally grown silicon oxide film 9 again penetrates the side wall 7 in the depth direction. Reduce the size (thickness) once more (Fig. 5).

After depositing the second polysilicon layer 10, which is a material to form the control gate on the oxide film (Fig. 6),

In order to create a control gate 12 for controlling the coupling between the electrical potential of the quantum dots 15 and the floating quantum dots 14, patterning 11 using an electron beam direct drawing method in the direction perpendicular to the conduction channel and then resting the rest After removing the second polysilicon layer 10 by dry etching using RIE, the control gate electron beam pattern 11 is not removed.

The side wall 7 is exposed by removing the interlayer insulating film under the wet and dry etching under appropriate conditions (FIG. 7).

Subsequently, using the control gate electron beam pattern 11 as a mask, the process (Fig. 4) is revealed.

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Claims (6)

delete In order to fabricate a programmable single-electron device of the present application, the steps of defining a source and a drain connected by conducting channels of several to several tens of nanometers wide using a nano patterning method suitable for upper layer silicon: Etching the formed nano patterning to form an active region in the upper layer silicon: Forming a gate oxide film over the substrate; Depositing first polysilicon on the substrate and performing dry etching to form side walls on both sidewalls of the conductive channel: Forming an interlayer insulating film of all possible materials on the front of the substrate: Forming a second polysilicon layer over the substrate to be used as a control gate material: After said process, defining the shape of the control gate by electron beam lithography in a direction perpendicular to the conducting channel beneath it; After the process, the control gate is formed by appropriate reactive ion etching: Removing sidewalls other than the intersections between the interlayer insulating film and the control gate in order by performing the appropriate wet etching and reactive ion etching; delete delete In claim 2, When the interlayer oxide film is grown by thermal oxidation method, the silicon oxide film penetrates the side wall in the depth direction to further reduce the size of the floating quantum dots in the future. In claim 2, Wet etching removes the interlayer insulating film and the side wall under the gate polysilicon to remove side walls other than the floating quantum dots and to further reduce the size of the floating quantum dots in the longitudinal direction by using the isotropy of the wet etching. Method of manufacturing a programmable single electronic device.

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