JP3581289B2 - Field emission electron source array and method of manufacturing the same - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a field emission electron source array used for a cold cathode lamp, a fluorescent display tube, a backlight for a liquid crystal device, a field emission display, and the like, and a method for manufacturing the same. The present invention relates to a field emission electron source array requiring an XY address like an image forming apparatus and a method of manufacturing the same.
[0002]
[Prior art]
In recent years, field emission electron sources that emit field emission electrons by applying a strong electric field have been actively researched and developed, and are expected to be applied to flat panel displays, that is, field emission displays (FEDs).
Recently, a carbon nanotube (CNT) having a nested shape of a graphite layer wound in a cylindrical shape was discovered by Iijima et al. (S. Iijima, Nature, 354, 56.1991), and CNT was used. Research and development of FEDs have been started. An example of the configuration of the FED using such CNTs is disclosed in Japanese Patent Application Laid-Open No. H11-162383.
FIG. 5 is a cross-sectional view of a flat panel display disclosed in Japanese Patent Application Laid-Open No. 11-162383. The configuration of a conventional flat panel display using CNTs will be described with reference to FIG. The electron emission portion 105 is divided by the rib 104 and is electrically connected to the cathode electrode wiring through a through hole. A gate electrode wiring is provided on the rib 104. By using the gate electrode wiring and the cathode electrode wiring, XY addresses are enabled, and a flat display can be provided.
[0003]
[Problems to be solved by the invention]
However, in the flat display described in the above-mentioned publication, the electron-emitting portion (pixel portion) is a paste pattern of columnar graphite (CNT) formed by a screen printing method, and the pixel portion and further the display surface of the display. There is a problem that the uniformity of light emission luminance is deteriorated.
In addition, since this flat display is not provided with a current limiting mechanism such as a resistance layer which has been conventionally used, the CNT is damaged by an overcurrent, and the reliability of the flat display deteriorates. Furthermore, simply arranging a resistance layer as conventionally known on this flat display has an electrical contact between the respective CNTs in the paste, and cannot sufficiently add resistance. The effect of the current limiting mechanism was not so much obtained.
The present invention has been made in view of such a problem, and has a uniform emission current, a current limiting mechanism, and a field emission that can reduce flicker and improve reliability of a thin image forming apparatus. An object of the present invention is to provide an electron source array and a method for manufacturing the same.
[0004]
[Means for Solving the Problems]
In the field emission electron source array of the present invention, the field emission electron source and the cathode electrode wiring are electrically connected via a resistance layer, and the field emission electron source and the resistance layer are filled in the same minute space, Each of the minute spaces is insulated and separated by an insulating material, and the electron emission region is formed by integrating the minute spaces filling the field emission electron source and the resistance layer.
That is, the field emission electron source array of the present invention is an aggregate of field emission electron sources divided and arranged in a small space of about several tens nm to several hundreds nm, and one field emission electron source is one It has a configuration in which it is electrically connected to the resistance layer in the minute space.
Further, the field emission electron source is composed of an electron emission material and a fixing material for fixing the electron emission material on the resistance layer in the minute space, so that the fixing material is an electron emitting material. It has the role of dispersing the release material and electrically and mechanically adhering it to the resistive layer.
Further, the insulating material having the minute space is porous alumina. Since the minute space penetrates from the cathode electrode wiring side to the electron emission surface side and the penetrated minute space is linear, the insulating material having the minute space is made of porous alumina.
[0005]
The method for manufacturing a field emission electron source array according to the present invention includes a step of forming a cathode electrode wiring on a support substrate, a step of forming an insulating material having a minute space on the support substrate, and a step of forming the cathode electrode wiring and the gate electrode wiring. Forming a resistive layer by filling a resistive material in the minute space, forming a field emission electron source on the resistive layer, and forming a gate electrode wiring on the resistive layer. And forming. That is, in the method of manufacturing a field emission electron source array according to the present invention, a minute space of an insulating material formed on a cathode electrode wiring is sequentially filled with a dispersion composed of a resistance material, an electron emission material and a fixing material. It is characterized by including the step of forming.
[0006]
Further, the step of forming the insulating material having a minute space on the supporting substrate is a step of bonding a thin film of the insulating material. In addition, the formation of the insulating material having minute spaces on the cathode electrode wiring may be performed by directly bonding the insulating material having minute spaces, by anodizing the deposited film of the patterned metal thin film, or by forming the bonded aluminum foil. It is characterized by including a step of anodizing.
Further, the step of forming a resistance layer by filling the minute space with a resistance material is electrochemical deposition.
[0007]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a perspective view of a field emission electron source array according to an embodiment of the present invention. The field emission electron source array of the present embodiment is an example applied to a field emission display (hereinafter, referred to as FED). The basic configuration of such an FED is similar to a cold cathode lamp, a backlight of a liquid crystal device, and a fluorescent display tube. That is, the cold cathode lamp does not need to address the electron emission region (pixel), and the gate electrode and the cathode electrode may be simple flat plates. Also, the backlight and the FED of the liquid crystal device need to address the gate electrode and the cathode electrode by dividing the gate electrode and the cathode electrode into lines, and the FED is arranged so that the gate electrode and the cathode electrode are orthogonal to each other. Further, the fluorescent display tube is provided with a gate electrode and a cathode electrode corresponding to the segment. The field emission electron source array of the present invention can be used for all these electronic devices.
[0008]
In FIG. 1, a field emission electron source array according to the present embodiment is made of a ceramic material, a support substrate 1 for designating a face plate from the back side of a back plate, and a cathode for sequentially applying a scanning voltage from a scanning driver. An electrode wiring 2; a gate insulating layer 6 for electrically insulating the cathode electrode wiring 2 from the gate electrode wiring 7; an anodic oxide film (insulating material) 3 for forming minute spaces (pores) 10; A field emission electron source 5 and a cathode electrode wiring 2 having a layered structure in which a field emission electron source 5 and a gate electrode wiring 7 for applying image data for horizontal lines from a data side driver are sequentially stacked. Are electrically connected via the resistance layer 4, the field emission electron source 5 and the resistance layer 4 are filled in the same minute space 10, and each of the minute spaces 10 is made of the insulating material 3. Are edges separated, has a structure in which an electron emission region is formed by integrating a small space 10 for filling the field emission electron source 5 and the resistor layer 4.
[0009]
As shown in FIG. 1, a cathode electrode wiring 2 is formed on a support substrate 1. In the present embodiment, the cathode electrode wiring 2 is directly formed on the support substrate 1, but the support substrate 1 may be processed into a concave shape and the electrode wiring material may be embedded. Further, the cathode electrode wiring 2 is divided into lines, and the line width (or line pitch) is appropriately determined by the design of a target device. Conventionally, it was necessary to form the resistance layer on the cathode electrode wiring, but in the present embodiment, it is not necessary to form the resistance layer on the cathode electrode wiring, so that the vertical direction (+ Z axis direction) in FIG. The configuration is such that the definition can be improved.
[0010]
As a material of the cathode electrode wiring 2, a conventionally well-known cathode electrode material such as gold, platinum, silver, copper, nickel, cobalt, and aluminum can be used. An insulating material 3 is provided on the cathode electrode wiring 2 to form a substantial electron emission region (a pixel in the case of an image forming apparatus) 8. The insulating material 3 has a minute space 10. The diameter of the minute space 10 is about several tens nm to several hundreds nm, the height (the film thickness of the insulating material 3) is about several μm to several tens μm, and the density is about 10 ⁸ to 10 ¹⁰ / cm ² . The material of the insulating material 3 needs to take into account the formation of the minute space 10. If the labor of fine processing is omitted, a metal material such that the minute space (pores) 10 due to anodic oxidation is spontaneously formed Is preferred. Examples of the material that can be anodized include aluminum and tantalum, and are not limited, but aluminum having a linear minute space 10 is most preferable in the present embodiment.
[0011]
A large number of minute spaces 10 are integrated in the electron emission region 8, and the minute space 10 is filled with a field emission electron source 5 and a resistance layer 4. The field emission electron source 5 is electrically connected to the cathode electrode wiring 2 via the resistance layer 4, and is composed of a field emission material and a fixing material. However, when the field emission material can be sufficiently fixed to the resistance layer 4, the fixing material need not be used. Examples of the field emission material include carbon materials such as carbon nanotube, diamond, fullerene, and graphite; semiconductor materials such as boron nitride and silicon; and noble metal materials such as gold and platinum.
As the fixing material, paste materials well known in the art can be used, and examples thereof include inorganic paste materials represented by glass, and organic paste materials represented by acrylic acid and cellulose. The resistance value of the resistive layer 4 to be introduced is appropriately determined by those skilled in the art according to the device design, and the designed resistance value corresponds to the cross-sectional area and height of the minute space 10 electrically insulated from each other. Is precisely represented on the device.
[0012]
A gate insulating layer 6 is provided in a gap between the electron emission region 8 and the adjacent electron emission region 8. The gate insulating layer 6 is for electrically insulating the cathode electrode wiring 2 and the gate electrode wiring 7, and by providing such a gate insulating layer 6, the reliability of short-circuit prevention between electron emission regions is reduced. Not only is improved, but also it is easy to arrange the cathode electrode wiring 2 and the gate electrode wiring 7 at right angles to each other. As the gate insulating material, a sinterable solution-type insulating material is preferable because of its ease of embedding.
[0013]
On the gate insulating layer 6, a gate electrode wiring 7 is provided. The gate electrode wiring 7 is for modulating an electron beam. For example, in the case of an image forming apparatus, XY addressing is performed between the gate electrode wiring 7 and the cathode electrode wiring 2. Although one gate opening is provided for the electron emission region 8 in FIG. 1, the present invention is not limited to this. A plurality of gate openings may be provided for the electron emission region. As the gate electrode wiring material, a well-known gate electrode wiring material of a field emission electron source is used.
[0014]
A field emission electron source array (5 inches diagonal, 320 × 240) having such a configuration was prototyped, and its field emission characteristics were experimentally verified. As a result, the field emission start voltage was 1 V / μm or less, and the current density was 10 mA / cm ² or more. Furthermore, a phosphor was arranged so as to face such a field emission electron source array, and field emission experiments were continued. As a result, it was confirmed that the phosphor emitted light uniformly and uniform field emission was obtained. Confirmed experimentally.
[0015]
FIG. 2 is a circuit diagram schematically illustrating an image forming apparatus using the field emission electron source array according to the present embodiment.
In FIG. 2, reference numeral 11 denotes a data driver, 12 denotes a scan driver, and 13 denotes a controller for controlling these drivers 11 and 12. A video signal for forming an image is input to the controller 13.
The controller 13 controls the scan driver 12 to perform scanning, and as a result, the scan driver 12 sequentially applies a scan voltage to the cathode electrode wiring 2. On the other hand, the data driver 11 controlled by the controller 13 applies a voltage corresponding to image data for a horizontal line to the gate electrode wiring 7. Thus, the pixel 8 addressed by the cathode electrode wiring 2 and the gate electrode wiring 7 emits electric field toward the opposing anode electrode.
In the present embodiment, each field emission electron source in the addressed pixel is connected in parallel to the cathode electrode wiring 2, and the same resistance is added. Thus, the field emission electron source array of the present embodiment operates as an image forming apparatus.
[0016]
Next, a method of manufacturing the field emission electron source array according to the present embodiment will be described with reference to FIGS.
3 and 4 are process cross-sectional views of the field emission electron source array of the present embodiment.
First, in FIG. 3A, a cathode electrode wiring 2 is formed on a support substrate 1. The formation of the cathode electrode wiring 2 can be sufficiently handled by a conventional technique. However, when the pitch of the cathode electrode wiring 2 is narrow or when the wiring length is long, a process suitable for each case should be appropriately selected. That is, when the pitch of the cathode electrode wiring 2 is 100 μm or less, it is preferable that the cathode electrode wiring 2 is formed by a sputtering method (or a vacuum evaporation method), a photolithography, an etching, or the like used in a normal semiconductor processing technique. Further, when the wiring length of the cathode electrode wiring is 30 cm or more, it is preferable to form the wiring by a screen printing method, a direct drawing method, or the like.
[0017]
Next, in FIG. 3B, an anodically oxidizable metal thin film 9 is formed on the cathode electrode wiring 2 and a gate insulating layer 6 is formed in a region other than the cathode electrode wiring 2. Examples of the anodizable metal on the cathode electrode wiring 2 include aluminum, tantalum, silicon and the like, and aluminum is most preferable in that a linear minute space (pores) can be obtained. The thickness of the aluminum thin film is preferably about 1 μm to 3 μm, and if it is 1 μm or less, it is difficult to form minute spaces (pores), while if it is 3 μm or more, the thin film is easily peeled. Further, the surface of the aluminum thin film is required to be flat, and it is necessary to optimize the deposition conditions so as to obtain a mirror surface. Although such deposition conditions vary depending on the deposition apparatus used, deposition conditions that increase the deposition rate and suppress the aluminum crystal growth are preferable.
In addition, the gate insulating layer 6 is deposited before performing anodic oxidation of aluminum, and prevents anodic oxidation from the side surface of the aluminum thin film. As the gate insulating layer 6, a solution insulating material such as SOG (spin on glass) often used in a semiconductor process is preferable. Such a solution-like insulating material is applied by a spin coater or the like, and the surface is polished by a CMP or a simple mechanical polishing method to expose the surface of the aluminum thin film. Thus, a process sectional view as shown in FIG. 3B is obtained.
[0018]
Next, as shown in FIG. 3C, the aluminum thin film 9 is anodized to obtain the anodic oxide film 3. A minute space (pores) 10 is formed in the anodic oxide film 3. Anodizing conditions can be appropriately determined by those skilled in the art depending on the thickness of the anodic oxide film 3 and the diameter of the minute space (pores) 10. The diameter of the minute space (pores) 10 is preferably about several tens nm to several hundreds nm. When the diameter is several tens nm or less, the method of filling the minute space (pores) with the resistance material and the electron-emitting material, When it is limited and is several hundred nm or more, anodizing conditions become difficult. In this embodiment, an aluminum thin film is deposited by a vapor deposition method to a thickness of 1 μm, anodized (in sulfuric acid, applied voltage: 40 V, temperature: 10 ° C.), and wet etched with a mixed acid of phosphoric acid / hydrochloric acid. : An anodic oxide film 3 having a minute space (pores) 10 of 60 nm was obtained (see FIG. 3C).
[0019]
Next, as shown in FIG. 4D, the resistance layer 4 is filled on the cathode electrode wiring 2. The filling method of the resistance layer 4 is preferably an electrochemical deposition method. As the resistance material, a resistance material should be selected according to a resistance value appropriately designed by those skilled in the art, and a material that can be filled by an electrochemical deposition method is preferable. Further, the material should be selected in consideration of the diameter and the filling amount of the anodic oxide film 3 formed in FIG.
Next, as shown in FIG. 4E, the field emission electron source 5 is filled on the resistance layer 4 in the minute space (pores) 10. The field emission electron source 5 is composed of fine particles of an electron emitting material or a dispersion of fine particles of an electron emitting material and a fixing material. Such a field emission electron source 5 is filled by an electrochemical deposition method or a screen printing method. As the electron-emitting material, fine particles of a carbon material, a semiconductor material, and a noble metal material are preferable as described above. As the fixing material, an inorganic paste material represented by a glass material, an organic paste represented by an acrylic acid material, and an organic paste represented by a cellulose material are used. Materials are preferred. At this time, when an elongated rod-shaped electron-emitting material, for example, a carbon nanotube is used and the length of the carbon nanotube in the longitudinal direction is set to be at least twice as long as the diameter of the minute space (pores) 10, the carbon nanotube is connected to the opposed anode electrode. Is controlled in the vertical direction with respect to.
[0020]
When the dispersion of the electron-emitting material and the fixing material is filled in the minute space (pores) 10, post-processing after filling is important. This post-processing is performed to expose the surface of the fine particles of the electron-emitting material from the fixing material, and an etchant or an etching gas is selected in consideration of the selectivity between the fixing material and the electron-emitting material. Such etching may be either wet etching or dry etching.
Finally, a gate electrode wiring 7 is formed on the gate insulating layer 6 as shown in FIG. The gate electrode wiring 7 can be formed by a screen printing method or a direct drawing method. As the material of the gate electrode wiring 7, a conventionally used material such as molybdenum or niobium can be used.
Further, when the electron emission region 8 is about several hundred μm, there is a limit in manufacturing by the screen printing method or the direct drawing method. In such a case, it is preferable to mask the electron emission region 8 with a resist, deposit a gate electrode wiring material, and lift off the resist. If a method of etching and removing the electron emission region 8 of the deposited gate electrode wiring material as used in a normal semiconductor process is used, there is a possibility that the electron emission region may be damaged by the process, which is not a preferable manufacturing method. . However, as long as the process damage is not a problem, it may be removed by etching.
[0021]
As described above, the field emission electron source array according to the present embodiment has a basic configuration in which each field emission electron source 5 is divided and arranged in the minute space 10 and connected in parallel with the resistance layer 4. The electron source array is composed of an electron emission material and a fixing material, and the insulating material 3 having the minute space 10 is composed of porous alumina. The method of manufacturing the field emission electron source array includes, as described in detail with reference to FIGS. 3 and 4, a resistive material, an electron emitting material, and a fixing material in a minute space 10 of the insulating material 3 formed on the cathode electrode wiring 2. And the insulating material 3 having the minute space 10 on the cathode electrode wiring 2 is directly bonded to the insulating material 3 having the minute space 10. Anodizing of the deposited film of the patterned metal thin film or anodizing of the bonded aluminum foil makes it possible to easily manufacture the field emission electron source array. As compared with the field emission electron source array, a field emission electron source array having excellent uniformity of emission current and high reliability can be realized.
[0022]
【The invention's effect】
As described above in detail, according to the field emission electron source array of the present invention, each field emission electron source is divided and arranged in a minute space of about several tens nm to several hundreds of nm to form one field emission electron source. Because one resistance layer is configured to be electrically connected in parallel in a minute space, it is possible to improve the uniformity and reliability not only in the electron emission area but also in the designed device plane. it can.
Further, in the field emission electron source array of the present invention, the field emission electron source is composed of the electron emission material and the fixing material, so that electrical and mechanical adhesion to the resistance layer to be connected can be improved, Since the micro space for filling the field emission electron source is made of porous alumina, it is possible to provide a micro space having a fine diameter.
[0023]
In the method of manufacturing a field emission electron source array according to the present invention, a minute space of an insulating material formed on a cathode electrode wiring is sequentially filled with a dispersion composed of a resistance material, an electron emission material, and a fixing material. By including the forming step, it is possible to construct a configuration in which the field emission electron source array is divided into small spaces and connected in parallel to the resistance layer.
In addition, the formation of the insulating material having minute spaces on the cathode electrode wiring may be performed by directly bonding the insulating material having minute spaces, or by anodizing the deposited film of the patterned metal thin film, or by bonding the bonded aluminum foil. The anodizing process eliminates the need for microfabrication technology used in normal semiconductor processes, and the process of filling a resistive material into a minute space of insulating material to form a resistive layer is an electrochemical process. By using the selective deposition method, the manufacturing cost can be reduced.
Therefore, it is possible to manufacture a highly integrated and small field emission electron source array without using a fine processing technique, and it is suitable for application to a large-sized panel that is XY-addressable.
[Brief description of the drawings]
FIG. 1 is a perspective view of a field emission electron source array according to an embodiment of the present invention.
FIG. 2 is a circuit diagram schematically illustrating an image forming apparatus using the field emission electron source array of the present embodiment.
FIG. 3 is a process cross-sectional view (part 1) of the field emission electron source array of the present embodiment.
FIG. 4 is a process sectional view (part 2) of the field emission electron source array of the present embodiment.
FIG. 5 is a cross-sectional view of a conventional flat display.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Support substrate 2 Cathode electrode wiring 3 Anodized film 4 Resistance layer 5 Field emission electron source 6 Gate insulating layer 7 Gate electrode wiring 8 Electron emission area (pixel)
9 Metal thin film (metal foil)
10 micro space (pore)
11 Data side driver 12 Scan side driver 13 Controller

Claims (7)

The field emission electron source and the cathode electrode wiring are electrically connected via a resistance layer, the field emission electron source and the resistance layer are filled in the same minute space, and each of the minute spaces is insulated and separated by an insulating material. And an electron emission region is formed by integrating a minute space filling the field emission electron source and the resistance layer, and the field emission electron source includes an electron emission material and the electron emission material in the minute space. And a fixing material to be fixed on the resistance layer in the field emission electron source array. 2. The field emission electron source array according to claim 1 , wherein the insulating material having the minute space is porous alumina. A step of forming a cathode electrode wiring on a support substrate, a step of forming an insulating material having a minute space on the support substrate, and a step of forming a gate insulating layer that insulates the cathode electrode wiring and the gate electrode wiring, Filling a resistive material into the minute space to form a resistive layer; and filling the minute space with a dispersion composed of an electron emitting material and a fixing material to form a field emission electron source on the resistive layer A method for manufacturing a field emission electron source array, comprising: a step of forming a gate electrode wiring. 4. The method for manufacturing a field emission electron source array according to claim 3, wherein the step of forming the insulating material having a minute space on the supporting substrate is a step of bonding a thin film of the insulating material. 4. The method according to claim 3, wherein the step of forming a resistance layer by filling the minute space with a resistance material is electrochemical deposition. Wherein the step of forming an insulating material on a supporting substrate having minute spaces, the step of patterning the aluminum thin film, an electric field according to claim 3 or 4, characterized in that it comprises an anode oxidation step of the aluminum A method for manufacturing an emission electron source array. 7. The method according to claim 6, wherein the patterning step of the aluminum thin film is a bonding step of an aluminum foil.

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