JP3542308B2 - Semiconductor device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, particularly to a high-speed, highly integrated semiconductor device which is constituted by fine elements and which operates at a low voltage and is suitable for a semiconductor integrated circuit which can operate on a battery.
[0002]
[Prior art]
2. Description of the Related Art The integration degree of a semiconductor integrated circuit (LSI = Large Scale Inegration) has been promoted by miniaturization of a MOS transistor as a constituent element thereof. In the case of a so-called deep sub-micron LSI having a device size of 0.5 μm or less, a problem arises in that the breakdown voltage of the device decreases and the power consumed by the LSI increases. To solve such a problem, it is considered that reducing the operating power supply voltage with miniaturization of the element is an effective means. As the power supply voltage of the current LSI is 5 V, the technology of mounting a voltage conversion circuit for stepping down an external power supply voltage on an LSI chip has been developed as a means for configuring an LSI with fine elements.・ E-Journal of Solid-State Circuits, Vol. 21, No. 5, pp. 605-611 (1986) (IEEE Jounal of Solid-State Circuits, vol. 21, No. 5, pp. 605-611) , October 1986). In this case, the values of the external power supply voltage and the internal power supply voltage are 5 V and 3.5 V, respectively. As described above, the problem of power consumption is becoming apparent in a dynamic RAM (DRAM = Dynamic Random Access Memory) having the highest integration among LSIs. In accordance with such a tendency, there is a movement to reduce the external voltage itself of the LSI. For example, in a 64-Mbit DRAM using a processing technique of 0.3 microns, the external power supply voltage will be reduced to about 3.3V. As the degree of integration increases, the external power supply voltage may further decrease.
[0003]
In recent years, with the spread of portable electronic devices, there has been an increasing demand for low-voltage, low-power-consumption LSIs capable of operating a battery and retaining information in the battery. For such applications, an LSI operating at a minimum of 1 to 1.5 V is required. In particular, in the case of a dynamic memory, the degree of integration has already reached the megabit level, and there has been a movement to use the semiconductor memory also in the field of large-capacity storage devices which could only use magnetic disk devices in the past. . For that purpose, it is necessary to back up with a battery so that data is not lost even if the power is turned off. This backup period usually needs to be guaranteed for weeks to years. For this reason, it is necessary to reduce the current consumption of the memory as much as possible. To reduce the power, it is effective to reduce the operating voltage. However, if the operating voltage is set to around 1.5 V, only one dry battery is required as a backup power source, so that the cost is low and the occupied space is small.
[0004]
In a CMOS (Complementary MOS) LSI composed of only an inverter and various digital logic circuits, for example, a processor, even if the power supply voltage is reduced to about 1.5 V, even if the constant and the threshold voltage of the MOS transistor are properly selected. It is possible to operate with a power supply voltage as low as about 1.5 V without causing a significant decrease in performance. However, in addition to the external power supply voltage (VCC or VSS), an intermediate voltage thereof or a voltage exceeding these ranges is generated on the LSI, and in an LSI using the same, the reduction of the power supply voltage is crucial. The performance was reduced. A representative example of such an LSI is a DRAM. Therefore, when an information device that operates at a low voltage is constituted by a plurality of types of LSIs such as a processor and a memory, a voltage other than the power supply voltage is generated on the LSI and used for the operation as represented by DARM. Low-voltage operation of the LSI is essential.
[0005]
When the DRAM is operated at a low voltage, problems occur mainly in the following three cases which have been conventionally used.
[0006]
(1) A circuit for reading a small signal read from a memory.
[0007]
(2) A circuit for generating a high voltage for driving a word line necessary for transmitting a signal without loss by setting a MOS transistor constituting a memory cell to a sufficiently high conductive state.
[0008]
(3) A circuit that generates an intermediate voltage (VCC / 2) that becomes a reference voltage when detecting a read signal from a memory cell storage capacitor plate electrode and a memory cell.
[0009]
These conventional examples will be described below in order.
[0010]
(1) is as follows. As the integration and scale of LSIs increase, the parasitic capacitance of signal wirings increases, and the problem that the operation speed decreases is becoming apparent. In the case of a dynamic memory, the speed at which a small signal read from each memory cell onto a data line is amplified by a sense amplifier, and an input / output control line (common I / O) for reading information from a selected data line The operation speed of the line occupies a large proportion of the operation speed of the whole memory, and a technique for increasing the operation speed is indispensable for improving the performance of the memory. Conventional I / O control circuits include, for example, IEE, Journal of Solid State Circuits, SC22 (1987), pages 663 to 667 (IEEE, Journal of Solid-State Circuits). As described in State Circuits, Vol. To control the connection between the data line pair and the common I / O line pair.
[0011]
FIG. 20 shows a conventional example of (2). This shows circuits related to a memory cell array (MA) and a word driver (WD) of a DRAM. FIG. 21 shows the waveform of each part. This circuit is described, for example, in IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. sc-21, NO. 3, JUNE 1986, pp. 381-387.
[0012]
The conventional example of (3) is as follows. The DRAM system in which data lines are precharged to a VCC / 2 voltage has become the mainstream of 1-Mbit and higher DRAMs together with CMOS circuits due to features such as high speed, low power consumption, and noise resistance. An example of a conventional intermediate voltage generating circuit for generating this VCC / 2 voltage is disclosed in IEEJ Journal of Solid State Circuits, Vol. 21, No. 5, pp. 643-648. (1986) (IEEE Jounal of Solid-State Circuits, vol. 21, No. 5, pp. 643-648, Octorber 1986).
[0013]
[Problems to be solved by the invention]
Problems to be solved by the present invention with respect to the above conventional example are as follows.
[0014]
First, the conventional example (1) is as follows. FIGS. 7A and 7C show examples of the conventional method. This method is effective for reducing the area of the entire memory because it can be constituted by a minimum number of transistors, but has the following disadvantages. (A) If the MIS-FETs (T50, T51) for I / O control are made conductive before the signal voltage of the data line (D0, D0 #) is sufficiently amplified, the operation of the sense amplifier SA0 is hindered. Causes malfunction.
[0015]
(B) For the above-described reason, it is necessary to provide a time delay (timing margin) between the input of the selection signal Y01 and the conduction of the MIS-FET after the operation of the sense amplifier, thereby lowering the operation speed. FIG. 7 (c)).
[0016]
(C) In order to prevent such a malfunction, there is a design constraint on the ratio of the channel conductance (conductivity between drain and source) of the MIS-FET to the channel conductance of the MIS-FET constituting the sense amplifier. I do. Generally, it is necessary to make the former smaller than the latter, and it is difficult to increase the driving capability of the common I / O lines (IO0, IO0 #). Therefore, in addition to (b), the operation speed further decreases.
[0017]
(D) As the degree of integration of memories increases, the internal power supply voltage tends to decrease in order to cope with a reduction in power consumption and a decrease in withstand voltage of elements. Therefore, the driving capability of the MIS-FET is further reduced, and the operation speed is further reduced.
[0018]
(E) It is difficult to write or read in parallel between one common I / O line and a plurality of data lines connected to it, mainly due to the reason (c) above. Limited in terms of test functions.
[0019]
For this reason, the conventional input / output circuit system cannot provide a circuit system suitable for a highly integrated memory that operates at high speed even at a low voltage.
[0020]
Next, the conventional example of (2) is as follows. As shown in FIG. 20, the word driver includes transistors QD and QT. Here, when the X decoder output N1 becomes High level (VL), the gate N2 of the QD is charged through the QT, and the QD is turned on. At this time, the voltage of N2 becomes VL-VT. Next, when the word line drive signal φX (amplitude is equal to or more than VL + VT) generated by the peripheral circuit FX goes to a high level, a current flows from the drain to the source of the QD, and the word line W goes to a high level. At this time, the potential difference between the gate of QT and N1 is 0, and N2 is Vt, so that QT is cut off. Therefore, when φX rises, the voltage of N2 rises together with φX due to the coupling between the gate and source capacitance of QD. Here, when the gate-source voltage of QD is equal to or higher than VT when φX reaches the maximum value, the voltage of the word line becomes equal to φX. On the other hand, if φX becomes lower than VT during the rise, the capacitance between the gate and the source of QD becomes 0, and the rise of N2 stops at that point, and VL−VT + α as shown in FIG. (VL-2VT) / (1-α). The word line voltage is (V_DL-2V_T) / (1−α). Here, α is the ratio of the gate capacitance of the QD to the total capacitance of the node N2.
[0021]
Here, consider the case where VL drops to 1.1 V due to battery consumption. If α = 0.9 and VT = 0.5 (V), the voltage of N2 is 1.5 V from the above equation. Therefore, the word line voltage only rises to 1.0V. Normally, the threshold voltage of the switch transistor QS of the memory cell is higher than that of the peripheral circuit and becomes 0.5 V or more, so that the amount of charge stored in the memory cell is less than half of the maximum value (CS × 1.1) ( CS × 0.5), which significantly reduces the soft error resistance and the S / N of the sense amplifier. That is, the stored data is likely to be destroyed.
[0022]
As described above, when an attempt is made to operate a DRAM with a battery using the conventional technique, if the electromotive force of the battery drops to almost twice the threshold voltage VT of the MOS transistor, a malfunction in the word driver causes a malfunction in the memory cell. There is a problem that the writing voltage is lowered and data is likely to be destroyed, and there is a problem that needs to be solved.
[0023]
Regarding (3), the following two problems occur in the conventional intermediate voltage generation circuit due to the lower voltage and higher integration. (A) As the power supply voltage decreases, the voltage setting accuracy decreases, and the signal-to-noise (S / N) ratio deteriorates.
[0024]
(B) Since the element operates in the source-follower mode, the response speed is determined by the value of the drive capability and the load capacitance of the transistor. Therefore, the load capacitance is increased due to high integration, and the voltage is further reduced. As a result, the response speed decreases due to the reduction in the driving capability of the element.
[0025]
FIG. 30 shows a conventional example of a DRAM intermediate voltage generating circuit. Hereinafter, the above problem will be described with reference to FIG. In FIG. 30, TN5 and TN6 are N-channel MIS FETs, TP5 and TP6 are P-channel MIS FETs, R1 and R2 are resistors, and CL is a load capacitance. The circuit of FIG. 30 is a kind of a complementary push-pull circuit. TN6 and TP6 constitute a voltage dividing circuit for dividing a power supply voltage VCC (VSS is a ground potential) to an intermediate voltage of HVC, and a bias voltage is applied to these gates. And TN5 and TP5 for providing a bias circuit constitute a bias circuit. In a DRAM of the VCC / 2 precharge type, the load capacity is almost equal to the capacity of all data lines. The value of the degree. In this circuit, a small current is constantly passed through each FET, so that the output is stabilized to a constant voltage. If the current is small, the voltage difference between the terminal 20 and the terminal 22, ie, V (20) −V (22), is almost equal to the threshold voltage VTN of the FET TN5, and the voltage difference between the terminal 22 and the terminal 21, ie, V (22). -V (21) becomes substantially equal to the absolute value VTP of the threshold voltage of the FET TP5. The gate width-to-gate length ratio W / L of the FETs TN6 and TP6 is selected to be several times to several tens times the W / L of the TN5 and TP5, respectively. Therefore, the bias current of TN6 is several times to several tens times the bias current of TN5.
[0026]
First, the first problem will be described. Now, assuming that there is no difference in element characteristics (for example, threshold voltage, channel conductance per unit gate width, etc.) between the FET pair TN5 and TN6 and TP5 and TP6, the output HVC has the terminal 22 Is obtained. The output voltage is
V (HVC) = R2 / (R1 + R2) × VCC-R2 / (R1 + R2) × VTN + R1 / (R1 + R2) × VTP
It is expressed as Here, it is assumed that VSS is at the ground potential. Under the standard condition, when the values of VTN and VTP are designed to be almost equal and R1 = R2,
V (HVC) = VCC / 2−VTN / 2 + VTP / 2
That is, if the difference between VTN and VTP is negligible compared to VCC,
V (HVC) ≒ VCC / 2
It becomes. In general, the variation in the threshold voltage of the element is considered to be constant without being reduced even by the high integration, and therefore, as VCC is lowered, the setting accuracy of V (HVC) decreases. For example, assuming that VTN and VTP fluctuate ± 0.1 V with respect to the standard value, respectively, when the power supply voltage is 5 V (HVC is 2.5 V), the fluctuation of the intermediate voltage is about ± 4%. When the power supply voltage is 1.5 V (HVC is 0.75 V), the fluctuation of the intermediate voltage reaches about ± 13%, which hinders the stable operation of the memory.
[0027]
Next, the second problem will be described. When the load is charged and discharged, the output MISFET operates in the saturation region.
ID = β / 2 × (VGS−VT)^Two
It is expressed as Here, VGS is the gate-source voltage, VT is the gate threshold voltage of the MISFET, and β is a constant determined by the structure and dimensions of the element. Now, in the conventional circuit, the time required to raise the voltage of the load (load capacity = CL) from 0 V to 90% of the intermediate voltage VCC / 2.
tr is
tr = 18CL / β × 1 / (VCC / 2)
It is expressed as It is assumed that the number of memory cells connected to one data line is 256 and the capacitance value per data line is 0.5 pF. Since these values are almost constant with higher integration of the memory, the value of the load capacity increases by four times for each generation. For example, CL 、 ４8.2 nF for a 4 Mbit DRAM, CL ≒ 33 nF for a 16 Mbit, and CL ≒ 131 nF for a 64 Mbit. On the other hand, when the power supply voltage decreases from 5 V to 3.3 V to 1.5 V for each generation, β of the MISFET becomes 10 mA / V^Two, The rise time tr increases by about 10 times from 5.9 μs → 36 μs → 314 μs for each generation. In order to keep the response speed constant, it is necessary to increase the β of the MISFET by 10 times for each generation. However, there is a side effect of increasing the layout area and the steady-state current. It is impossible to keep tr constant.
[0028]
It is an object of the present invention to solve the conventional problems described above and to provide a semiconductor device that operates stably at high speed even at a low voltage. More specifically, the following three objects are aimed.
[0029]
(1) To provide a method of an input / output control circuit of an ultra-highly integrated memory that operates at high speed even at a low voltage, has excellent operation stability, and has a parallel test function.
[0030]
(2) To provide a circuit capable of generating a sufficiently high word line voltage so that data destruction does not occur even when the electromotive force of the battery decreases.
[0031]
(3) To provide a voltage supply circuit (voltage follower) that operates with high accuracy and high speed even in an LSI with a high integration and a low power supply voltage.
[0032]
[Means for Solving the Problems]
In order to achieve the above-mentioned object (1), input / output control circuits for reading information from a data line or writing information to a data line are alternately arranged on the left and right sides of a memory array, and The circuit configuration is such that the transfer impedance between the I / O line and the data line is changed between when reading and writing information. Further, as a sense circuit for detecting a signal on the read line (RO line), a current-voltage conversion means using a MISFET complementary to a MISFET for selection is provided. This means is to operate at high speed even at a low voltage.
[0033]
In order to achieve the object (2), the following measures were taken as described in the claims. That is,
(A) An output of a data line power supply and a word driver for applying a voltage 1.5 to 2 times the threshold voltage of a switch transistor of the memory cell array to the data line as a minimum operating voltage applied to the memory cell array and the data line And a voltage conversion circuit for converting the data line power supply voltage to a voltage higher than the data line voltage by at least the threshold voltage of the switch transistor of the memory cell array, and using the output of the voltage conversion circuit as a power supply. A word line drive is provided with an operating static word driver.
[0034]
(B) The voltage conversion circuit according to the first aspect includes a charge pump circuit and a rectifier circuit.
[0035]
(C) The charge pump circuit according to the second aspect includes first, second, third, and fourth MOS transistors and first and second capacitors, and the second, third, and fourth capacitors are provided. The drain of the MOS transistor serves as a power supply, the gate of the second MOS transistor serves as the source of the fourth MOS transistor, the source of the third MOS transistor serves as the source of the second MOS transistor, and the third and fourth MOS transistors. Is connected to the power supply, one terminal of the first capacitor is connected to the source of the fourth MOS transistor, and one terminal of the second capacitor is connected to the source of the second MOS transistor. The other end of the second capacitor is connected to a charge pump circuit to which a pulse of the opposite phase is input. The on to power, the source of the fourth MOS transistor to the source, it was decided to combine the gate to the source of the second MOS transistor.
[0036]
This means is to speed up the rise of the charge pump circuit even at a low power supply voltage and to further increase its output voltage.
[0037]
(D) In the rectifier circuit according to the above item (2), the rectifier element is constituted by a MOS transistor, and the drain of the MOS transistor is input and the source is output, and the input is the charge pump circuit according to item (3). The source is connected to a circuit for transmitting electric charge from the output, a capacitor for storing the electric charge, and a circuit for transmitting the electric charge to a power supply. When the input voltage is at a high level, one end of the capacitor is set to a high level. The gate voltage of the MOS transistor is set to be equal to or higher than the sum of the input voltage and the threshold voltage of the MOS transistor. When the input voltage is low, one end of the capacitor is set to a low level, and at the same time, the gate voltage of the MOS transistor is lowered. The power supply voltage was set.
[0038]
This means is to reduce the voltage drop of the rectifying transistor and obtain a high output voltage.
[0039]
(E) In the means of the first or second item, the threshold value of the MOS transistor used for the memory cell array, the word driver and the voltage conversion circuit is set to three types, the threshold value of the memory cell array is the highest, and that of the word driver is the highest. The voltage conversion circuit was set to be the lowest among those in the middle.
[0040]
The present means achieves further stabilization, higher speed and lower power consumption as an integrated circuit even at a low power supply voltage.
[0041]
Furthermore, in order to achieve the object of (3), in the semiconductor device of the present invention, the input of the reference voltage equal to the intermediate voltage and at least two first and second complementarys whose outputs are connected in parallel to the same load. A push-pull circuit and a push-pull current amplifying circuit for amplifying and outputting a reference current, wherein the first complementary push-pull circuit adds an input of the reference voltage to the bias circuit and the input to the input; A bias voltage source for applying a bias voltage to the gate of the voltage dividing transistor of the push-pull circuit; the voltage dividing circuit of the push-pull circuit forms a reference current circuit of the current amplifying circuit; The output terminal of the circuit is connected to the bias circuit of the second complementary push-pull circuit.
[0042]
That is, a generator of a reference voltage equal to the intermediate voltage is separately provided from the bias circuit of the complementary push-pull circuit, and the load is driven in parallel by at least two complementary push-pull circuits. The voltage difference is detected as a current flowing through one push-pull circuit, and the other push-pull circuit is driven by an amplified current substantially proportional to the current.
[0043]
Here, it is preferable that the bias voltage of the first and second complementary push-pull circuits is substantially equal to the gate threshold voltage of the transistor of the push-pull circuit to which the voltage is applied. This suppresses the current flowing through these transistors to a low value in a steady state.
[0044]
Alternatively, if the current amplifying circuit is a current mirror type push-pull amplifying circuit, a high driving capability can be easily obtained with a simple circuit configuration with little variation.
[0045]
Alternatively, it is preferable to configure the first and second complementary push-pull circuits with field-effect transistors because they can be operated at a low power supply voltage.
[0046]
According to the semiconductor device of the present invention for achieving the object (3) more effectively, an input of a reference voltage equal to the intermediate voltage and at least two first and second outputs connected in parallel to the same load. Complementary push-pull circuit and tri-state drive circuit, and a push-pull current amplifier circuit that amplifies and outputs a reference current, the first complementary push-pull circuit, the bias circuit, the input of the reference voltage And a bias voltage source added to the input, wherein the voltage dividing circuit of the push-pull circuit forms a reference current circuit of the current amplifying circuit, and the output terminal of the current amplifying circuit is connected to the second complementary push-pull circuit. Connected to a bias circuit of a pull circuit, and the tri-state drive circuit further comprises a first circuit which is lower than a voltage of the input. A constant voltage and a second determination voltage higher than the input voltage are provided.The output is charged when the output voltage is lower than the first determination voltage, and the output is charged when the output voltage is higher than the second determination voltage. It is characterized by having means for discharging.
[0047]
That is, in the present invention, the tri-state drive circuit is connected in parallel to the load together with the complementary push-pull circuit to supplement the driving capability of the push-pull circuit.
[0048]
Here, the bias voltage of the first and second complementary push-pull circuits is set to a voltage substantially equal to the gate threshold voltage of the transistor of the push-pull circuit to which the voltage is applied, or the current amplifier circuit Is a current mirror type push-pull amplifier circuit, or the first and second complementary push-pull circuits are preferably constituted by field effect transistors, as described above.
[0049]
Here, it is preferable that the input and output voltages are set to a half of the power supply voltage in terms of appropriateness for a circuit such as a DRAM.
[0050]
Further, an integrated circuit (LSI) including at least a plurality of blocks of the same type and operating one or a plurality of blocks selected by a block selection signal during operation, and a unit for supplying and driving a voltage using the blocks as a load In the case of a semiconductor device having: a first and a second drive circuit, and a block provided for each block in an operating state as the above-described drive means for driving a block in order to achieve a high-speed response. Is provided with switching means for respectively connecting a block in a non-operating state to the second drive circuit.
[0051]
Such a means is suitable for an integrated circuit such as a large-capacity dynamic memory.
[0052]
In such a case, the block includes at least a memory cell array, and the load includes a common electrode of a memory cell storage capacitor and a precharge voltage supply line of a data line transmitting a signal from the memory cell to a signal detection circuit. It is good to include at least.
[0053]
Here, it is preferable for the application to the DRAM that the driving circuit generates a voltage of one half of the power supply voltage.
[0054]
Further, if the semiconductor device of the present invention is used as the driving circuit, high accuracy and high speed can be achieved even for a large-capacity LSI.
[0055]
Regarding (1), with the above configuration, the input / output control circuit can be laid out at a pitch twice as large as the data line pitch. Can be taken. As a result, the operation margin of the input / output circuit is remarkably improved, and stable and high-speed operation can be performed even at a low voltage. Further, since the operation is stable even when writing and reading are performed in parallel, a parallel test with a high degree of parallelism can be performed.
[0056]
Regarding (2), in the static word driver, a P-channel transistor is connected to the power supply side, and an N-channel transistor is connected to the ground side. Therefore, if the gate is set to the ground level (0 V) at the time of driving the word line, the P-channel transistor is always on if the power supply voltage is equal to or higher than the threshold voltage VT, and its output voltage rises to the power supply voltage. In this way, the static word driver operates stably even at a low power supply voltage because the gate voltage of the drive transistor operates at a low level.
[0057]
Therefore, by using the output of the voltage conversion circuit as the power supply of the word driver, it becomes possible to apply a voltage higher than the data line voltage by the threshold voltage of the switch transistor of the memory cell array by at least the threshold voltage of the memory cell array. This makes it possible to stabilize the memory operation even when the power supply voltage drops to about 1V.
[0058]
Further, the charge pump circuit of the present invention feeds back its output voltage to the precharge transistor. By using this in the voltage conversion circuit, it is possible to obtain a fast rise and a high output voltage even with a low power supply voltage. become.
[0059]
The rectifier circuit according to the fourth aspect of the present invention synchronizes the gate voltage of the rectifying transistor with the output voltage of the charge pump circuit, and when the output, that is, the drain voltage of the transistor is at a high level, sets the gate voltage to a higher level. The voltage is increased by the value voltage or more, and when it is at the low level, the two are set to the same level. This makes it possible to reduce the voltage drop of the rectifying transistor and to prevent the backflow of charges.
[0060]
When the threshold voltage of a transistor is lowered, the driving capability of the transistor generally increases. Therefore, it is effective to use such a transistor in a voltage conversion circuit that is not so large as described in the fifth means of the above means. However, as will be described later, in the case where a large number of transistors are used like a word driver, on the contrary, the leakage current flowing when the transistor is in the off state cannot be ignored, so that a standard threshold current is used. Further, when the threshold voltage of the transistor of the memory cell array is lowered, the refresh interval is shortened as described later, which leads to an increase in power consumption. Therefore, it is preferable to use a transistor having a higher than standard voltage.
[0061]
That is, the fifth term of the above-mentioned means operates to further stabilize the integrated circuit even at a low power supply voltage, to increase the speed, and to reduce the power consumption.
[0062]
Regarding (3), by dividing the generation section of the reference voltage equal to the intermediate voltage from the bias circuit of the complementary push-pull circuit, the voltage can be set independently of the bias circuit, and the output of the intermediate voltage can be increased. It is possible to improve accuracy.
[0063]
Also, by converting the voltage difference between the input and output to a current through the transistor of the first complementary push-pull circuit, and driving the second complementary push-pull circuit with an amplified current proportional to the current, As long as there is a voltage difference between the input and output, the driving capability of the push-pull circuit is increased to charge and discharge the load capacitance at high speed. In addition, the charging and discharging driving capacities at that time can be made uniform, so that it is possible to provide a voltage supply circuit (voltage follower) that operates stably at high speed even at a low voltage.
[0064]
Furthermore, if the bias voltage of the complementary push-pull circuit is substantially equal to the threshold voltage of the voltage application transistor and the current of the push-pull circuit is suppressed to a low value as described above, the steady-state power of the semiconductor device is thereby reduced. While it is small, it is possible to obtain a high driving capability when the output voltage fluctuates.
[0065]
In addition, if a current mirror type amplifier circuit is used as the current amplifier circuit, current amplification can be performed with a simple circuit configuration. Driving capability can be easily obtained with little variation.
[0066]
Since the gate threshold voltage of the field effect transistor can be reduced by controlling the impurity concentration, the power supply voltage is reduced by configuring the first and second complementary push-pull circuits with the field effect transistor. The required operation can be easily obtained.
[0067]
Further, according to the above-mentioned means of connecting the tri-state drive circuit to the load in parallel with the complementary push-pull circuit, the load capacitance is charged when the voltage error between the input and the output becomes larger than the judgment voltage. Alternatively, by discharging, the voltage error is converged within the determination voltage, thereby compensating for the operation of the push-pull circuit to further increase the response speed in the transient state.
[0068]
According to the means of the present invention, in which a plurality of blocks of the same type are included in an integrated circuit and only a part of the blocks is operated, only the blocks in operation are switched to be selected as loads. Even in such a case, since a part of the load is substantially carried, a high-speed response is possible without flowing a large transient current. Furthermore, if the device of the present invention is used in this drive circuit, it is possible to more effectively obtain high-accuracy high-speed response as described above.
[0069]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described specifically with reference to examples. In the following description, an example in which the present invention is applied to a dynamic memory (DRAM) will be described. However, the present invention can be similarly applied to, for example, a static memory (SRAM) and a read-only memory (ROM). . In addition to the memory using the MIS type FET element, a memory using the bipolar element, a so-called BiCMOS type memory combining the bipolar element and the MIS-FET, and further using a semiconductor material other than silicon. The same can be applied to a memory.
[0070]
1 to 6 show one embodiment of the memory circuit of the present invention. 1 to 6, MA denotes a memory cell array in which a plurality of memory cells each including one MIS-FET and one storage capacitor are two-dimensionally arranged, and CKT0 and CKT1 detect a memory cell signal and read a read line. Or an input / output control circuit for exchanging information with the outside of the memory through a write line, a data line pair for transmitting signals between the memory cells and the input / output control circuit, D0 and D0￣, D1 and D1￣, WD is a word line drive circuit for designating a row address in the memory cell array and supplying a drive signal to one word line, W0 to Wm are word lines, and YD is a column address in the memory cell array. Y (column) decoder, and Y01 represents a column selection signal line. In the input / output control circuit, SA0 and SA1 are detection circuits (sense amplifiers) for detecting minute signal voltages on data lines, and CSN0 and CSP0, and CSN1 and CSP1 are for driving detection circuits SA0 and SA1, respectively. A signal line, CD0 or CD1 is a drive signal generation circuit of a detection circuit; PR0, PR1 are precharge circuits for short-circuiting a data line pair and setting to a voltage convenient for operation of a sense amplifier in a non-operation state; RG0 or RG1 is a read gate for reading a signal (voltage difference) appearing on the data line pair to the outside of the memory array, T1 to T4 are N-channel MIS-FETs constituting the read gate, and WG0 or WG1 is an external. A write gate for driving a data line according to information, and T5 to T8 constitute one write gate N Channel MIS-FETs, RO0, RO0￣, RO1, RO1￣ are read lines, WI0, WI0￣, WI1, WI1￣ are write lines, RCS0, RCS0￣, RCS1, RCS1￣ are read control lines, WR0, WR0 {, WR1, WR1} indicate write control lines, respectively. SWR0 and SWR1 are switch circuits for connecting read lines to common read lines CRO and CRO #, SWW0 and SWW1 are switch circuits for connecting write lines and common write lines CWI and CWI #, SEL0 and SEL1 are signals for selecting either the left or right switch. AMP is a sense amplifier for detecting and amplifying signals appearing on CRO # and CRO, DOB is an output buffer, and DIB is an input buffer. In this embodiment, the input / output control circuits CKT0 and CKT1 are alternately arranged on the left and right sides of the memory cell array for each data line pair, and the I / O lines in the input / output control circuit are read out lines (RO lines). And a write line (WI line). Hereinafter, specific configurations and effects thereof will be described.
[0071]
FIG. 2 shows a plan layout diagram of the read gate and write gate circuits. In general, as the degree of integration of memories increases, it becomes difficult to lay out the input / output control circuits Ci at the data line pitch. However, by arranging the input / output control circuits alternately on the left and right sides of the memory cell array as in this embodiment, the layout pitch of the input / output control circuits can be twice the data line pair pitch, that is, 2 dy, so that the chip area is greatly increased. The layout is possible without having to do it. In a highly integrated memory, for example, IEE Journal of Solid-State Circuits, 23 (1988), pp. 1113 to 1119 (IEEE, Journal of Solid-State Circuits, vol. As described in No. 5, October 1988, pp. 1113-1119), there is a problem that the signal-to-noise ratio is significantly reduced due to capacitive coupling between adjacent data lines. It is known that the capacitance coupling noise in the memory cell array can be reduced by crossing the data lines in the middle of the memory cell array, but in the input / output control circuit, the coupling capacitance between adjacent data lines depends on the location. Due to the non-uniformity, noise could not be sufficiently reduced. In this embodiment, by arranging a shield wiring between the data line pairs of the input / output control circuit, it is possible to significantly reduce the line-to-line capacitive coupling noise as compared with the related art. Hereinafter, this will be described. In the layout of the input / output control circuit section as shown in FIG. 2, another signal wiring formed simultaneously with the data line is arranged between the data line pair. Here, for example, the read lines RO, RO # and the read control lines RCS, RCS #, which are wired in a direction perpendicular to the data lines in the read gate RGi, are connected to wiring materials formed simultaneously with the data lines through through holes. Connected and arranged in parallel with the data lines. By doing so, the parasitic capacitance between the data line and the adjacent data line can be reduced, the noise accompanying the reading operation can be minimized, and a stable operation can be expected.
[0072]
Next, specific configurations of the read switch SWR0, the write switch SWW0, and the sense amplifier circuit AMO will be described.
[0073]
FIG. 3A shows a configuration example of the read switch SWRi (i = 0, 1). This circuit selectively connects one of the plurality of read lines ROi, ROi # to common read lines CRO, CRO # and controls the voltage of read control lines RCSi, RCSi # of the selected memory block. Then, a signal is taken out to the read line. In the figure, T10 to T17 denote N-channel MISFETs, INV100 denotes an inverter, and NAND1 denotes a two-input inversion AND circuit that outputs a low level only when both inputs are in a high level combination. When the memory block is selected and the selection signal SELi is at a high level, and the memory is in a read state and the write signal WE is at a high level, the MISFETs T10 to T13 are turned on and T14 to T17 are turned off. Therefore, read lines ROi, ROi # are connected to common read lines CRO, CRO #, respectively, and read control lines RCSi, RCSi are grounded. Thus, for example, when the column selection signal Y01 goes high in FIG. 1, T3 and T4 become conductive, and the read control lines RCS0 and RCS0 from the read lines RO0 and RO0 # according to the voltage difference between the data line pair D0 and D0 #. A signal is obtained as the difference between the currents flowing through ￣. Here, read control lines RCS0, RCS0 # are not necessarily separated in consideration of only the read operation, but they are indispensable when a parallel test is performed as described later.
[0074]
When the memory block is deselected and the selection signal SELi is at a low level, or the memory is in a write state and the write signal WE # is at a low level, the MISFETs T10 to T13 are turned off and T14 to T17 are turned on. Therefore, read lines ROi, ROi # and read control lines RCSi, RCSi # are connected to the same voltage (here, intermediate voltage HVL). Thus, for example, even if the column selection signal Y01 goes high in FIG. 1 and T3 and T4 become conductive, no current flows from the read lines ROi, ROi # to the read control lines RCSi, RCSi #. As described in FIG. 10, it is convenient when one column selection signal line selects column addresses of a plurality of memory blocks (including a selected block and an unselected block).
[0075]
FIG. 3B is a configuration example of the write switch SWWi (i = 0, 1). This circuit selectively connects one of the plurality of write lines WIi, WIi # to the common write line CWI, CWI #, and sets the write control line WRi of the selected memory block to a high level to perform the write operation. I do it. In the figure, T20 and T23 to T26 denote N-channel MISFETs, T21 and T22 denote P-channel MISFETs, INV101 to INV103 denote inverters, and NAND2 denotes a two-input inverted AND circuit. When a memory block is selected and the selection signal SELi is at a high level, and the memory is in a write state and the write signal WE is at a high level, the MISFETs T20 to T23 become conductive and T24 to T26 become nonconductive. Therefore, write lines WIi, WIi # are connected to common write lines CWI, CWI #, respectively, and a high level is output to write control line WRi. Thus, for example, when the column selection signal Y01 goes high in FIG. 1, T5 and T6 conduct, the data line pair D0, D0 # is connected to the write lines WI0, WI0 #, and the write information on the write line is the data line. Is written to.
[0076]
When the memory block is deselected and the selection signal SELi is at a low level, or the memory is in a read state and the write signal WE is at a low level, the MISFETs T20 to T23 are nonconductive and T24 to T26 are conductive. Therefore, write lines WIi, WIi # are connected to the same voltage (here, intermediate voltage HVL), and write control line WRi goes low. Thereby, for example, even if the column selection signal Y01 goes high in FIG. 1 and T5 and T6 are turned on, the data line and the writing line are not turned on. For example, as described in FIG. This is convenient when a column address of a plurality of memory blocks (including a selected block and an unselected block) is selected by a signal line.
[0077]
Next, FIG. 4 shows a configuration of a sense amplifier circuit for amplifying a signal read on the common read lines CRO, CRO #. In the figure, amp1 is a first sense amplifier circuit that inputs common read lines CRO and CRO # and outputs d1 and d1. Amp2 is a second sense amplifier circuit that inputs d1 and d1 # and outputs d2 and d2 #. A sense amplifier circuit, amp3 is a third sense amplifier circuit which inputs d2, d2 # and d3, d3 # is an output, and T42, T43 are MISFETs for initializing the third sense amplifier circuit before operation. . The first sense amplifier circuit amp1 is composed of two current-voltage conversion circuits having the same configuration. The current-voltage conversion circuit includes a differential amplifier circuit DA1, a P-channel MISFET T30, and an N-channel MISFET T31. The second sense amplifier circuit amp2 is composed of two differential amplifier circuits DA3 and DA4 having the same configuration. The third sense amplifier circuit amp3 includes two inverting OR circuits MOR1, NOR2 and two inverters INV105, INV106.
[0078]
Next, the operation of this embodiment will be described with reference to the operation waveforms of FIGS. Here, an example will be described in which information read out to data lines D0, D0 # is read, or information from the outside is written into D0, D0 #, but the same operation is performed for all the data in the memory array. It is obvious that the operation can be selectively performed on the memory cell. Although the case where the operating voltage is 1.5 V is described here, the present invention is not limited to this, and the present invention can be similarly applied and the same effect can be obtained even when operating at another voltage.
[0079]
First, the read operation will be described with reference to FIG. The control signal PC of the precharge circuit unit PR0 falls at time t0, and the precharge operation for the data line ends. Subsequently, the selected word line W0 rises at t1, and a signal is read from the memory cell to data lines D0, D0 #. Next, at t3, the sense amplifier drive signal CSP is changed from the intermediate potential to the high level, and CSN is changed from the intermediate potential to the low level, and the sense amplifier SA0 is driven. Thus, the signal read out to the data line is amplified to High and Low by the sense amplifier. Here, in this embodiment, the data line is connected to the gates of the transistors T1 and T2 in the read gate RG0, and is connected to the read lines RO0 and RO0 # through the transistors T3 and T4. The read control lines RCS0, RCS0 # of the selected input / output circuit CKT0 are driven low at t1. With this configuration, the data line and the read line are separated. Therefore, during the amplification before the data line is fixed to the High and Low levels, the information of the data line is input even if the column selection signal line Y01 is input at t3 here. There is no destruction. Therefore, since the information on the data line can be transmitted to the read line without destroying the data line, the speed of the read operation can be increased. The reason why the speed can be increased as compared with the related art and the effect will be described later in detail. Here, the signal voltage of the read line and the common read line, that is, the voltage difference between RO0 and RO0 # and the voltage difference between CRO and CRO # is about 20 mV, and the output signal amplitude of the first sense amplifier circuit (voltage difference between d1 and d1 #). Is about 200 mV, and the output signal amplitude (voltage difference between d2 and d2￣) of the second sense amplifier circuit is about 1 to 1.5V. That is, the voltage gain of the first sense amplifier is about 10 and the voltage gain of the second sense amplifier is about 5 to 7. The voltage amplification rate of the third sense amplifier circuit is about 1-2. However, the third sense amplifier circuit has a function of storing output information, a so-called latch function. That is, by amplifying the input signal and setting both inputs low, an output corresponding to the previous input is held until the next input is input. Thus, it is not necessary to always put all of the first to third amplifier circuits into operation, and after output, the first or second or both amplifier circuits are put into a non-operation state to reduce power consumption. can do.
[0080]
This figure also shows an example of a so-called static column operation in which a column address is switched and another information is read after reading one piece of information. That is, the information is read out by raising Y23 next to the column selection signal Y01. According to the present embodiment, the voltage amplitude of the read line and the common read line is reduced to 20 mV, which is 1/10 of the conventional voltage, by making the input of the sense amplifier circuit a current as described later. As a result, the time required for charging and discharging the parasitic capacitance of the read line and the common read line can be reduced to about 1/10, and the delay from switching the address to outputting the information can be extremely reduced.
[0081]
Next, an example in which a write operation is performed after a read operation will be described with reference to FIG. In the figure, the first read operation is the same as in FIG. When WE becomes high at t4, the column selection signal line Y01 remains High,
The control signal line RCS0 of RG0 becomes HVL (0.75V), and the control signal line WR0 of the write gate WG0 becomes ゛ High. At the same time, when write data is applied to the write input / output lines WI0, WI0 #, data is written to the data lines D0, D0 # through the transistors T5, T7 and T6, T8 in the write gate WG0.
[0082]
As shown in the above example, as one means for changing the transfer impedance between the I / O line and the data line in the write operation and the read operation, the read operation margin is obtained by separating the read line and the write line. And the write operation margin can be individually set, so that the operation can be speeded up and stabilized even at a low voltage operation.
[0083]
Next, the effects of the sense amplifier circuit used in this embodiment will be described with reference to FIGS. FIG. 7A schematically shows a configuration of a conventional sense amplifier circuit, and FIG. 7B schematically shows a configuration of a sense amplifier circuit according to the present invention. FIG. 7C schematically shows operation waveforms of the conventional sense amplifier circuit and the sense amplifier circuit according to the present invention. In the conventional circuit, a small signal read from the memory cell MC to the data line (D0, D0 #) is amplified by the sense amplifier SA0, and then the MISFETs T50, T51 # controlled by the column selection signal Y01 are turned on. And transmitted to the read lines (IO0, IO0 #). Conventional circuits have two problems that hinder speeding up. One is that it is necessary to turn on the MISFET after it has been sufficiently amplified by the sense amplifier. Otherwise, since there is a capacitance difference of several tens of times between the data line (CD about 0.3 pF) and the read line (CR about 8 pF), a large charge flows from the read line, and the information that has been amplified is destroyed. This is because The other is that it is necessary to amplify a read line having a large parasitic capacitance to a large voltage of 200 mV by a sense amplifier having a small driving capability. This is due to the signal detection sensitivity of the second sense amplifier circuit in the next stage.
[0084]
Therefore, in the present invention, the NMOS transistors T1 and T2 which receive the signal of the data line at the gate are provided, and the sense amplifier and the read line are separated. As a result, the MISFETs T3 and T4 controlled by the column selection signal can be turned on without waiting for the data line to be sufficiently amplified, so that the voltage information on the data line is converted into current information and read at high speed. Can be served. Further, a current sense circuit, which is achieved by a P-channel MISFET and an amplifier circuit, is provided so as to be suitable for low-voltage operation, so that a voltage output proportional to a current input can be obtained. By using the current input, the voltage amplitude of the signal line can be reduced by about one digit (200 mV → 20 mV) as compared with the conventional case, and the time required for charging and discharging the parasitic capacitance CR is greatly reduced, thereby increasing the speed. Is done.
[0085]
FIG. 8 compares the operation speeds of the conventional sense amplifier circuit and the sense amplifier circuit according to the present invention based on computer simulation results. Here, the sense time is a delay time from when the signals CSN and CSP for starting the sense amplifier are applied to when a signal voltage of 200 mV is obtained on the I / O line (in the case of the related art), or the first time. It is defined as the delay time until an output of 200 mV is obtained as the output of the sense amplifier circuit (in the case of the present invention). With the circuit of the present invention, the speed is increased by 20 ns at 1.5 V as compared with the conventional example, and thus it was shown that the present invention operates at low voltage and at high speed.
[0086]
As described above, in this embodiment, the input / output control circuits are alternately arranged on the left and right sides of the memory cell array, and the input / output lines for reading and writing are separated, so that the operation can be performed even in the low voltage operation. Speeding up and stabilization can be achieved. Further, the first sense amplifier circuit for detecting the signal on the read line is constituted by a current-voltage conversion circuit, and the MISFET for driving the read line and the MISFET for converting the voltage of the data line to the current of the read line are complementary. With this configuration, it is possible to provide a sense amplifier circuit that operates at high speed even with a low power supply voltage of about 1 to 2 V.
[0087]
FIG. 9 shows an embodiment for further stabilizing the operation. As described above, in the input / output control circuit section, the parasitic capacitance between the data lines could be reduced. Here, the operation is further stabilized by balancing the parasitic capacitance between the data lines in the memory cell array section. That is, the data lines intersect at the center of the memory cell array for each line pair. The parasitic capacitance between D1 and D1 # and data line D0 # is Cc01, respectively._L, Cc01_RHowever, since Cc01L and Cc01R match, the parasitic capacitance between D1, D1 # and data line D0 # can be made equal. Similarly, since the parasitic capacitance between D1, D1 # and the data line D2 can be equalized, the parasitic capacitance between adjacent data lines can be balanced between the paired data lines. Therefore, the reading operation can be further stabilized in the memory cell array.
[0088]
FIG. 10 shows an embodiment in the case where a plurality of memory cell arrays exist. Here, the reading operation will be described. The input / output control circuit CKTij is shared by the left and right memory cell arrays, switch transistors T60 to T63 are connected between CKTij and each memory cell array, and their gates are SHRij which is a selection signal of the memory cell array. Is entered. SWRi is a switch connected to a read line RO and a common read line CRO shared by a plurality of RO lines, and a memory cell array selection signal SHRij is also input to this switch. SHRij is set to High in advance. For example, when memory cell array MA2 is selected, SHR1 is set to SHR1._R, SHR3_LOnly low. Here, assuming that column selection signal Y01 is selected, signals read out to data lines D1, D1 # and D0, D0 # are read out to RO12, RO12 #, RO23, RO23 # through input / output control circuits CKT12, CKT23. Be sent out. These are further read out to common I / P lines CRO0, CRO0 #, CRO1, CRO1 # through switches SWR1 and SWR2. In this way, even when a plurality of memory cell arrays exist, the input / output control circuits are alternately arranged on the left and right sides of the memory cell array and shared by the left and right memory cell arrays without greatly increasing the chip area. The improvement of the characteristics described above can be realized.
[0089]
FIG. 11 shows an embodiment of a parallel test using the present invention. The parallel test is performed by simultaneously selecting a plurality of column selection signals (multiple selection). That is, during the parallel test, the column selection signal is multiplexed by the test signal TEST. As a result, in the read operation, the read signals of the data lines are simultaneously read to the read lines according to the multiplicity. If the information of the data lines read simultaneously coincides, one of the read lines RO and RO # has a "High" voltage level and the other has a "Low" voltage level according to the read information. . If at least one erroneous information is read, both RO and RO # are at the "Low" voltage level. On the other hand, in a write operation, data is written to a data line connected to a write gate selected from input / output lines for writing. Here, in the present invention, even in the case of the parallel test, the parallel test can be performed without providing a new test I / O line, and information is transmitted from the data line to the AMP in the same manner as in the normal test. In addition, since the read signal line and the write signal line are separated, the operation margin can be set individually for the read operation and the write operation as described above, and the limitation in increasing the multiplicity is limited. And allow for a high degree of parallel read / write. In the figure, the drive signal RCS of the read gate RG is paired to separate the RCS connected to the read lines RO, RO # in the read operation. This is an effective means for determining one erroneous reading even when the multiplicity is increased. When the multiplicity is increased, it is necessary to increase the current flowing from the RO to the RCS. On the other hand, the current flowing from RCS to GND saturates at a certain constant due to the wiring resistance of the read line. In other words, the potential of RCS rises. Therefore, unless the RCS is separated, the signal current of the I / O line on the side where the erroneous reading has occurred decreases with an increase in the multiplicity, making detection difficult. By separating the RCS, the potential of the RCS on the side where the erroneous reading was performed does not increase, and only the current flowing from the RO to the RCS need be detected, so that more accurate detection can be performed. As described above, the present invention enables a high-level parallel test, so that the test time can be significantly reduced.
[0090]
FIG. 12 shows an embodiment of a specific circuit for determining the multiplicity. Normally, Y0 to Yn-1 are input to the column decoder YD. Yn-1 divides the column direction into two, Yn-2 further divides each into two, and so on. Y0 repeats "0" (Low) and "1" (High) for each column selection signal. Here, the test signal TEST is set to High, and the OR gate output signals of Yn-1￣, Yn-1 and TEST are set to AYn-1, AYn-1 '. By inputting to the decoder, both AYn-1 and AYn-1 'can be made high irrespective of High and Low of Yn-1 and two column selection signals can be selected, so that the multiplicity can be made two.
[0091]
FIG. 13 shows an embodiment in which the multiplicity is set to 4. The NAND gate outputs of Yn-1 and Yn-2 are input to the NAND gate together with TEST, and their outputs are changed from AYn-20 to 3, and if they are input to the column decoder, the multiplicity can be set to 4. As described above, based on the embodiments shown in FIGS. 12 and 13, column decoders can be multiplexed during a parallel test, and one column select signal can be selected during a normal test by setting test signal TEST to Low. . FIG. 14 shows an embodiment of a sense amplifier circuit for realizing a parallel test. A method of outputting a test result at the time of the parallel test will be described with reference to FIG. In a normal read operation, the outputs after the current-voltage conversion are input as they are to the inversion and non-inversion inputs of the two differential amplifier circuits DA4 and DA5 constituting the amp2T, and those outputs are input to the amp3. At the time of the parallel test, the non-inverting inputs of the two differential amplifier circuits DA4 and DA5 have V as a reference voltage._RTEnter In the parallel test, if at least one erroneous information is included in the multiplexed data lines, a current flows through both RO and RO #. Therefore, the current-to-voltage conversion outputs d1, d1 # of the first sense amplifier circuit amp1 both have a low level. On the other hand, the reference voltage V_RTIs set to a voltage between the high level and the low level of the current-voltage conversion output. In this way, when at least one erroneous information is included, a high level is output to the outputs of the two differential amplifier circuits DA4 and DA5. That is, when both d2 and d2 are high, it can be determined that the information read in parallel contains erroneous information. At the time of the parallel test, these outputs are taken into the judgment circuit TEJ by making TEST # low. TEJ outputs High or Low to ERR according to the output voltage of d2, d2 #. That is, if the results of the parallel tests are all correct, ERR outputs Low, and if at least one is incorrect, it outputs High. The determination of the parallel test result with the multiplicity increased in this way can be performed using the input / output circuit system and the sense amplifier circuit according to the present invention.
[0092]
FIG. 15 shows the reference voltage V used for the parallel test._RT5 is an embodiment of a generation circuit. In the same figure, the current-voltage conversion circuit described above is used, and during the parallel test, the parallel test signal_RTHas occurred. In this circuit, a reference current corresponding to about half of the signal current is applied to the input of the current-voltage conversion circuit. As a result, when a signal current flows through both RO lines, the converted voltage becomes V_RTSmaller. If the result of the parallel test is correct, one of the converted voltages is V_RTLarger than. Therefore, the test result can be determined by comparing the converted voltage with VRT.
[0093]
FIG. 16 shows a specific example of the write switch SWW. WE is a write signal. The present embodiment is based on FIG. 10 when there are a plurality of memory cell arrays, and it is assumed that the memory cell array on the right side of the SWW operates (SELR is high and SELL is low). During the parallel test, TEST is low. During the reading operation, WE is low, and WI and WI # are kept at the same potential by the circuit WST. When the write operation is started, WE goes high. Since all signals input to the GR become High in the reading operation, WER becomes Low and one WEL becomes High. Accordingly, the write control signal WR goes high, and data is written from CWI, CWI to WI, WI # through the N-channel MISFETs T77, T78 and the P-channel MISFETs T75, T76.
[0094]
FIG. 17 shows an embodiment in which the voltage level of the power supply line on the high voltage side of the sense amplifier for detecting and amplifying the signal read from the memory cell to the data line can be arbitrarily set. The write voltage level when writing "1" to the memory cell is the voltage level of the power supply line on the high voltage side of the sense amplifier. Therefore, it is only necessary that the voltage level of the power supply line on the high voltage side can be arbitrarily set. Here, two types of power supply lines on the high voltage side are provided, and one of the power supply lines is_DLUsed for normal writing. The other power supply wiring V_DMCan be set arbitrarily from outside the chip, for example. As a result, if the signals MT0 and MT1 are made low, the drive signal CSP of the sense amplifier becomes V_DLOn the contrary, if the signals MT0 and MT1 are set to High, the drive signal CSP of the sense amplifier becomes V_DMCan be. According to the present embodiment, only the voltage level of the information “1” can be set arbitrarily. Further, the voltage level of the information “1” can be set by changing every other pair. Therefore, as in the case of testing the coupling noise between data lines, a voltage can be written as soon as the information is inverted every other pair, which is effective when a margin test is desired. Further, there is an effect that the test time for the information retention characteristics of the memory cell can be shortened.
[0095]
18 and 19 show one embodiment of the word drive circuit according to the present invention. The feature of this embodiment is that a static word driver including QD1, QD2, QP and QT is used instead of the conventional dynamic word driver. Further, a voltage conversion circuit VCHG which always generates a voltage higher than the data line voltage VL by VT of the switch transistor QS of the memory cell is provided as the power supply. Hereinafter, the operation of this embodiment will be described.
[0096]
First, when the X-decoder XD is selected by the address signal Ai, its output N1 goes low. Then, the electric charge at the node of N2 is extracted through the transistor QT, so that N2 also becomes Low level. Then, the transistor QD1 turns on, and the word line W rises to the level of VCH. Since the level of VCH is equal to or higher than VL + VT (QS), a maximum VL voltage is written to the memory cell CS.
[0097]
Next, in the precharge cycle, first, φ と な り P goes low, which turns on QP and sets node N2 to VCH. Then, since QD1 is turned off and QD2 is turned on, the word line W is at the Low level, and the charge is held in the memory cell.
[0098]
As described above, in this embodiment, since the gate voltage of the drive transistor operates at the low level, the word transistor operates stably even when the power supply voltage decreases.
[0099]
FIG. 22 shows a specific embodiment of the word line voltage conversion circuit VCHG of FIG. FIG. 23 shows an internal waveform and input timing at the time of activation of the circuit. A feature of this embodiment is that in the charge pump circuit, the output voltage is pre-charged to the output voltage precharge transistor (QB in FIG. 22) in order to obtain a fast rise and a high output voltage even at a low power supply voltage. The operation will be described below.
[0100]
First, consider the case where the input pulses φ and φ￣ are High and Low, respectively. At this time, since the voltage of the node B is charged from VL through QC, it becomes VL-VT. On the other hand, the node A has a value determined by the electric charge stored in the capacitors CA and CD and the amplitude of φ. In this embodiment, this voltage is assumed to be VL. Next, when the voltages φ and φ are switched, the node B is boosted by CB and becomes VL−VT + αVL. Here, α is the ratio of the total capacity of CB and node B. At this time, the voltage at the node A becomes a voltage VL−2VT + αVL lower than the voltage at B by the VT of QA.
[0101]
Next, when the voltages φ and φ # are switched again, the voltage of the node A is boosted again. At this time, if it is higher than VL by δ, the voltage of node B is precharged to VL-VT by QC, so that QB is turned on and the voltage of node B is further raised by δ. Therefore, in the next cycle, the voltage of the node B is further increased, and the voltage of the node A is further increased. By repeating the above, the voltage of the node A rises, and finally, reciprocates between VL and 2VDL.
[0102]
When this output is connected to a rectifier circuit indicated by 2, that is, a diode-connected MOS transistor QD, and further including a smoothing capacitor CD in the output, a boosted DC voltage VCH is obtained. This output voltage becomes 2VL-VT in a no-load state.
[0103]
Here, the circuit connecting QA and CA is divided into two, and the output point of each circuit, that is, one of the connection points between QA and CA is connected to the rectifier circuit 2 and the other is connected to the gate of QB. Is separated from the load circuit, the gate voltage becomes high enough that no current flows through the load circuit, and the voltage of the node A can rise more quickly.
[0104]
The feature of this circuit is that, as described above, the precharge voltage is increased by feeding back the output voltage to the precharge circuit, and a high output voltage can be obtained even with a low power supply voltage. For example, assuming that VL = 0.8 (V) and VT = 0.5 (V), when there is no feedback, that is, when there is no QB, the maximum voltage of the node B is 1.1 V (when α = 1, 2VL −VT), and as a result, node A becomes 1.4V (3VL−2VT) and VCH becomes 0.9V (3VL−3VT). On the other hand, when there is a QB, 1.6V (2VL), 1.6V (2VL), and 1.1V (2VL-VT) are all higher than the former.
[0105]
FIG. 28 shows the result of a comparison of the boosting rate between the case where the feedback transistor QB exists (the present invention) and the case where the feedback transistor QB does not exist (the conventional method) by computer simulation. Here, a solid line indicates a transistor having a standard threshold voltage, and a broken line indicates a transistor having a low threshold voltage. From this figure, it can be seen that the power supply voltage drops sharply between 1 and 1.5 V in the conventional method, whereas it is constant up to 0.8 V in the present invention and operates stably even at a low power supply voltage. . Note that the rectifier circuit has no voltage effect due to the threshold voltage of the transistor.
[0106]
The embodiment shown in FIGS. 24 and 25 is a circuit for obtaining a higher output voltage. The feature of this embodiment is that the gate voltage is synchronized with the output voltage of the charge pump circuit in order to reduce the voltage drop in the rectifying transistor, and when the output is at High level (2 VL), it is higher than VT by more than VT. When the level is (VL), it is set to VL.
[0107]
In FIG. 24, CP and QD are the aforementioned charge pump circuit and rectifier circuit. Q1 to Q19 and C1 to C4 are added elements, Q1 is a rectifying transistor, Q3 to Q10, C1 to C3 are circuits for controlling the gate voltage of Q1, and Q11 to Q13, Q15 to Q18, and C4 are gate boosters. A charging circuit for the capacitor C3 for use, Q19 is a precharge transistor for accelerating the rise of VCH. PA and PA # are control signals of the charge pump circuit, and PB and PB # are control signals of the gate voltage control circuit. The operation will be described below.
[0108]
1 is a charge pump described above, in which PA and PA alternately become High and Low, so that the voltage of the node A is boosted and reciprocates between VL and βVL (β ≒ 2). At this time, PA and PA # are set so that the High periods do not overlap each other as shown in FIG. This is because, when φ 図 corresponding to PA￣ in FIG. 22 has not completely dropped to 0 V and the voltage at node B is still VL + VT or more, φ corresponding to PA 上 記 rises and the voltage at node A rises. Then, because the QA is in the ON state, the charge stored in the CA leaks to the power supply side through the QA.
[0109]
Next, as for the rectifier circuit, when PA and PB are Low and PA # and PB # are High, the gate of Q4 is boosted to VL + VT or more by C1 so that the voltage of the gate G of Q1 is equal to VL. . At this time, since node A is at VL, there is no backflow from VCH to node A. Further, the gate of Q11 precharges C4 to VCH (2VL) -VT by Q13 and Q18, and then boosts the voltage at PA） (VL), so that 3VL-VT is obtained. Therefore, if VL ≧ 2VT, the voltage is raised to VCH (2VL) + VT or more, and the node C becomes VCH. At this time, since the voltage between the gate and the source of Q10 exceeds VT at VCH-VL, it turns on, and the gate voltage of Q9 becomes equal to the node C. Therefore, Q9 turns off and no current flows from node C to node G.
[0110]
Next, when PA and PB become High and PA # and PB # become Low, the node A becomes 2VL and the node C becomes VL + VCH. On the other hand, the gate of Q7 is boosted to VL + VT or more by C3, so that the source is VL. That is, since the gate of Q9 becomes VL, the voltage between its gate and source becomes VCH, Q9 turns on, and the gate of Q1 becomes VL + γVCH (γ ≒ 1). Therefore, 2VL is output as it is without lowering by VT as in the embodiment of FIG.
[0111]
In this embodiment, PB is set to a low level before PA. However, when the gate voltage of Q1 is still equal to or higher than VL + VT, PA becomes low, the voltage of node A becomes VL, and the output from the output becomes VL. This is to prevent the charge from flowing back to the node A. The reason why the minimum potential of the gate control circuit is set to VL like the sources of Q4 and Q7 is to reduce the potential difference between the electrodes of the transistors. As a result, the potential difference between the electrodes becomes 2 VL or less, and the same fine transistor as other portions can be used.
[0112]
The above is the feature of the embodiment shown in FIG. 24. In FIG. 24, the same effect can be obtained by removing Q7 and Q10 and connecting the gate of Q9 to the gate of Q4. For example, when PB is VL and PB # is 0, the node C is at VCH + VL, and the gates of Q4 and Q9 are at VL, so Q4 is off, Q9 is on, and node G is at VCH + VL. On the other hand, when PB is 0 and PB # is VL, node C is at VCH (2 VL), and the gates of Q4 and Q9 are at 2 VL, so that Q4 is on and Q9 is off, and node G is at VL.
[0113]
26 and 27 show circuits for generating the timing shown in FIG. In FIG. 26, inverters I5 to I8, resistor R2, capacitor C2, NAND gate NA2, and NOR gate NO1 are circuits for preventing duplication of PA and PA #, and I2, I3, R1, and C1 are delays for the fall of PA and PB. Circuits for determining time, I9 to I13 and NA3, are circuits for creating a delay at the time of the fall of PA and PB. I14 to I25 are buffer inverters. This may be any number of stages as long as the odd number of stages is the same, and may be adjusted according to the magnitude of the load. FIG. 27 is an example of a circuit for generating the input pulse OSC of the circuit. This circuit is generally called a ring oscillator. The feature of this circuit is that the time constants of R and C are made sufficiently larger than the delay time of the inverter in order to suppress the fluctuation of the oscillation frequency due to the power supply voltage. Therefore, the oscillation frequency becomes stable even if the ratio of the VT of the transistor to the power supply voltage is 1: 3 or less and the power supply voltage dependence of the delay time of the inverter is large.
[0114]
In addition to the above countermeasures, by lowering the VT of the transistors in the embodiments of FIGS. 22 and 24, the operation at a lower voltage becomes more stable. This is because the driving capability of the transistor is increased by lowering the VT. Although the sub-threshold current also increases due to the reduction in VT, the number of elements of the voltage conversion circuit is at most about several tens, so that it can be almost neglected in the whole chip. On the other hand, the driving capability of word drivers and memory cells also increases due to the reduction in VT.^Three-10^FourSince a plurality of transistors are used, a leakage current flowing when the transistor is off cannot be ignored. In the latter case, there is a problem that the charge holding time is shortened and the refresh interval must be shortened. This leads to the greatest increase in power consumption. Therefore, it is best that VT is set lower in the voltage conversion circuit, word driver is set as standard, and memory cell is set higher than standard.
[0115]
As described above, according to the present embodiment, the gate voltage of the rectifying transistor can be made higher than the drain voltage by the threshold voltage VT or more, and furthermore, the backflow of charges can be prevented. The value can be increased to the value of 2VL. Further, by using the oscillation circuit and the timing generation circuit using the RC delay, the delay time between the oscillation frequency and the timing becomes stable with respect to the power supply voltage fluctuation, so that the voltage conversion efficiency can always be kept in the best state. Further, by providing three types of VTs for the transistors, the voltage conversion circuit is low, the word driver is standard, and the memory cell is higher than the standard, it is possible to achieve low voltage stabilization, high speed, and low power consumption. Therefore, a semiconductor integrated circuit that operates stably even when the power supply voltage is the electromotive force of one battery can be realized.
[0116]
Next, an embodiment in which the present invention is applied to an intermediate voltage generating circuit will be described. In the following description of the embodiment, although VCC is used as a symbol representing the higher power supply voltage, it does not need to be different from the VL used so far, and may be replaced with VL as it is. Further, although HVC is used as a symbol representing the intermediate voltage, it does not need to be different from the HVL used so far, and may be replaced with HVL as it is. FIG. 29 is a configuration example of a voltage follower circuit according to the present invention. This circuit outputs a voltage substantially equal to the voltage applied to the input, and drives a large load capacitance. Referring to FIG. 1A, reference numeral 1 denotes a first complementary push-pull circuit, which includes an N-channel MOS transistor TN2, a P-channel MOS transistor TP2, and bias voltage sources VN1 and VP1. Reference numeral 2 denotes a current-mirror push-pull amplifier circuit, which comprises a pair of N-channel MOS transistors TN1 and TN3 and a pair of P-channel MOS transistors TP1 and TP3 forming a current mirror circuit. Reference numeral 3 denotes a second complementary push-pull circuit, which includes an N-channel MOS transistor TN4, a P-channel MOS transistor TP4, and bias power supplies VN2 and VP2.
[0117]
The constant setting of various transistors and voltage sources of this circuit and the operation in a steady state will be described. The values of the voltage sources VN1 and VP1 are selected to be substantially equal to the gate threshold voltages of the transistors TN2 and TP2, respectively. This prevents both the transistors TN2 and TP2 from being simultaneously cut off under any operating conditions. For this reason, it is possible to prevent the output impedance from becoming high and the potential from being unstable or the output voltage from fluctuating depending on the load condition. By making the value of the voltage source substantially equal to the gate threshold voltage of the transistor, the current flowing through the two transistors in the steady state is suppressed to a low value, and the standby power of the integrated circuit is reduced while the power is increased. The load drive capability is obtained. Operation under such a bias condition is generally referred to as class AB operation. Now, assuming that the current values flowing through TN2 and TP2 are IC1 and ID1, respectively, these currents are converted into TP3 by a current mirror circuit including P-channel MOS transistor pairs TP1 and TP3 and N-channel MOS transistor pairs TN1 and TN3. Is converted to a current ID2 flowing through the TN3 and a current IC2 flowing through the TN3. The current ratio between IC1 and IC2 is almost equal to the β ratio between transistors TP1 and TP3, and the current ratio (mirror ratio) between ID1 and ID2 is almost equal to the β ratio between transistors TN1 and TN3. That is,
M_p= IC2 / IC1 = β_TP3/ Β_TP1
M_N= ID2 / ID1 = β_TN3/ Β_TN1
It is. By setting this ratio to a value of 1 or more, the current can be amplified and the driving capability of the next stage load (terminals 6 and 7) can be increased. In the present invention, this ratio is selected to a value of about 1 to 10. Like the first push-pull circuit, the values of the voltage sources VN2 and VP2 are set to be substantially equal to the gate threshold voltages of the transistors TN4 and TP4, respectively. Thus, the second push-pull circuit also performs the class AB operation.
[0118]
Now, what happens when the first push-pull circuit deviates from the steady state, that is, the state where IC1 = ID1 holds, will be described. The current value when the output voltage is forcibly changed from the steady state by the voltage δV is expressed as follows.
[0119]
IC1-ID1 =-(√ (2β_NI) + √ (2β_PI)) × δV + (βN−βP) / 2 × δV^Two
Where β_NAnd β_PIndicates the β of the transistors TN2 and TP2, respectively, and I indicates the current flowing through the first push-pull circuit in a steady state (that is, I = IC1 = ID1).
[0120]
Now, for the sake of simplicity, the characteristics of TN2 and TP2 are almost complete, and β_NAnd β_PAre equal (β = β_N= Β_P), The above equation gives
IC1-ID1 ≒ -2√ (2βI) × δV
It becomes. Also, the mirror ratio of the two current mirror circuits is equal (M = M_N= M_P)
IC2-ID2 ≒ -2 × M × √ (2βI) × δV
It becomes.
[0121]
For example, M = 5, β = 1 mA / V^Two, I = 0.2 μA, IC2-ID2 = 20 μA when the output voltage drops by 0.1 V (δV = −0.1 V).
[0122]
In other words, a driving current of 20 μA, which is sufficiently large with respect to the steady current of 1 μA (0.2 μA × 5) of IC2 and ID2, is obtained even for a small change of 0.1 V in the output voltage. Therefore, the terminal 6 can be driven to the minimum VSS and the terminal 7 can be driven to the maximum VCC even for a slight change in the output voltage, to the limit of the power supply voltage range. In the driving direction, the terminal 7 is driven to VCC when the output voltage decreases, and the terminal 6 is driven to VSS when the output voltage increases. Accordingly, when there is an error in the output voltage, the second push-pull circuit is driven by the signal obtained by amplifying the error, and the operation is performed to eliminate the error in the output voltage. Therefore, a significantly higher driving capability can be provided as compared with the case of simply driving with a source follower circuit as in the conventional example. Further, even if the bias current in the steady state is suppressed to a sufficiently low value, a high drive current can be obtained by amplifying the error. Further, as can be easily understood from the above equation, this circuit operates symmetrically with respect to the direction of the error, so that the same driving capability can be obtained for charging and discharging of the output.
[0123]
Next, the accuracy of the present circuit as a voltage follower will be described. In this circuit, an error in the output voltage is detected by the first push-pull circuit, and the amplified signal is used to drive the second push-pull circuit. Therefore, the output voltage accuracy (input / output voltage difference) is determined by the voltage accuracy (input / output voltage difference) of the first push-pull circuit. In the first push-pull circuit, when a steady state, that is, a condition in which IC1 = ID1 holds, is obtained, a relationship between the input voltage V (IN) and the output voltage V (OUT) is obtained, and the following equation is obtained.
[0124]
V (OUT) −V (IN) = β × (VN1−VTN) − (VP1−VTP) / (β_R+1)
here
β_R= √ (β_TN2/ Β_TP2)
, And VTN and VTP are the absolute values of the gate threshold voltages of the N-channel and P-channel MOS transistors, respectively. As is apparent from this equation, by giving VN1 and VP1 characteristics that change in accordance with changes in VTN and VTP, and by appropriately selecting the β of the transistor, the N-channel transistor and the P Even if the element characteristics of the channel transistor change independently, the voltage difference between the output and the input can be made zero. The voltage source as described above can be easily configured by connecting the gate and the drain of each channel conductivity type MOS transistor and flowing a predetermined current through it, as described in the next embodiment. In general, even if there are variations in characteristics between elements of different conductivity types, since the transistors of the same conductivity type go through the same manufacturing process, the characteristic difference between the elements can be suppressed to a sufficiently small value. In particular, when the gate width and the gate length are designed to have sufficiently large values compared to the processing accuracy with respect to variations in the processing shape, the characteristic difference between the element pairs can be further reduced. For example, taking the gate threshold voltage as an example, the difference between pairs of elements of the same conductivity type can be easily reduced to about 20 to 30 mV or less, but the difference between the elements of different conductivity types can be easily reduced. Generally, the variation is about 200 mV at the maximum, which is about one digit larger. As described above, the voltage accuracy (input / output voltage difference) of the first push-pull circuit is suppressed to about 20 to 30 mV, which is determined by the threshold voltage difference between the transistor pair, which is about one digit lower than the conventional method.
[0125]
Now, a transient operation will be described with reference to FIG. Now, consider a case where the input voltage V (IN) decreases from time t0 to t1 and increases from time t4 to t5. Since the output does not immediately follow immediately after the input voltage drops, the transistor TN2 is cut off from the time t1 to the time t2, and the value of the current IC1 becomes almost zero. On the other hand, ID1 increases, and the voltage V (6) at the terminal 6 drops to almost VSS (0V). As a result, the driving capability of the transistor TP4 increases, and the output OUT is discharged at a high speed. After the time t2, when the difference between the output voltage and the input voltage decreases, the transistor TN2 starts to conduct, and finally at the time t2 when the voltage difference between the input and the output disappears, IC1 = ID1, and a steady state is established. When the input voltage rises, symmetrically, the voltage at terminal 7 rises to VCC, charging the output at high speed.
[0126]
As described above, according to the present invention, even if there is a variation in the manufacturing process, the error between the input and output voltages is small, and the voltage follower that can charge and discharge a large-capacity load at high speed in a transient state. Can be provided. In addition to the application as a voltage follower, the present circuit can be used as a high-performance current detection circuit by inputting a signal current to the output terminal OUT and extracting an output from the terminal 6 or 7.
[0127]
Next, an embodiment in which the above-described circuit is applied to an intermediate voltage (VCC / 2) generating circuit of a dynamic memory will be described with reference to FIGS. FIG. 31 shows a configuration example of the intermediate voltage generation circuit according to the present invention. In the figure, 30 is a reference voltage generating circuit, 31 is a first complementary push-pull circuit, 32 is a current mirror type amplifier circuit, and 33 is a second complementary push-pull circuit. The reference voltage generation circuit generates an intermediate voltage at the terminal 34 by dividing the power supply voltage in half by two resistors R3 and R4 having the same resistance value. By using the same type of elements for the resistors R3 and R4, a fairly accurate value can be obtained for the intermediate voltage. It should be noted that the element for obtaining the intermediate voltage is not limited to a resistor, and it is obvious that a similar circuit can be formed using, for example, a MOS transistor or the like. The first push-pull circuit is basically the same as the push-pull circuit 1 shown in FIG. Here, a resistor R5 and an N-channel MOS transistor TN10 are used instead of the voltage source VN1, and a resistor R6 and a P-channel MOS transistor TP10 are used instead of the voltage source VP1. Thus, as described in the previous embodiment, the voltage of terminal 35 is always automatically set to a value higher than input terminal 34 by almost the gate threshold voltage of the N-channel MOS transistor. Can be. The resistance value is selected so that the current flowing through R5 or R6 becomes a small value of about a fraction to one-tenth of the current flowing through R3 or R4. This is because even if the characteristics of the N-channel transistor and the P-channel transistor vary independently and the current value flowing (or flowing) from the push-pull circuit to the reference voltage generating circuit fluctuates, the voltage at the terminal 34 is affected. This is to prevent fluctuation. The current mirror type amplifier circuit 32 has exactly the same configuration as the current mirror type amplifier circuit 2 shown in FIG. The second push-pull circuit is basically the same as the push-pull circuit 3 shown in FIG. Here, an N-channel MOS transistor TN14 is used instead of the voltage source VN2, and a P-channel MOS transistor TP14 is used instead of the voltage source VP2. By doing so, similarly to the first push-pull circuit, the value of the bias current flowing through the push-pull circuit is kept from changing with the change in the threshold voltage of the transistor. With the above-described circuit configuration, a high-precision intermediate voltage can be obtained for the output HVC, and the load capacitance CL can be charged and discharged at high speed.
[0128]
32 (a) and 32 (b) show the results obtained by computer analysis of the performance comparison between the present circuit system shown in FIG. 31 and the conventional circuit system shown in FIG. In FIG. 32A, the horizontal axis represents the difference between the absolute values of the gate threshold voltages of the N-channel transistor and the P-channel transistor, and the vertical axis represents the value of the intermediate voltage. From this result, in the conventional circuit, when the threshold voltage difference fluctuates by ± 0.2 V, the output voltage fluctuates by about ± 100 mV (about ± 13% with respect to 0.75 V). In the circuit (1), the output voltage fluctuation is about ± 8 mV (about ± 1% with respect to 0.75 V), which can be reduced by one digit or more compared to the related art. FIG. 32 (b) plots the rise time of the output voltage after the power is turned on against the power supply voltage. The rise time is defined as the time when the output voltage reaches 90% of the steady value. The value of the load capacity is assumed to be the total capacity of the bit line precharge power supply and the plate electrode of the 64M bit DRAM. As can be seen from this analysis result, according to the circuit of the present invention, the load can be raised in about one digit shorter time than the conventional circuit.
[0129]
FIG. 33A is a circuit diagram showing another embodiment of the present invention. In the figure, reference numeral 40 denotes a complementary push-pull type voltage follower circuit, and reference numeral 41 denotes a tri-state buffer. The voltage follower circuit is basically the same as the push-pull circuit 1 in FIG. Here, the tri-state buffer operates so as to supplement the driving capability of the push-pull circuit. The tri-state buffer includes a P-channel transistor TP21 and an N-channel transistor TN21 for driving a load, two differential amplifier circuits (comparators) AMP1 and AMP2 for driving these transistors, and two voltages for setting an offset amount. It comprises a source VOSL and a VOSH. The operation of this circuit depends on which of the following three voltage conditions applies.
[0130]
(1) V (OUT)> V (IN) + VOSH
(2) V (IN) + VOSH> V (OUT)> V (IN) -VOSL
(3) V (IN) −VOSL> V (OUT)
Under the voltage condition (1), the voltage of the output OUT becomes higher than the voltage of the terminal 43, and the voltage of the terminal 45 becomes a high voltage level (VCC). Further, the voltage of the terminal 44 also becomes a high voltage level (VCC). Therefore, the N-channel transistor TN21 conducts, the P-channel transistor TP21 cuts off, and discharges the load. Under the voltage condition (2), the voltage of the output OUT becomes lower than the voltage of the terminal 43, and the voltage of the terminal 45 becomes a low voltage level (VSS). Further, the voltage of the terminal 44 maintains a high voltage level (VCC). Therefore, the two transistors TN21 and TP21 are both cut off, and the output is in a high impedance state. Under the voltage condition (3), the voltage of the output OUT becomes lower than the voltage of the terminal 42, and the voltage of the terminal 44 becomes a low voltage level (VSS). Further, the voltage of the terminal 45 maintains a low voltage level (VSS). Therefore, the N-channel transistor TN21 is cut off and the P-channel transistor TP21 becomes conductive, charging the load. Thus, there are three states (discharge when the output voltage increases beyond a certain range around the input voltage, charging when the output voltage decreases below a certain range, and neither charging nor discharging if within the certain range) ( (Tri-state). The operation of this circuit during a transition is shown in FIG. Now, consider the case where the input voltage V (IN) drops at time t0 and rises at time t2. At the time of falling, the voltage of the terminal 45 becomes VCC from time t0 to time t1 when the output voltage becomes equal to “(voltage in a steady state) + VOSH”, the transistor TN21 is turned on, and the load is discharged. Further, at the time of rising, the voltage of the terminal 44 becomes VSS from time t2 to time t3 when the output voltage becomes equal to “(voltage in a steady state) −VOSL”, the transistor TP21 is turned on, and the load is charged. .
[0131]
In this way, by combining the push-pull circuit with the tri-state buffer, when the voltage error between the input and the output becomes larger than a certain level, the transistor having a high driving capability is turned on to increase the response speed in the transient state. be able to. It is possible to speed up the convergence to the set voltage by setting the values of the two voltage sources VOSL and VOSH as small as possible for setting the offset amount. However, in order to avoid malfunction, the differential amplifier circuit (comparator) AMP1 is used. And a value sufficiently higher than the input offset voltage of AMP2. When a circuit is constituted by MOS transistors, this value is desirably 50 mV or more. The circuit configuration of the tri-state buffer is not limited to the example shown here, and any other system may be used as long as the same function is realized.
[0132]
Next, an embodiment in which a voltage follower using a tri-state buffer is applied to an intermediate voltage (VCC / 2) generating circuit of a dynamic memory will be described with reference to FIGS. FIG. 34 shows a configuration example of the intermediate voltage generation circuit according to the present invention. 34, reference numeral 50 denotes a reference voltage generation circuit, 51 denotes a voltage follower circuit described with reference to FIG. 29, and 52 denotes a tri-state buffer. In this case, by adding a tri-state buffer to the intermediate voltage generating circuit shown in FIG. 31, the restoration ability when the voltage error between input and output becomes large is enhanced. Hereinafter, the configuration and operation of the tri-state buffer will be described. The feature of this embodiment lies in that the first push-pull circuit is used as it is, an error voltage is detected using the difference in the mirror ratio of the current mirror circuit, and the tri-state buffer is activated. In FIG. 34, TP36 and TP37 are P-channel MOS transistors, TN36 and TN37 are N-channel MOS transistors INV1 and INV2 are inverters, TP38 is a P-channel MOS transistor configured to drive a load by the output of the inverter INV1, and TN38 is an inverter INV2. N-channel MOS transistors adapted to drive a load with the output of FIG. TP32 and TP36 and TP32 and TN37 each constitute a current mirror circuit. Here, the current flowing through the transistor TN31 is denoted by IC1, the current flowing through the transistor TP31 is denoted by ID1, the current flowing through the transistor TN36 is denoted by ID2, and the current flowing through the transistor TP36 is denoted by IC2. The relationship between the output voltage error δV and IC1 and ID1 is as described above.
IC1-ID1 ≒ -2√ (2βI) × δV
Can be approximated. The mirror ratio of the current mirror circuit is
M_P1= IC2 / IC1 = β_TP36/ Β_TP32
M_N1= ID2 / ID1 = β_TN36/ Β_TP32
Then, the following expression is obtained.
IC2 / M_P1-ID2 / M_N1{-2} (2βI) × δV
Now, when an offset voltage Vos is applied to the output, it is assumed that IC2 = ID2, and the current value at that time is I2_TwoAnd the offset voltage Vos is
Vos @ I_Two/ (2 × α) × (M_P1-M_N1) / (M_N1× M_P1)
It is expressed as here,
α = √ (2βI₁)
Further, β is β, I of a transistor constituting the first push-pull circuit.₁Is a current flowing through the first push-pull circuit in a steady state. For example, I₁= 0.2 μA, I_Two= 1 μA, β = 1 mA / V^Two, M_N1= 1, M_P1Assuming that = 0.2, the offset voltage Vos becomes -100 mV. That is, when the output voltage drops from the steady value by 100 mV or more, the input voltage of the inverter INV1 transitions from the low level to the high level, and the output voltage transitions from the high level to the low level, thereby turning on the driving P-channel MOS transistor TP38, Charge the load. Similarly, by appropriately selecting the constants of the transistors TP37 and TN37, the N-channel MOS transistor TN38 can be turned on to discharge the load when there is a predetermined positive offset.
[0133]
As described above, by adopting the circuit configuration as shown in this embodiment, the same function as that shown in FIG. 33 can be realized. Further, in this circuit method, since the offset amount is determined by the mirror ratio of the current mirror circuit, the offset amount can be accurately set if care is taken to reduce the characteristic difference between the transistor pair. Further, since there is no need to separately provide a high-precision differential amplifier circuit, high performance can be realized with low power consumption and a simple configuration.
[0134]
FIG. 35 shows a result obtained by computer analysis of the performance comparison between the present circuit system and the conventional circuit system shown in FIG. FIG. 35 is a graph in which the rise time of the output voltage after the power is turned on is plotted against the power supply voltage. The rise time is defined as the time when the output voltage reaches 90% of the steady value. The value of the load capacity is assumed to be the total capacity of the bit line precharge power supply and the plate electrode of the 64M bit DRAM. As can be seen from this analysis result, according to the circuit of the present invention, the rise time can be further reduced by about half an order as compared with the embodiment shown in FIG. The load can be started up in about one and a half times shorter than the conventional circuit. As described above, by combining the tri-state buffer with the push-pull circuit, it becomes possible to provide a voltage follower circuit capable of following the input at a higher speed. Since the voltage setting accuracy is determined by the push-pull circuit, the voltage error between the available powers can be made extremely small, as in the case of the previous embodiment.
[0135]
In the above embodiment, the circuit configuration for driving a large-capacity load in an integrated circuit (LSI) at high speed has been described. However, if an attempt is made to drive at a higher speed, a transient current during charging / discharging becomes a serious problem. For example, the load capacitance of the intermediate voltage generating circuit of a DRAM of about 64 Mbits is about 115 nF, but the current value when driving this with an amplitude of 1 V for 5 μs reaches 23 mA. This is equivalent to the current consumption value of the DARM. Driving at a higher speed causes an influence on main circuit characteristics, for example, generation of noise in a power supply line and reduction in reliability of a drive signal line. Not preferred due to danger. In general, in an ultra-highly integrated LSI, particularly in a memory, the entire LSI is often configured with a plurality of blocks of the same type, and at the time of operation, a configuration is often adopted in which only some of the blocks are activated. In such an LSI, it is effective to apply the embodiment described below.
[0136]
FIGS. 36 and 37 show an embodiment in which the present invention is applied to an intermediate voltage supply system of a dynamic memory (DRAM). In FIG. 36, MB0, MB1 to MBi are i + 1 memory blocks, 60 to 62 are word line selection circuits, 68 to 70 are intermediate voltage leads from each memory block, and 76 and 77 are two sets of intermediate voltages. Generating circuits, 74 and 75 are signal lines for supplying intermediate voltages HVC1 and HVC2 to each memory block from two sets of intermediate voltage generating circuits, and 71 to 73 are for supplying one of two signal lines to the memory block. This is a switch provided for each block. The memory block MB0 includes a memory cell array MA0 in which memory cells are two-dimensionally arranged, an input / output control for amplifying a signal read from the memory cell, outputting the amplified signal to the outside, and writing an external signal to the memory cell. It comprises a circuit block MC0, an input / output circuit 67 and the like. DL0, DL0 #, DLj # are data lines for transmitting signals to the memory cells, 63 is a plate electrode forming a counter electrode of the storage capacitor, and 64 is a precharge voltage arranged to make the data line an intermediate voltage when not selected. Supply lines, PC is a precharge signal line, SA0 to SAj are sense amplifiers for detecting and amplifying signals read from memory cells, and 65 and 66 are common input / outputs for transmitting signals between the input / output circuit 67 and each data line. Line pairs IO0 to IOj are IO gates for controlling connection between a data line pair selected by an address designating signal and a common input / output line pair.
[0137]
Now, let us consider a case where only one block MB0 is selected from the (i + 1) memory blocks to be in an operation state. At this time, one word line in MA0 is selected by the word line selection circuit 60, and transitions to a high level. At the same time, the switch 71 is controlled, and the intermediate voltage lead line 68 is connected to the intermediate voltage supply signal line 75. On the other hand, the lead lines 69 and 70 from the unselected memory blocks MB1 to MBi are connected to the intermediate voltage supply signal line 74. Thus, the load of i memory blocks is connected to the intermediate voltage generating circuit 76, whereas the load of only one memory block is connected to the intermediate voltage generating circuit 77. For example, when i = 15, the load capacity driven by the intermediate voltage generating circuit 77 is 1/15 of the load capacity driven by the intermediate voltage generating circuit 76. Therefore, even if the same circuit is used for 76 and 77, the intermediate voltage of the selected block MB0 operates 15 times faster than the intermediate voltage of the non-selected block. From the viewpoint of circuit performance, the response speed of the unselected memory block is independent of the performance of the memory. Therefore, the performance of the entire memory can be improved with almost no increase in transient current. FIG. 37 shows a temporal change of the intermediate voltage when the power supply voltage changes during the memory operation. That is, it is assumed that the voltage VCC has dropped between time t0 and time t2. It is also assumed that memory block MB0 is selected from time t0 to t1 and after time t3, and memory block MB1 is selected from time t1 to t3. From time t0 to time t1, block MB1 is not selected, so that intermediate voltage V (69) responds slowly, whereas block MB0 is selected, so that intermediate voltage V (68) is low. Following fast. When the block MB1 is switched to the selection and the block MB0 is switched to the non-selection at the time t1, the voltage V (69) immediately changes toward the voltage to be set. As described above, according to the present embodiment, a large-capacity load such as an intermediate voltage of a dynamic memory can be driven at a substantially high speed without substantially increasing a transient current. In this example, an example in which the present invention is applied to an intermediate voltage of a dynamic memory has been described. However, the application range is not limited to this. The present invention can be generally applied to integrated circuits.
[0138]
Although the details of the present invention have been described with reference to the embodiments, the scope of the present invention is not limited thereto. For example, the case where an LSI is constituted by CMOS transistors has been mainly described here. However, an LSI using a bipolar transistor, an LSI using a junction type FET, a BiCMOS type LSI combining a CMOS transistor and a bipolar transistor, and a silicon Other materials, for example, LSI in which elements are formed on a substrate of gallium arsenide or the like can be applied as they are.
[0139]
In this embodiment, a current mirror circuit is used as a current amplifier circuit, but another current amplifier circuit can be used.
[0140]
【The invention's effect】
As described above, according to the present invention, the input / output control circuits connecting the data lines and the I / O lines are alternately arranged on the left and right sides of the memory cell array, and the transfer impedance between the data lines and the I / O lines is reduced. By adopting a circuit configuration that changes between the reading operation and the writing operation, it is possible to operate stably at high speed even at a low voltage.
[0141]
Further, the present invention is also suitable for a parallel test, and can greatly reduce the test time.
[0142]
Furthermore, according to the present invention, since the gate transistor of the word line drive transistor operates at a low level, it operates stably as a word driver even if the power supply voltage decreases. In addition, the voltage conversion circuit which constantly raises the data line voltage VL to a voltage VCH higher than the data line voltage VL by the threshold voltage VT of the switch transistor of the memory cell and operates as a power supply of the word driver has its rectifier. The gate voltage of the transistor for use can be higher than the drain voltage by a threshold voltage or more, and the backflow of charges can be prevented, so that the output voltage can be increased to 2 VL which is the theoretical value of the voltage doubler generation circuit. Further, by using the oscillation circuit and the timing generation circuit using the RC delay, the delay time between the oscillation frequency and the timing becomes stable with respect to the power supply voltage fluctuation, so that the voltage conversion efficiency can always be kept in the best state. Further, by selecting three types of threshold voltages of the transistors, it is possible to achieve low voltage stabilization, high speed, and low power consumption. Thus, a semiconductor integrated circuit that operates stably even when the power supply voltage is the electromotive force of one battery can be realized.
[0143]
Further, according to the present invention, in a highly integrated LSI, a circuit configuration for driving a large load capacitance at high speed with high voltage accuracy, or a circuit for driving a large load capacitance at high speed without flowing a large transient current We can provide a method. For example, in the conventional circuit, if the output voltage fluctuates by about 13% with respect to 0.75 V when the threshold voltage difference of the transistor is 0.2 V, according to the present invention, it is suppressed to about 1%. Thus, the voltage accuracy is improved by one digit or more, and the high-speed response is obtained so that the rise time of the output voltage after the power is turned on is improved by about one digit or more compared with the conventional circuit.
[Brief description of the drawings]
FIG. 1 is a diagram showing a first embodiment of the present invention.
FIG. 2 is a diagram showing a first embodiment of the present invention.
FIG. 3 is a diagram showing a first embodiment of the present invention.
FIG. 4 is a diagram showing a first embodiment of the present invention.
FIG. 5 is a diagram showing a first embodiment of the present invention.
FIG. 6 is a diagram showing a first embodiment of the present invention.
FIG. 7 is a view showing an effect of the present invention.
FIG. 8 is a diagram showing the effect of the present invention.
FIG. 9 is a diagram showing an embodiment in which the effect obtained by using FIGS. 1 to 6 is further enhanced.
FIG. 10 is a diagram showing an embodiment when a plurality of memory cell arrays exist.
FIG. 11 is a diagram showing an embodiment of a parallel test.
FIG. 12 is a diagram showing an example of a parallel test.
FIG. 13 is a diagram showing an embodiment of a parallel test.
FIG. 14 is a diagram showing an example of a parallel test.
FIG. 15 is a diagram showing an embodiment of a parallel test.
FIG. 16 is a diagram showing an embodiment of a parallel test.
FIG. 17 is a diagram showing an embodiment for writing an arbitrary write voltage to a memory cell.
FIG. 18 shows an embodiment of the present invention.
FIG. 19 is a timing chart.
FIG. 20 shows a conventional example and a timing chart thereof.
FIG. 21 shows a conventional example and its timing chart.
FIG. 22 shows an embodiment of the present invention.
FIG. 23 is a timing chart.
FIG. 24 shows an embodiment of the present invention.
FIG. 25 is a timing chart.
FIG. 26 shows an embodiment of the present invention.
FIG. 27 shows an embodiment of the present invention.
FIG. 28 is a view showing the effect of the embodiment in FIG. 22;
FIG. 29A is an example for explaining the basic concept of the present invention.
(B) is a diagram for explaining the operation during the transition.
FIG. 30 shows a conventional example of an intermediate voltage generating circuit for a DRAM.
FIG. 31 is a specific example in which the present invention is applied to an intermediate voltage generating circuit of a DRAM.
FIG. 32 illustrates an effect of the present invention.
FIG. 33 (a) is an embodiment for explaining another basic concept of the present invention. (B) is a diagram illustrating the operation.
FIG. 34 shows a specific embodiment applied to an intermediate voltage generating circuit of a DRAM.
FIG. 35 is a diagram illustrating the effect.
FIG. 36 is a view for explaining a specific embodiment in which another basic concept of the present invention is applied to an intermediate voltage driving method for a DRAM.
FIG. 37 is a diagram for explaining a change in the intermediate voltage in the embodiment of FIG.
[Explanation of symbols]
MA: memory cell array, CKT: input / output control circuit, RG0, RG1: read gate, WG0, WG1: write gate, SA0, SA1: sense amplifier, SWR0, SWR1: read switch, SWW0, SWW1: write switch, RO, RO￣: read line, WI, WI￣: write I / O line, dy: data line pitch, WD: word driver, XD: X decoder, VLG: voltage conversion circuit for memory array, VCHG: for word line Voltage conversion circuit, W: word line, φ￣P: precharge signal, FX: word line drive pulse generation circuit, φX: word line drive pulse, CP: charge pump circuit, RECT: rectifier circuit, VL: data line voltage or Internal (for array) power supply voltage, VCH ... Word line voltage conversion circuit output voltage, φ, φ￣, PA, PA￣ PB, PB￣: step-up pulse for word line voltage conversion circuit, OSC: ring oscillator output pulse, C, C1, C2, C3, C4, CA, CB, CD: capacitor, R, R1, R2: resistor, QD1, QP, Q9, Q10: P-channel MOS transistors, QT, QD2, QS, QD, QA, QB, QC, QP, Q1, Q8, Q11, Q19: N-channel MOS transistors, I1, I25, I30, I33: inverters, NA1, NA2 NAND circuit, NO1 NOR circuit, VEXT external power supply voltage, 1, 31, 40 ... first complementary push-pull circuit, 2, 32 ... current mirror type push-pull amplifier circuit, 3, 33 ... Two complementary push-pull circuits, 30, 50 ... reference voltage generating circuits, 41, 52 ... tri-state bus AMP1, AMP2: Differential amplifier circuit, MB0 to MBi: Memory block, 60 to 62: Word line selection circuit, 71 to 73: Switch, 76, 77 ... Intermediate voltage generation circuit (drive circuit), MA0 ... Memory cell array, MC0: signal amplification and input / output control circuit group, SA0 to SAj: detection amplification circuit (sense amplifier), IO0 to IOj: input / output gate, 67: input / output circuit.

Claims (10)

A plurality of memory cells provided at intersections of a plurality of word lines and a plurality of data lines, and a plurality of word drivers provided corresponding to the plurality of word lines;
A voltage conversion circuit that receives the first potential and generates a second potential,
The operating voltage of the plurality of word drivers is always higher than a data line voltage by a threshold value of a transistor in the memory cell or more,
When one of the plurality of word lines is selected, the corresponding word driver applies the second potential to the selected word line via switch means;
The voltage conversion circuit, a first capacitor having a first node and a second node,
A first MOS transistor having a source / drain path coupled between the first potential and the second node;
A second capacitor having a third node and a fourth node;
A second MOS transistor having a source / drain path coupled between the first potential and the fourth node;
A third capacitor having a fifth node and a sixth node,
A third MOS transistor having a source / drain path coupled between the first potential and the sixth node;
A gate of the first MOS transistor is connected to the fourth node;
A gate of the second MOS transistor is connected to the second node;
The semiconductor device according to claim 1, wherein a gate of the third MOS transistor is connected to the fourth node. In claim 1,
The switch means comprises a P-type MOS transistor;
A fourth MOS transistor having a source / drain path coupled between the first potential and the second node, the gate of which is connected to the first potential;
A semiconductor device, further comprising: a fifth MOS transistor having a source / drain path coupled between the first potential and the fourth node and having a gate connected to the first potential. In claim 1 or 2,
The voltage conversion circuit further includes a sixth MOS transistor having a source / drain path coupled between the first potential and the sixth node, and having a gate connected to the first potential. Semiconductor device. In any one of claims 1 to 3,
The first node is driven to the high level and the low level in a predetermined cycle,
The third node is driven at a low level when the first node is driven at a high level, and is driven at a high level when the first node is driven at a low level.
The semiconductor device according to claim 1, wherein the fifth node is driven at a high level when the first node is driven at a high level, and is driven at a low level when the first node is driven at a low level. In any one of claims 1 to 4,
The semiconductor device, wherein the voltage conversion circuit further includes a rectifying transistor having a source / drain path coupled between the sixth node and an output node for outputting the second potential. In claim 5,
The voltage conversion circuit further includes a second charge pump circuit for outputting a third potential higher than the second potential,
An output node of the second charge pump circuit is connected to a gate of a rectifying transistor. In claim 6,
The semiconductor device according to claim 2, wherein the second charge pump circuit applies a voltage higher than the first voltage to a gate of the rectifying transistor during a period when the five nodes are at a high level. 8. The semiconductor device according to claim 1, further comprising a decoder for receiving an address signal.
The memory cell is a dynamic memory cell,
The semiconductor device, wherein the word driver is a static word driver, receives an output of the decoder, and uses an output of the voltage conversion circuit as an operating voltage. In any one of claims 1 to 8,
The semiconductor device according to claim 1, wherein the first potential is 1.5 V or less. In any one of claims 1 to 9,
A semiconductor device, wherein each of the first to third MOS transistors is an N-type MOS transistor.

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