JPS6221323A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a large output level by constituting the titled device with a circuit controlled by a pre-stage circuit and including at least one bipolar transistor (TR) and at least one insulation gate field effect TR. CONSTITUTION:At least >= one voltage among voltages fed to terminals B1-Bn to which voltages being references to the operation of a combination circuit D including a bipolar transistor (TR) and a MIS TR are applied is kept higher than a voltage fed to a terminal A to which a voltage being a reference to the operation of a pre-stage circuit (c) is applied. Then the level of a signal outputted to an output terminal G of the circuit D is kept higher than the level of the signal inputted to the circuit D via a signal fine F. Thus, while high speed performance of the bipolar TR is utilized, a high level signal is generated.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a bipolar transistor and an insulated gate field effect transistor ( The present invention relates to a circuit using an M■S transistor (hereinafter referred to as an M■S transistor).

[Background of the invention]

2. Description of the Related Art Conventionally, as a circuit using bipolar transistors and MIS transistors, there is a semiconductor device disclosed in Japanese Unexamined Patent Publication No. 59-25423.

FIG. 17 is a configuration diagram of the semiconductor device.

The operation of the circuit and its problems will be explained with reference to FIG. This semiconductor device has a combination circuit of an 0MO8 (complementary MO3) and a bipolar transistor 7, and a combination circuit of an MIS transistor 6 and a bipolar transistor 8 connected in parallel. Below, the voltage of the negative power supply Vs, s
The explanation will be given assuming that Ov is Ov. When the potential of the input terminal 1 is Ov, the P-channel MIS transistor 4 is turned on, current flows to the base of the bipolar transistor 7, and the bipolar transistor 7 is turned on. On the other hand, the bipolar transistor 8 does not turn on because the base potential is Ov. As a result, a current flows to the output terminal 2, and the potential of the output terminal 2 increases. The potential of the output terminal 2 ultimately becomes a value obtained by subtracting the base-emitter forward voltage VBE of the bipolar transistor 7 from the voltage Vce of the positive power supply. In this manner, in the conventional circuit shown in FIG. 17, the potential at the output terminal 2 does not rise to the voltage Vcc of the positive power supply.

In addition to the above-mentioned circuit, there is a drive circuit disclosed in Japanese Patent Laid-Open No. 8431/1983 as a semiconductor device comprising a circuit combining a MIS transistor and a bipolar transistor.

FIG. 18 is a diagram showing the configuration of the semiconductor device described above.6 The circuit in FIG. 18 is a combination circuit of a reverse 0M03 circuit and a bipolar transistor connected in parallel between input and output terminals. The circuit shown in FIG. 17 described above outputs an inverted signal of the input, whereas the circuit shown in FIG. 18 outputs an inverted signal that is in phase with the input. That is, when the input terminal 10 becomes high level, the MIS transistor 13 is turned on, current flows to the base of the bipolar transistor 17, and the bipolar transistor 17 is turned on. On the other hand, P channel MIS) - transistor 15 is off, N channel MISI
- Since the transistor 16 is turned on, the base potential of the bipolar transistor 18 becomes Ov, and the bipolar transistor 8 is turned off. As a result, a current flows to the output terminal 11, and the potential of the output terminal 11 increases. At this time, the potential of the output terminal 11 is lower than the positive power supply Vcc by N
7 threshold voltages of the channel MIS transistor 13,
As the output level of the circuit shown in FIG. 18 increases to the value Vcc-VT-VBE obtained by subtracting the base-emitter forward voltage VBE of the bipolar transistor 17, the output level of the circuit shown in FIG.
The output level becomes even lower than the output level shown in FIG.

As described above, the conventional circuit cannot make the output level sufficiently high. If the output level is small, the input level of the next-stage circuit becomes small, which slows down the operation of the next-stage circuit, and the high-speed performance of the bipolar transistor cannot be fully demonstrated when viewed as an entire LSI. Further, this problem becomes more noticeable when conventional devices are miniaturized and it becomes necessary to lower the power supply voltage. Therefore, a circuit is desired that can produce a sufficiently large output level while fully utilizing the high driving ability of bipolar transistors.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that can improve such conventional problems, take advantage of the high driving ability of bipolar transistors, and obtain a sufficiently large output level.

[Summary of the invention]

In order to achieve the above object, a semiconductor device of the present invention includes a circuit controlled by a pre-stage circuit and including at least one bipolar transistor and at least one insulated gate field effect transistor; By operating with one voltage as a reference, and at least one of the reference voltages having a voltage value different from the voltage at which the preceding circuit that controls the circuit operates as a reference, high driving capability and large output amplitude can be obtained. I made it possible.

[Embodiments of the invention]

EMBODIMENT OF THE INVENTION Below, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is an embodiment diagram illustrating the concept of a semiconductor device of the present invention. FIG. 1 shows an example of a circuit that is powered by one person and has one output. Figure 1 ↓;

D is a combination circuit including a bipolar transistor and an MIS transistor, C is a pre-stage circuit that controls the circuit, A is a terminal that applies a voltage that serves as a reference for the operation of the MC,
B1 to Bn are terminals to which voltages are applied as a reference for the operation of the circuit. Further, E is an input terminal of the circuit C, G is an output terminal of the circuit, and a connecting line F is a signal line for transmitting a signal from the circuit C to control the circuit.

In the present invention, among the voltages applied to B1 to Bn,
By making at least one voltage higher than the voltage applied to terminal A, the level of the signal output to terminal G is changed to signal! The level should be higher than that of the signal input to the circuit via the IF. This makes it possible to generate high-level signals while taking advantage of the high-speed performance of bipolar transistors.

Here, the voltage applied to the terminal A or the terminals 81 to Bn may be at a constant level or a pulse as necessary, or in some cases, multiple voltages may be applied to one circuit C as a reference. You may also supply
There may be a plurality of signal lines F.6 The present invention is not limited to that shown in FIG. 1, and can be applied to multiple input and multiple output circuits, but for the sake of simplicity In the following, an embodiment based on the same configuration as that in FIG. 1 will be shown. Note that one circuit C is a CMO as shown in Fig. 2.
We will use an S inverter. In FIG. 2, the terminal A is connected to the positive power supply vA, but as described above, the connection is not limited thereto.

FIG. 3 is a configuration diagram of a semiconductor device showing a first embodiment of the present invention. In this embodiment, a pulse voltage serving as a reference for the operation of the circuit is applied to the terminal B1, and a level higher than the operating reference voltage VA of the preceding stage circuit C is output to the output terminal G.

The operation shown in FIG. 3 will be explained below using the voltage waveform shown in FIG. 4. When the input terminal E is set to Ov, the potential of the signal line F becomes a high level due to the pre-stage circuit C shown in FIG. 2, and the voltage V
It becomes stationary at A. At this time, the potential of the terminal B1 is VA in FIG. 4, but the threshold voltage of the P-channel M/S transistor 25 is set to VT26, and -VA+IVT 2
Set it to 61 or less to connect the P-channel M-S transistor to 25
All you have to do is turn it off. When the potential of the signal line F becomes high level, the N-channel M/S transistor 27 is turned on, the base of the bipolar transistor 26 becomes Ov, the bipolar transistor 26 is turned off, and the N-channel M/S transistor 27 is turned on.
Since the IS transistor 29 is turned on, the potential of the output terminal G becomes 0■. Next, raise the potential of input terminal E to VA, raise the potential of signal line F (see Figure 2),
Increase the potential of terminal B1 to more than vA. At this time, the P-channel MIS transistor 25 is turned on, and the N-channel MIS transistor 25 is turned on.
S transistor 27 is turned off, base current flows to bipolar transistor 26, and bipolar transistor 2
6 is turned on and the N-channel MIS transistor 29 is turned off, so a current flows to the output terminal G and the potential of the output terminal G rises. Since the potential of the output terminal G reaches the potential obtained by subtracting the base-emitter forward voltage VBE from the potential of the base of the bipolar transistor 26, let us assume that the desired output level is vA+vα (Vα≧0).

If the potential of terminal B1 is boosted to vA+vα+VBE,
A desired output level can be obtained at the output terminal G.

The potential of input terminal E is changed to Ov, and the potential of input terminal B is changed to Ov.

When the potential of the signal line F is returned to VA, the potential of the signal line F rises to VA as described above, the bipolar transistor 26 is turned off, the N-channel M/S transistor 29 is turned on, and the potential of the output terminal G becomes Ov. The potential of 81 at this time can be set to any value as long as it is less than VA+IVT261, as described above.

For example, it can be made equal to VA.

As described above, according to this embodiment, by arbitrarily setting the potential of B1 when the signal input from the signal line F is at a low voltage, the high-speed performance of the bipolar transistor can be utilized. You can get voltage output.

Note that in FIG. 3, the N-channel MIS transistor 29 for lowering the potential of the output terminal G can also be configured as shown at 30 in FIG. 5. That is, one circuit has a configuration in which a combination of an 0MO8 and a bipolar transistor in opposite directions are connected in parallel. In this case, the current flowing through the N-channel MIS transistor 40 is amplified by the bipolar transistor 42.

The potential of the output terminal can be lowered quickly.

However, in this case, the potential of the output terminal G is limited by the base-emitter forward voltage of the bipolar transistor 42, and therefore does not completely drop to Ov. If it is necessary to completely lower the potential of the output terminal G to Ov,
In parallel with the N-channel MIS transistor 29 in FIG.
30 in FIG. 5 may be installed. Note that in FIG. 5, the P-channel MIS transistor 41 has a signal line F connected to
This is to ensure that the bipolar transistor 42 is turned off by accumulating the charge at the base of the bipolar transistor 42 and extracting the charge when the voltage becomes v.

FIG. 6 is a configuration diagram of a semiconductor device showing a second embodiment of the present invention.

The difference between this embodiment and the embodiment shown in FIG. 3 is that in FIG.
While the source of the transistor 25 is connected to the terminal B1, in FIG. 6, only the source of the P-channel MIS transistor 51 is connected to the terminal B1, and is not connected to the collector terminal B2 of the bipolar transistor 52. It is. In other words, in the configuration shown in FIG. 6, only the base current of the bipolar transistor 52 needs to be supplied from the terminal B. Therefore, compared to the case where both the base and collector currents of the bipolar transistor 26 are supplied from B1 as shown in FIG. 3, the burden on the circuit that drives the terminal B1 is reduced, and high-speed operation is possible. Other operations are the same as in FIG. 3.

Note that in FIG. 6, the collector of the bipolar transistor 52 is connected to the terminal B2, and the potential can be set independently of the terminal B1 that supplies current to the base 55. Therefore, by keeping the potential of this terminal B2 higher than the potential of the base 55 of the bipolar transistor 52,
It is possible to reliably prevent the bipolar transistor 52 from becoming saturated. To do this, a pulse voltage with an amplitude greater than the base voltage must be applied to B in synchronization with the potential fluctuation of the base 55.
2, or the potential of B2 may be kept at a constant value higher than the upper limit of the potential of the base 55.

In the latter case, when the signal 1sF becomes a high level and the potential of the output terminal G transitions to a low level, a high voltage is applied between the collector and emitter of the bipolar transistor 52. At this time, the base 55 is connected to the N-channel MIS. Since the bipolar transistor 52 is grounded by the transistor 53, the breakdown voltage of the bipolar transistor 52 is determined by BVCES (collector-emitter breakdown voltage when the base is grounded), so there is no problem because it is higher than when the base is in a floating state.

In addition, in FIG. 6, when there is a possibility that the bipolar transistor 52 is temporarily deeply saturated due to fluctuations in the power supply voltage, the terminals B1 and B are connected as shown in the same figure.
A diode DI○ may be inserted between the terminals 2 and 2 to prevent the bipolar transistor 52 from becoming deeply saturated by causing current to flow through the diode when the potential of the terminal B1 becomes abnormally high. In addition, in FIG. 6, the circuit 30 that lowers the potential of the output terminal G may be configured only with the M/S transistor 29 as shown in FIG.
As mentioned above, it may be constructed of bipolar transistors and MIS transistors as shown in the figure, or both may be used in parallel.

FIG. 7 is a configuration diagram of a semiconductor device showing a third embodiment of the present invention.

The major difference between the circuits in FIG. 7 and FIG. 6 is that in FIG. 6, the circuit outputs an inverted signal of the signal input from the signal line F. In contrast to the so-called inverter operation, in FIG. 7, a so-called non-inverter operation is performed in which a signal in phase with the input F is output.

In FIG. 7, a bipolar transistor 83 is a transistor for supplying a current to an output terminal G to raise the potential of the terminal G, and an N-channel MIS transistor 84 is a transistor for supplying a current from an output terminal G to Vss, and a transistor for supplying a current to an output terminal G to raise the potential of the terminal G. Transistor for lowering the potential of G, other MI
The S transistor is for controlling on/off of the bipolar transistor 83 and MIS transistor 84.

The operation of the embodiment shown in FIG. 7 will be described below using the voltage waveform shown in FIG.

In the figure, in order to simplify the explanation, it is assumed that the potential of the terminal B2 is kept at a constant value higher than the upper limit of the potential of the base 76 of the bipolar transistor 83. A pulse voltage synchronized with potential fluctuations may be applied. When the potential of the input terminal E is vA, the potential of the signal line F becomes Ov by the cycle 1c, so the N-channel MIS transistor 75 is turned off, the P-channel MIS)-transistor 80 is turned on, and the N-channel MIS)-transistor 81 is turned on. Turn it off,
The potential of 87 is vA. As a result, N channel M
Transistor 77 turns on and bipolar transistor 8
3 is turned off and the N-channel intermediate S transistor 84 is turned on, so that the output terminal G becomes Ov. Next, input terminal E
When the potential of the signal 11F falls to Ov, the potential of the signal 11F becomes vA, and as a result, the gate 88 of the N-channel MIS transistor 75 becomes
will be charged to the voltage minus the threshold voltage.

On the other hand, since the P-channel M-S transistor 8o is turned off and the N-channel S-transistor 81 is turned on, the potential of 87 becomes Ov, and the N-channel MIS transistor 84
．． 77 is off.

In this state, if the potential of terminal B1 is boosted above VA, M
The gate 88 of the IS transistor 75 is connected in advance to v
Since it is charged to the voltage obtained by subtracting the threshold voltage of the N-channel MIS transistor 74 from A, the N-channel MIS transistor 74
IS) - Due to the self-capacitance between the gate 88 of the Langistav 5 and B1, 88 is boosted to a higher potential than B1. Therefore, a current flows to the base 76 of the bipolar transistor 83, and the potential of the base 76 is not limited by the threshold voltage of the N-channel MIS transistor 75 and rises to the potential of the terminal B1. As a result, the potential of the output terminal G rises to a value obtained by subtracting the base-emitter forward voltage VBE of the bipolar transistor 83 from the potential of B1.

If the desired output level is vA+vα, the potential of B1 may be set to vA+vα+VBE. Note that N-channel MI
S)-Langistav 4 sets the voltage at its gate 73 to vA
Therefore, when the gate 88 is boosted to a level higher than VA, it is turned off and serves to prevent current from flowing backward from the gate 88 to the signal line F. Next, when the potential of the input terminal E is raised to vA and the potential of the terminal B1 is lowered, the signal line F becomes Ov and the gate 87 becomes vA, and while the bipolar transistor 83 remains off, the N-channel intermediate S transistor 84 is turned on and the output terminal G becomes Ov. At this time, the base 76 of the bipolar transistor 83 is grounded through the N-channel, M-channel, and S transistor 77, so that the withstand voltage of the bipolar transistor 83 becomes high.
The bipolar transistor 83 is unlikely to be destroyed even if the high voltage remains applied to B2, as in the case of FIG. It becomes possible to generate high output level signals.

Note that as the circuit 86 for lowering the potential of the output terminal G, the circuit shown in FIG. 9 may be used as necessary, or the circuit shown in FIG. 9 and the N-channel MIS transistor 84 may be used in parallel. In addition, if there is a possibility that the bipolar transistor 83 may be temporarily deeply saturated due to fluctuations in the power supply voltage, etc., as shown in FIG. 6, connect a diode between B1 and B2 to reduce the potential of B1. What is necessary is to prevent the value from increasing abnormally with respect to 82.

FIG. 1O is a block diagram of a semiconductor device showing a fourth embodiment of the present invention.

The biggest difference in the circuits between Figures 7 and 10 is
In the figure, the collector and base of the bipolar transistor 83 are electrically separated, whereas in FIG.
By inserting an N-channel MIS transistor 103 between the collector and base of the bipolar transistor 104,
2, the base current and collector current are supplied.

The operation of this embodiment will be explained below. Note that the desired output level is vA+vα, and terminal B2 has vA+vα+V.
It is assumed that the voltage of BH is applied. Here VBE
is the base-emitter forward voltage of the bipolar transistor 104.

When terminal B1 is Ov, the potential of input terminal E is changed from VA to O.
When the voltage falls to V, the gate of the N-channel M/S transistor 103 becomes lower than VA as in the case of FIG.
It is charged to a potential obtained by subtracting the threshold voltage of channel MIS transistor 102. At this time, since the N-channel M/S transistors 105 and 108 are off,
A current flows from the terminal B2 to the base of the bipolar transistor 104, turning on the bipolar transistor 104, a current flows to the output terminal G, and the potential of the terminal G rises.

The base potential of the bipolar transistor 104 is vA, assuming that the threshold voltages of the N-channel MIS transistors 102 and 103 are VTI 02 p vTL03, respectively.
Since the potential of the output G only rises to VT102-VT103 and further drops by VBE, it is not possible to obtain an output level higher than VA as it is, so the gate 11
2 is charged, a pulse voltage is applied to the terminal B1, and the potential of the gate 112 is set to VA+ by the capacitor 100.
V(!+VBE+V7103 or more. As a result, the base potential of the bipolar transistor 104 becomes ■A
+vα+VBE, and the potential at output terminal G reaches the desired output level vA+vα. In this embodiment, the base potential of the bipolar transistor 104 is the terminal B2.
Therefore, even if the potential of terminal B2 drops for some reason, the bipolar transistor 104 will not be saturated.Next, when the potential of input terminal E is raised from Ov to VA, , signal line F is O
v, and the N-channel MIS transistor 103 and 1
07 is turned off, the P-channel M■S transistor 106 is turned on, and the N-channel MIS transistor 105 is turned on, so that the bipolar transistor 104 is turned off and the N-channel MIS transistor 108 is turned on, so that the potential of the output terminal G becomes Ov. In this embodiment as well, the circuit 113 that pulls down the output terminal G may have the configuration shown in FIG. 11 if necessary, or the circuit shown in FIG. 108 may be connected in parallel, as in the embodiment of FIG. In addition, in the above explanation, the potential of terminal B2 is vA+v
α + VBE is set at a constant level, but after the gate 112 is charged, V A + V from terminal B2&, :OV
A pulse voltage reaching a + VBE may be applied. At this time, since the potential of the gate 112 is boosted by the self-capacitance between the gate 112 of the N-channel M-S transistor 103 and the terminal B2, the capacitance 100. Terminal B1 is not necessarily required.

In this way, in this embodiment, in a circuit including a bipolar transistor and an MIS transistor, by setting the reference voltage for operation to a value different from the reference voltage of the preceding stage circuit that controls the circuit, the bipolar transistor By making full use of the high drive capability of the semiconductor device, it is possible to realize a semiconductor device with a high output amplitude higher than the reference voltage of the previous stage circuit.

By the way, in the embodiments described so far, the terminal B1
It is necessary to apply a pulse voltage to There are many types of circuits that generate pulse voltages, and their circuit configurations are well known, so they will not be explained here, but for example, a circuit that generates pulse voltages as shown in the voltage waveform of FIG. Ishihara, Miyazawa.

Co-authored by Sakai “256K 0MO3 Dynamic RAMJ with Static Column Mode with Cycle Time 50ns”
, Nikkei Electronics, February 11, 1985 issue,
There is a circuit shown in FIG. 7 for PP243-263. Furthermore, in the embodiments shown so far, a P-channel MIS transistor (for example.

In some cases, the source of 25) in Figure 3 is at a high potential.
It goes without saying that it is necessary to keep the potential of the well of the P-channel MIS transistor higher than the potential of the source to prevent the flow of excessive forward current between the source and the well, so-called latch-up. In this embodiment, there is a K-channel intermediate S transistor in which a high voltage is applied between the drain and source (for example, 29 in FIG. 3), but if there is a problem in terms of withstand voltage,
By inserting an N-channel MIS transistor with a gate potential of VA in series between the drain of the N-channel MIS transistor and the terminal to which the drain is connected, the N-channel connection that has the above-mentioned problem in breakdown voltage can be solved. The voltage applied between the drain and source of the S transistor can be reduced.

Although the present invention can be used in various ways, it is particularly suitable as a word driver for a dynamic semiconductor memory device. This is because, in order to realize a high-speed dynamic "type semiconductor memory device," it is necessary to drive the selected word line at high speed and high amplitude, increase the signal voltage to increase the S/N, and further increase the accumulated charge. Regarding the circumstances of 0 or more, which is due to the need to increase soft error resistance,
ITOH.

K, and SUNAMI, H, r High Density One Device Dynamic MOS Memory Cells''Hi
gh density one-device
dynamic MOS memory call
s', IEE PROC,, vol, 130
ePt,,1. No, 3. JUNE 1
983. Details can be found in ppl 27-135.

Next, an example will be shown in which the present invention is applied to a word driver of a dynamic semiconductor memory device.

FIG. 12 is a block diagram of a dynamic semiconductor memory, showing an N-bit memory cell array MCA and a group of peripheral circuits.

This memory cell array MCA has one word line WL.
and j data lines DL are arranged in an intersecting manner, and memory cells MC are arranged at N intersections between word lines and data lines. Address inputs Xo to Xn are provided to address buffer circuits ABX and ABY, respectively.

yo7Ym is applied, and its output is transmitted to the decoder/driver circuits XD and VD. Of these decoder/driver circuits XD and VD, the circuit XD drives the word line, and the circuit YD drives the write/read circuit RC, respectively, to write information to a selected memory cell MC in the memory cell array MCA, or CC reads information from the memory cell MC.
A read control circuit, this circuit CC controls the address buffer circuits ABX, ABY, and decoder/driver circuits XD, YD in response to a chip select signal C5, a write operation control signal WE, and an input signal DI.

Write/read circuit RC1 controls output circuit OC. The output circuit OC is a circuit for outputting the information read by the write/read circuit RC to the outside.

In the above configuration, by applying the circuit of this embodiment to the decoder/driver circuit 'XD, it becomes possible to drive the level of the word line WL at high speed and with high amplitude, and it becomes possible to drive the level of the word line WL at high speed and with high stability. can be realized.

In addition, in FIG. 12, the write/read circuit RC
A part of the circuit is placed at the end of the memory cell array MCA on the opposite side from the decoder/driver circuit VD, and the decoder/driver circuit VD is
The control signal from the driver circuit VD is sent to the memory cell array M.
It can also be controlled through the CA. Also, the 12th
In the figure, the X-system address input Xo-Xn and the Y-system address input YO-ym are input from separate input terminals.
to of Technical Papers"P, 1
As described in 2 to 13, it is also possible to use a method in which these input terminals are shared and input with a time difference, the so-called 1-address multiplex method 2'.

In that case, signals for controlling address capture, so-called RAS and CAS, may be used in place of the chip select signal C8 to drive the write/read control circuit.

FIG. 13 is an embodiment diagram that is a more specific version of FIG. 12, and shows a part of the memory cell array MCA and the decoder/driver circuit XD in more detail.

In FIG. 13, DECo and DECI are decoders, W
Do t W D 1 is a word driver, wL,
otWL□ is a word line, D Lo+D Lo is a pair of data lines, and MC, MCI are memory cells.

In addition.

EQ is an equalizer for making the data lines potential balanced, and SA is a sense amplifier.

Regarding the circuit configuration of the equalizer EQ and sense amplifier SA, please refer to the 1984 l5SCCr Digest.
Off Technical Papers J”Dige, sto
f Technical Papers”, P, 2
76 N277 etc., so I will omit it here.

Note that the decoders DECo and DECI are connected to terminals 13 and 13 respectively.
o.

The word drivers WDO and WDI to which the present invention is applied operate based on the voltage vA applied to the terminal 137, and the word drivers WDO and WDI operate based on the pulse voltage φX applied to the terminals 1.54 and 157, and the voltage vH1 applied to the terminals 155 and 158, respectively. Terminal 156,1
It operates based on the pulse voltage φL applied to the terminal 59. Here, the voltage vH is set to the bipolar transistor 150
Needless to say, the voltage should be set to a potential that does not saturate the voltage and the like.

The circuit configuration of the word driver WDot WDL includes N-channel M-S transistors 151, 165 and N-channel M-S transistors 152, 166 in parallel! The circuit is the same as that shown in FIG. 7, except that the Below, the first
The read operation in FIG. 13 will be explained using the voltage waveform in FIG. 4.

To start a read operation, data line pair DLO+D
After the LO is set to an equal potential of about 1/2 vA by the equalizer EQ, it is set in a floating state. On the other hand, all address buffer outputs AXOpAXO...AX
With all R set to Ov, precharge signal φP is set to Ov.
In this example, only two word drivers are shown, but in reality, all After raising the 0th and 5th precharge signal φP that simultaneously precharges the word driver, either the affirmative or negative address buffer output rises, and one of the N-channel MIS transistors in the decoder DEC rises accordingly. The gates of the unselected word drivers other than the word driver connected to the selected word line among the gates of the precharged MIS transistors become Ov. Here, a case is shown in which word @WLO is selected, and the gate of N-channel MIS transistor 148 remains precharged. On the other hand, N-channel MIS transistor 1
Since gate 64 is not selected, it becomes 0■. Also, D
Since the output of EC, becomes Ov, the unselected word line WL1
In the first order, the N-channel MIS transistor 165 in the word driver WD is turned on and fixed at Ov.Then, the word latch signal φL is lowered and the signal φX is set to VA while ov.
When the voltage is raised to +Vα+VBE, the gate of the N-channel MIS transistor 148 during wDo is precharged, so the potential of the word line WLo rises to vA+Vα in the same manner as the circuit operation in FIG. On the other hand, since the gate of the N-channel MIS transistor 164 in the WD is OV, it is not boosted, and the N-channel MIS
The transistor 164 is off, and the potential of the word line WL remains Ov. When the potential of the selected word line WLa rises, the N-channel MIS transistor 160 in the memory cell array turns on, and the potential of the word line WL remains Ov.
The signal is read out to the data line DLo, and the data @DL
, and the paired data line DLo.

The potential difference between the data line pair is amplified by the sense amplifier SA, information is rewritten in the memory cell, and is transmitted to the subsequent stage circuit. Next, the pulse signal φX is lowered to Ov, the latch signal φL is raised and the word line WLo is lowered to Ov, and then the data line pair is brought to the same potential of approximately L/2 V A by the equalizer EQ, while the address After all buffer outputs are brought down, the precharge signal φP is brought down to OV to perform precharging.
Prepare for the next action. In the read operation described above, since the circuit of this embodiment is applied to the word drivers WDOe WDI, . . . , the potential of the selected word line can be raised quickly and with high amplitude. As a result, the signal voltage and the storage voltage of the memory cell can be increased, and both high speed and high reliability can be achieved. In FIG. 13, as the circuit for generating the pulse signal φX, the circuit published in the Nikkei Electronics magazine referred to earlier may be used, or to achieve even higher speed, for example, the embodiment shown in FIG. 6 may be used. may also be used. In addition, in FIG. 13, a decoder is provided for each word driver, and a pulse signal φ
X is commonly applied to all word drivers, but if necessary, one decoder is provided commonly to multiple word drivers, and the pulse signal of only one of the word drivers sharing the decoder is decoded and applied. Of course, various modifications are possible, such as.

Also, here, the precharge voltage of the data line is V A
/2 is shown as an example, but it is not limited to this and can be set arbitrarily in the range of 0 to vA.

Note that in the above read operation, bipolar transistors in unselected word drivers, for example.

The base of 168 in WDl is a MIS transistor inserted by φX when the signal φX is OV, and between the base of the bipolar transistor and Vss when the signal φX rises.

For example, it is kept at Ov by 167 in WDl. Therefore, since the withstand voltage of the above-mentioned bipolar transistor is determined by BVCES as mentioned above, the collector is connected to a high voltage v
There is no problem even if it remains at H.

By the way, the configuration shown in FIG. 13 requires two positive power supplies, one for supplying voltage VA and the other for supplying voltage VH. Of course, it is possible to supply these power supplies separately from outside the chip, but it is also possible to supply only one of them from the outside and the other generated and supplied inside the chip based on this, or both of them can be supplied from outside the chip. It can also be generated internally with reference to another power source. Therefore, the first
3. Among the embodiments shown in Figure 3 or described above, those requiring two positive power supplies are connected to one external positive power supply. The voltage of the external positive power supply is determined by patent application No. 56-168698,
It is also possible to supply the voltage at a lower level using a voltage limiter circuit as shown in Japanese Patent Application No. 57-220083.

Also, in some cases, of the two power supplies required.

The lower voltage may be supplied from an external positive power supply, and the higher voltage may be increased and supplied by a circuit that boosts the voltage of the external positive power supply.

FIG. 15 is a diagram showing one embodiment of a booster circuit used in the present invention.

In this circuit, voltage vA is supplied from an external positive power supply to generate a high voltage V)I. The circuit shown in FIG. 15 basically consists of so-called charge pump type booster circuits CPl and CP2.
are arranged in parallel.

The operating principle of a charge pump type booster circuit is well known, so a description thereof will be omitted here. Here, the Zener diode 192 is used to leak current and prevent a further increase in potential when the voltage at the terminal 194 rises too much above the desired level VH, but it can be removed if unnecessary. It's okay.

Further, instead of the Zener diode 192, a plurality of ordinary diodes or MIS diode circuits in which the gate and drain of an M/S transistor are connected in the forward direction may be used. Also, as CP,,CP2,M
Although we have shown an example in which diodes composed of IS capacitors and MIS transistors are connected in three stages, generally the number of stages is n, and MIS
The threshold voltage of the transistor is V T p φs1~φS
31 If the pulse amplitude of φT1 to φT・3 is vA, then
The voltage obtained is approximately (n+1) (VA VT), and the value of n may be selected depending on the required value of vH.

When this circuit is applied to Figure 13, terminal 1 in Figure 15
The current that must be supplied by 94 increases when a word line is selected. Therefore, during the active period of the dynamic semiconductor memory, both CP1 and CF2 are operated to obtain a large supply current, and during the standby period.

It is also possible to operate only the CPI. This allows a large output current to be obtained with low power consumption.

FIG. 16 is an example of the voltage waveform of the pulse applied to CPI and CF2 in FIG. 15.

The figure shows an example in which only CPI operates during tst+, ie, standby period, and both CP1 and CF2 operate during t,op, ie, active period. For example, the chip select signal C8 or the RAS signal may be used to synchronize the activation time of CF2 with the word line selection time. In addition, when operating in a so-called page mode where information from memory cells on one word line is read out continuously, it is necessary to keep the potential of one selected word line at a high potential for a long time. In this case, even after the word line potential reaches a high level, CA
Of course, CF2 may be activated using the S signal or the like.

Although an example using two charge pump circuits has been shown here, it is of course possible to use one or more circuits as necessary. Furthermore, if the potential of the word line is raised very quickly, the potential of the terminal 194 in FIG. 15 may temporarily drop.

In that case, in order to prevent saturation of the bipolar transistor whose collector is connected to the terminal 194,
It is necessary to increase the capacitance of the capacitor and reduce the drop in potential. To this end, by connecting all the collectors of the bipolar transistors for supplying vH to the terminal 194, the parasitic capacitance of the terminal 194 can be increased by the collector capacitance of the bipolar transistors.

Also here.

Although φs1 and φs3 and φT1 and φT3 are shown as separate signals, they may be driven by the same signal depending on the case.

Note that if the bipolar transistor may be temporarily saturated due to fluctuations in the source voltage, the pulse signal φ
The output terminal of the circuit that generates X and the VH terminal 1 in Figure 15
94, as mentioned before, and the diode is turned on when the potential of φX is high with respect to vH to prevent saturation.6 [Effects of the Invention] As explained above, according to the present invention, in a circuit including a bipolar transistor and an M/S transistor, the reference voltage for operation is set to a value different from the voltage at which the preceding stage circuit controlling the circuit operates as a reference. Therefore, the high driving ability of the bipolar transistor can be fully utilized and a desired high output level can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a schematic configuration diagram of a semiconductor device showing the basic configuration of the present invention, FIG. 2 is a diagram showing a specific example of the front-stage circuit of FIG. 1, and FIG.
The figure is a configuration diagram of a semiconductor device showing a first embodiment of the present invention.
Figure 4 is the voltage waveform diagram of Figure 3, and Figure 5 is the circuit 3 of Figure 3.
0, FIG. 6 is a configuration diagram of a semiconductor device showing a second embodiment of the invention, FIG. 7 is a configuration diagram of a semiconductor device showing a second embodiment of the invention, and FIG. 7 is a diagram showing the voltage waveform, FIG. 9 is a side view of the configuration of the circuit 86 in FIG. 7, FIG. 10 is a configuration diagram of a semiconductor device showing the fourth embodiment of the present invention, and FIG. FIG. 10 is a side view of the configuration of the circuit 113, FIG. 12 is a side view of the configuration of a dynamic semiconductor device to which the present invention is applied, FIG. 13 is a diagram of an example configuration when the present invention is applied to a word driver, and FIG. The figure shows the voltage waveform of Fig. 1°3, Fig. 15 shows the charge pump type booster circuit used in the present invention, Fig. 16 shows the voltage waveform of Fig. 15, and Fig. 17 shows the first conventional method. The example diagram, FIG. 18, is a diagram of a second conventional example. A: Terminal that applies the voltage that serves as the reference for the operation of circuit C, B
, ~Bn: A terminal that applies a voltage that serves as a reference for the operation of the circuit i1D, C: A circuit that controls the circuit wID, D: A circuit that includes an M-S transistor and a piebola transistor, E: an input terminal, F: a signal line , G: Output terminal, VA: Voltage that serves as a reference for the operation of circuit C. 30.86, 113: A circuit that lowers the potential of the output terminal G, Xo-Xn: X address, yo-'ym: Y address, MCA: Memory cell array, MC. MC,, MC,: memory cell, [)L, DL,, DLl
:Data line, W L v W Lo * W L
1: Word line, ABX, ABY near address buffer circuit, XD, YD: Decoder, driver circuit, RC: Write/read circuit, CC: Write/read control circuit, OC: Output circuit, Do: Output, C8: Chip select Signal, WE: Write operation control signal, DI: Input, A
XOe AXRe AXO near address buffer output, D
ECa, DEC Engineering: Decoder, WDOI WDt:
Word driver, SA: sense amplifier, EQ: equalizer, φP nib recharge signal, φL: latch signal, φ
X: Pulse signal, CPI, CF2: Charge pump circuit, 192: Zener diode, φS1y φS2e
φs3: CPI activation pulse, φT1. φT2y φT9
:CP2 activation pulse. Patent applicant: Masatoshi Isomura, Patent Attorney, Hitachi, Ltd.5. '1.゛. '1'-Go・Pa 1 Figure 3 Cow Figure 5 Figure 6 Figure L, -J, D Figure 7 Figure 8 Figure 9 Figure G Figure 10 Figure 11 Figure 12 Figure 14 Figure 15 Figure 16

Claims (5)

[Claims] (1) The circuit is controlled by a pre-stage circuit and includes at least one bipolar transistor and at least one insulated gate field effect transistor, and the circuit operates with at least one voltage as a reference, and the circuit operates with reference to at least one voltage, and A semiconductor device characterized in that at least one of the voltages that control the circuit has a voltage value different from a voltage at which a pre-stage circuit controlling the circuit operates as a reference. (2) N controlled by the previous stage circuit and connected in cascade
Output voltage raising means consisting of a channel field effect transistor, a P channel field effect transistor, and a bipolar transistor with a dependent connection point connected to the base;
and an N-channel field effect transistor, a bipolar transistor whose base is connected to a cascade-connected field effect transistor, or a parallel connection thereof. (3) The output voltage raising means is characterized in that a reference voltage is connected to the source of the P-channel field effect transistor, and a voltage different from the reference voltage is connected to the collector of the bipolar transistor. A semiconductor device according to scope 2. (4) The output voltage raising means is configured such that the control signal from the previous stage circuit is connected to one gate of the cascade-connected field effect transistor via the drain and source of the field effect transistor, and the field effect transistor 3. The semiconductor device according to claim 2, wherein the semiconductor device is connected to the other gate and the output lowering means via a circuit. (5) The output voltage raising means applies a reference voltage to one gate of the cascade-connected field effect transistors;
5. The semiconductor device according to claim 4, wherein a voltage different from the reference voltage is applied to the drain of the field effect transistor and the collector of a bipolar transistor whose base is connected to the subordinate connection point.