JPS58188388A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce the access time without complicated manufacture process, by boosting a word line at a voltage higher than the power supply voltage for a memory cell at the selection of the word line and the power supply voltage for a peripheral circuit other than the cell. CONSTITUTION:When a control input VC is VDD initially and changes to a VSS, the voltage VS is boosted to 2 VDD at a boosting circuit 21. Further, an input voltage Vin is VDD initially and a word line 10 is VSS at a word line drive circuit 20. When the word line 10 is selected, the voltage Vin is VSS after the potential of the control input VC changes from VDD to VSS, the voltage VS is impressed to the word line 10 via a drive FETP6 and the line 10 is boosted. Thus, at the selection of the line 10, the leading speed of the voltage of the line 10 is quickened by boosting the line 10 at a voltage 2VDD higher than the VDD for a memory cell 11 and the VDD for the peripheral circuit other than the cell, and the effective driving ability of the bit line is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a state-type semiconductor memory device that is applied to integrated circuit memories, 1-chi, f'v microcombinator memories, and the like.

[Technical background of the invention]

In this semiconductor memory device, a large number of state and memory IJ cells are provided in the row direction and the tick direction,
A pair of bit lines are commonly connected to the memory IJ −j=6 in the same column, and the memory cells 11 in the same row are connected as shown in FIG.
One word line 10 is selected in common, and the row decoder (
The word line drive circuit 11'l) 1 drives the word line 10 based on a row selection signal from the word line drive circuit 11'l) (not shown).

Each of the memory cells 1 includes, for example, an enhancement type MO8) transistor Tl1T1% load resistance element R1+Rs for driving and a transfer r
-), and one end of each of the pair of transfer transistors T1+T4 is connected to a pair of bit lines 13 and 14, and the transfer transistor Tl
Each of the 174 dates is word #i! 10. (9) The word line drive circuit 12 has conventionally been formed using a CMog transistor as shown in FIG. That is, between the vD11 power source and the vsstlt source, a P-channel MOB transistor T of the enforcement type and nine N-channel MOB transistors T (9) are connected in series, respectively, and a row selection signal is commonly applied to each R. vi is applied from the row decoder, and a word line 10 is connected to the connection point between both transistors 'r, , 'r. When the row selection signal VlA is applied to the word selection circuit 12 as shown in FIG. 4(a), the word breakdown voltage vl#'i is boosted as shown in FIG. 4(b). In this case, the voltage of the word line 10 needs to be increased to a level higher than the threshold voltage of the transfer transistors 'r, , 'r4 of the memory cell 1. In such a semiconductor memory device, the following two series of times 'r, , 'rC occupy most of the access time. That is, the time Tw required to open the transfer rout of the memory cell located farthest from the word line drive circuit J2 after the word line 10 starts operating 1IIA, and the voltage written to the memory cell horn. Drive transistor Tl+ by information
71 drives a pair of pin and g lines 13 and 14, creates a potential difference between the pair of bit lines 13 and 14, and this potential difference is increased by 7 seconds! (not shown) is the time Tc required to create a senseable pressure difference that can be detected and amplified.

The wc5 diagram shows the first
Word line starting voltage in the figure ■mu, word 1I7NIl! It shows the change over time of the trend voltage V, where 2 is the word-boosted voltage, and Vl is the voltage at which the transfer r-) of the memory cell at the end of the word line is sufficiently opened.

Figure 6 shows 1 and 2 in order to explain the above-mentioned t and time C.
Figure C1k'y 11J13, 14011g, pressure VI
ΔV is the bit 1 voltage VIL based on the two voltage information v, , vL (VM>VL) held in the memory 7 in Figure 3.
This is the senseable it pressure that occurs between +hL. That is,
Initially, the bit lines 13 and 14 are in a precharged state, and the bit lines 13 and 14 are in a precharged state, and the bit lines 13 and 14 are both KA
level potential, but when the word line 10 is applied with an external voltage at time tl by a stepped voltage that is slightly higher than the threshold Ax voltage VTM of the transfer transistors T, T4, the driving transistor T3 becomes conductive due to the voltage information V. and further word l
1110 is boosted and the transfer transistor 〒4, which has also become conductive, lowers the pit line voltage V@L, and after a time 'rc from t, the pit line voltage VIL+
A voltage difference ΔV occurs between VIL.

[Problems with dorsal plasma technology]

By the way, in a static RAM whose access time is several tens of nanoseconds, the time Tw is about 40 to 60 am and Tc is about 10 to 20 mm. These two times Tw
, shorten 〒C to shorten memory access time, ^
Conventionally, the following method has been adopted to aggregate high-speed memory. That is, since the time 〒W largely depends on the signal lIl# caused by the electric resistance R and the electric capacitance C of the word line 10, Tw is made small by making the above-mentioned R small. Specifically, it is possible to use low-resistance all-pole silicide for the word line 10 (which also serves as y-h for the transfer transistors TI, T, in each memory cell), or to use a layer made of aluminum in parallel on the polysilicon word line. This is a method of connecting the distribution layers. However, all of these methods have problems such as complicated manufacturing/processes, high lot production costs, and low yields.

Also, regarding the time TC, its substance is connected to the bit line via the transfer transistor and the driving transistor in the memory cell in series! This is the time to discharge the nine charges accumulated during recharge. Therefore, as a measure to shorten this discharge time, efforts are being made to reduce the p-am filling amount of the bit line, which is the biggest factor, in order to reduce the capacitance of the bit line. Physically, efforts have been made to lower the impurity concentration of semiconductor substrates, but as transistors have become smaller, it has become physically impossible to lower the impurity concentration of the substrate. Therefore, attempts have been made to increase the discharge speed of the 9-bit line through the transfer transistor by increasing the size of the transfer transistor, but increasing the transfer transistor speed in this way would conversely increase the capacitance of the word line and Since the time Tw will increase, the overall access time will not be shortened.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and is manufactured! The present invention provides a semiconductor memory device in which access time can be shortened without complicating the process, increasing lot production cost, or decreasing yield.

[Cost of invention]

That is, the semiconductor memory device of the present invention has a voltage higher than the word line tube state selected by the row decoder among the word lines, the power supply voltage applied to the memory cells, and the power supply voltage applied to the peripheral circuit other than the memory cells. It was designed to be driven by Therefore, after the rising speed of the word line becomes faster and the word line potential is boosted to a high voltage, the transfer transistor of the memory cell is reduced in on-resistance due to the high r-to voltage, so that the transfer transistor and the selection Since the effective driving capacity of the bit line by the driving transistor in the memory cell increases, the cell M selection time TV% senseable voltage difference''
-“°”t-1-rh*+ <& b, “pa”-・
(- is shortened.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. FIG. 7 shows the relationship between the memory cell selection time τW in FIG. 1 and the word line 100 boosted potential V, so that by increasing this potential V
The slew rate when boosting increases, the output of the word line drive circuit (FIGS. 10, 12, and 13) increases, and the word line terminal voltage vl increases to the word line #!
The time TW required to reach the voltage v1 which sufficiently opens the transfer date of the memory cell located at I-1 becomes gradually smaller.

On the other hand, in the nine memory cells shown in FIG. 2, if the word line termination is high, the on-resistance of the transfer transistor 〒4 becomes small, and its drawn current [( becomes large, and ΔV from t in FIG. 6 occurs. The senseable voltage difference generation time Tc at the terminal becomes smaller. Figure 8 shows the relationship between the word line voltage VW and the time Tc. As V increases, the time Tc decreases monotonically. Here, Ding,
. is the transistor T for driving the memory cell when the on-resistance of the transfer transistor T4 is zero.

This is the time it takes for the voltage difference ΔV to occur after the solder pressure VIL is lowered by the voltage difference ΔV.

In the above explanation, the voltage characteristics of Tw and Tc have been described independently, but in reality, the senseable voltage ΔV between a pair of bit lines increases due to the word line potential being boosted and the voltage information in the memory cell. What happens is done as a series of actions. FIG. 9 shows this series of operations until a senseable voltage difference ΔV occurs between the pair of bit lines of the memory cell located at the end of the word line after the start of the word line section # and the word line boosted voltage, V. It shows the relationship with Time Ding 1.
As V increases, TI decreases to single a4 and asymptotically Tc
,become.

Since FIG. 1O shows a part of the static memory according to one embodiment of the present invention, the word line drive circuit 20 has been changed compared to that described with reference to FIGS. 1 to 3. ,
A booster circuit 11ybl is added. That is, in the booster circuit 21, P1 to P are enhancement mop channel MO8 transistors, NN11N is an enhancement type N-channel M (M1 to 57') star, and C is a booster converter. The transistor P1 has a source connected to the vDDt source, and a drain connected to the drain of the transistor N1 and one end of the capacitor C.The transistor N1 has a source connected to the VDDt source.
sa [connected to k (grounded), r-) is connected to transistor N
, and P, f−). The source of this transistor Nl is grounded, and its drain is connected to the drain of the transistor P and the r-to of the transistor PI. The source of this transistor Pl is VD
D [The source is connected to the source of the transistor P and the other end of the capacitor C, and the drain is connected to the source of the transistor P and the other end of the capacitor C, and the point A is the external pressure output terminal. A boost control human voltage VC is applied to the transistors pi and r-to of N1. On the other hand, word, 1N dynamic circuit 2
0, P4 to P are enhancement MP channel MO8) Lanzosters, Nl to N are enhancement L-type N-channel MOS transistors, transistors P4 and N3 form a CMO8 inverter, and the boost output terminal A control transistor p and N4 are connected in series between A and the ground terminal, and word line drive transistors P6 and N are connected in series. Above information! The output terminal of is transistor N4
The connection point of transistors P and N4 is connected to r-) of the driving transformer fiP,
The connection point of transistors P@ and N, ie, the word line drive output terminal, is connected to the r-) of transistor P. A row selection signal Vln is applied from the row decoder to the input terminal of the inverter (2) and the r-to of the drive transistor N.

Figures 11 (,) to (c) show the word line drive circuit 200 Å voltage Vim and boost control human input voltage in Figure 10.
3 shows the temporal relationship between c and the word edge termination voltage VB. That is, in the booster circuit 2, the control input vc is initially at the vDD potential, and the transistors PK and P
, are off, transistors N, , P, and N are on, and the voltage vI at one end of the capacitor C is at the Vll potential, and the voltage 2 at the other end is at the VDD 111 level. Next, when the control force Vc reaches VagTh, the transistor N
1 and N! is off, transistors PA and PI are turned on, and the voltage vI at one end of the capacitor C is boosted by the transistor P to VDD111, and the heavy voltage V at the other end is transferred to the r-top of the transistor P3 through the transistor /P=. is applied to

In this case, even if the voltage V at one end of the capacitor C is VDII, the potential difference between both ends of the capacitor C maintains the potential difference vDD at the trench, so the voltage #i other than the capacitor C is The voltage is increased by 2Vnmt. During this time, the transistor Ps remains off because the Vs'It pressure continues to be applied to the transistor P3t- and r-).
V, it pressure is on one side of transistor Ps'! 1 [V of calculation
It can be raised up to 2VDD which is higher than the DD potential.

On the other hand, in the word line drive circuit 20, the input voltage Vin is initially at the VDD potential, and the transistor P4
is off, transistor Ns and drive transistor N,
When the word line 10 is on, the word line 10 is at V. being dropped to a potential. Also, the Vast position of the word drive output terminal is r-
) is on, and the transistor N4 is off because its r-t is at the Vll potential via the transistor N$, so the voltage at the connection point of these transistors Ps and N4 is v,' is the transistor P in the on state, and the booster output terminal A connected to i/7'
is equal to the voltage V, and therefore the drive transistor P is turned off. Then input frost if word @10 is selected.

ff ■in Ka Ail le control human power Vc ノ Voo
+Vss' becomes V□ potential after the softening of about turns on, and the voltage at the connection point v,′
becomes V□ potential, the drive transistor P- turns on, and the boosted output terminal A
The word line 10 is boosted since the ot voltage V, is applied to the word L'm10, which causes the transistor P, 0r-1
Since the voltage also rises, the transistor pi turns off, and the voltage increases from the boost output terminal A to ■. The DC light path to the power supply is gone and V,
The voltage is used as an external voltage for the word line 10. word line 10
As the voltage of Vm increases, the charge stored in the external voltage capacitor C up to that point is used to charge the capacitor C of the word line 10, so that the Vm voltage decreases below 2VDD. Therefore, in order for the word line terminal voltage vl to be equal to or higher than the vI level, the valley 1 value of the boosting capacitor C must be set 4) larger than the capacitance Il value of the capacitance kCw of word @10.

In the static memory of the above embodiment, in the example, V
By boosting the word line 10 with a higher voltage (in this example, 2VDD) than the transfer transistor (DD potential), the rising speed of the word line voltage is increased, and the word line voltage is boosted to a higher voltage and the transfer transistor (the Figure 2TIIT4)
The on-resistance of the transfer transistor and selected memory cell decreases due to its high r-t
The effective driving capability of the bit line by the dynamic transistor can be increased.

Therefore, the cell selection time TW and the generation time Tc of the senseable voltage difference ΔV, as described above with reference to FIGS. 5 and 6, can be shortened, and the memory access time can be shortened.

The present invention is not limited to the above-mentioned embodiments, but as shown in FIG. N channel MO8) Ranjismetiformes, T! 2
, @value voltage is lower than -G, 5V! DI + Dl
, enhancement [N-channel MO8) transistors E+ to E· with threshold voltages higher than α5v may be connected as shown in the figure. Note that C1 is a boost capacitor, C
3 and Cs! - Tostra, 7# condenser line, 10 is the word line.

The operation of the external pressure circuit 31 is performed in accordance with the operation of the external pressure circuit 21 shown in FIG. 10 described above with reference to FIG. 11>)(@). That is, initially, the control human power Vc is vDD'
IIL rank and transistor! 1 and the drive transistor DI+Km are on, and the voltage at one end of the boost capacitor cl is Vl#iV,.

The potential, the other end voltage V, is at about VDD Iff. Next 1
Control human power■c?”When you reach the II military rank, transistor E1
and drive transistors D1, E, are turned off and y
- voltage VDD-V through transistors D1 and E.
tm' (The transistor TK1 to which the voltage of the transistor E is applied turns on, and the capacitor c
The voltage layer 7 at one end of 1 is boosted, and accordingly, the voltage r-) of the transistor TIT is boosted via the capacitor c1, so-called! -Tostra,! Depending on the operation, the voltage Vm F
i quickly becomes vDD potential, and the voltage at the other end of capacitor C is V
.

is increased by 4 voltages up to 2vDD.

Further, the operation of the word line drive circuit 3o in FIG.
This is carried out in accordance with the word line drive circuit 2o of FIG. 10 described above with reference to FIGS. 1(a) and 1(c).

That is, in the r period, the input voltage vthn is at the vDD potential, the transistor E4 and the driving transistor E are in the on state, and the word line 1o is at the vDD potential.

Seconds after being dropped to the potential, 1 [current is flowing from the vDD electrodes to transistors E1 and E4, and the capacitor C
mt! Not charged. Next, when the word line 10 is selected, the input voltage Via becomes Vs+V, and therefore the transistor E4 and the active transistor E are turned off, and the voltage V o 'R decreases through the transistor Σ3. (r-)K: The applied transistor TI2 turns on and the boosted output voltage V across this transistor Tx2t-.

increases the voltage of word #J10.As the voltage increases, the bootstrap driver,! The transistor TtzO0') is boosted by the capacitor C, and the so-called /-tostra,! As a result of the operation, the word line 10 rapidly rises to the boosted output terminal voltage V.

The pressure is boosted to

Note that in the word line drive circuit 30, the transistor T
When the threshold voltage of I2 is negative, the output terminal voltage of the booster circuit 3 is V, and when the voltage is boosted to 0, it is V1m through the transistor Tf2.
Since a current flows to ', a word line drive circuit 40 connected as shown in FIG. 13, for example, may be used to reduce this current. That is, E-~E is en1
1stment type N-channel MO8) transistor)
, C5 is a bootstrap drive,! The drain of the transistor is connected to the VDDt source,
The source is connected to the drive transistor E, r-) and the drain of the transistor ET, and the source is connected to the drive transistor E, r-) and the drain of the transistor ET.
is connected to the source of said drive transistor E. and the drain of said drive transistor E. via said drive transistor E. and said transistor E! , each source is grounded, and an input voltage 1 is applied to each r-to. Therefore, when vl is at VDD potential, transistors E and E are on, so transistor E is off, and when Via goes to Vll, transistors Eγ and E# are off, driving transistor E Since r-to is boosted by the transistor E-, this transistor E is turned on 9, and further, the boosted vehicle voltage V increases the voltage of the word line 10 through this transistor E-. Along with this voltage increase, Note Strap! Transistor Is by capacitor C
The r-t tolerance pressure also increases, and the so-called! The word line 10 is rapidly boosted to the boosted output voltage V by the -straight operation.

Note that in FIGS. 10, 12, and 13, the state-type memory cell connected to the word line 10 is connected to the second
It is not limited to the case where the drive transistor and the resistive load are directly connected as shown in the figure.
However, a so-called Ey'D11 memory cell using a scene type transistor may be used, or a CM using a transistor with the opposite *tm of the driving transistor instead of a resistive load.
It may be an O1ii memory cell, and the circuit type of the cell is not limited. Furthermore, in the above operation description, the booster circuit operates first to boost its output voltage V, and then the word line drive circuit operates to increase the word line to the power supply voltage VflD.
The case of boosting the voltage has been described above, but the circuits in Figures 1O and 12 are not limited to this order of operation, and even if the external pressure circuit and the word line drive circuit operate almost simultaneously, The word line drive circuit may operate before the external pressure circuit.

〔Effect of the invention〕

As described above, according to the semiconductor memory device of the present invention, when selecting a word line, the word line is boosted by a voltage higher than the single voltage for the memory cell and the power supply voltage for peripheral circuits other than the memory cell. Compared to conventional memory, which aims to increase speed by lowering the electric resistance of the word line, it shortens the actuating time without complicating the manufacturing process, increasing the cost of lost products, and reducing yield. is possible. For example, the circuit in Fig. 10 is converted into a 16-bit CM.
When applied to OS status and Rm, the activation time was shortened to 70 ms (110 m5 for the conventional circuit). In addition, the circuit of Fig. 12 can be changed to 16-bit I/
1) When applied to type static RAM, the time is 40ns.
(60m5 for the conventional circuit).

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing a part of static memory.
Figure 2 is a circuit diagram of an example of the memory cell in Figure 1;
The figure is a circuit diagram showing a conventional example of the word IIM drive circuit in FIG. A voltage waveform diagram shown to explain the cell selection time TV, Fig. 6 is w, a voltage waveform diagram shown to explain the senseable voltage ratio difference R1 generation time 'rc in Fig. 2, and Fig. 7 is Fig. 5. FIG. 8 is a characteristic diagram showing the relationship between the time 'rc of FIG. 6 and the word line voltage vw,
FIG. 9 is a characteristic diagram showing the relationship between the total time T1 of time 〒W in FIG. 7 and time 'rc in FIG. 8 and the word line boosted voltage . FIGS. 11(a) to 11(a) are voltage waveform diagrams shown to explain the operation of FIG. 10, and FIGS. 12 and 13 are circuit diagrams showing a part of the state memory, FIG. 2 is a circuit diagram showing a part of an embodiment of the present invention. 10...word line, 11...state, memory cell, 13.14...pit line,! 6, 30. 40... Word line drive circuit, 21.11... Boost circuit, TmpT4... Transfer transistor, TI2...
・Intrinsic, type transistor, E wealth ~ Σ.・・・Enhancement type transistor, C#C1...
・Boost capacitor, vDD...'l#. SS 1 (a) - Figure 6 - Figure 755 8 @ ta 9 欝V'r
vo(7-卜”ay)i mino E)th +o@

Claims (1)

[Scope of claims]
A pair of bit lines commonly connected to each end of a pair of transfer MO8 transistors in the same row, and each r of the transfer MOB transistors in each of the memory cells in the same row.
-) and the word #P edge selected by the row decoder among these word lines are connected to the power supply voltage applied to the memory cell and the power supply voltage applied to peripheral circuits other than the memory cell. 1. A semiconductor memory device comprising a word line drive circuit driven by a voltage. (2) The word line drive circuit is configured such that a boosted voltage higher than the power supply voltage is applied to each -1)IIIK applied threshold voltage is -0, IV to +o, the first in the svo range.
MOS) boosts the word line through a transistor, and boosts the word/11 by a second MOG transistor connected between the other end of the first transistor and the ground terminal and whose threshold voltage is greater than +0.5V. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is configured to step down the voltage. (3) The external voltage capacitor is used to boost the voltage at one end of the boost capacitor r/s, and the voltage at one end of this booster capacitor is supplied to the word line via the drive transistor of the word line drive circuit! l! Claims 1 to 9 are the semiconductor memory device according to claim 2. (4) Claim 1, characterized in that the voltage M111 of the boost capacitor is larger than the capacity of the word line.
The semiconductor storage device described in 1.