JP3112019B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, in particular, a high-speed, highly-integrated semiconductor device which is composed of fine elements and operates at a low voltage suitable for a semiconductor integrated circuit which can operate on a battery. .

[Conventional technology]

2. Description of the Related Art The integration degree of a semiconductor integrated circuit (LSI = Large Scale Integration) has been improved by miniaturization of a MOS transistor as a constituent element thereof. When the element size becomes a so-called deep submicron LSI of 0.5 micron or less,
As the withstand voltage of the element decreases, an increase in power consumed by the LSI becomes a problem. To solve such a problem, it is considered that reducing the operating power supply voltage as the element is miniaturized is an effective means. As the current LSI power supply voltage is 5 V, the technology of mounting a voltage conversion circuit that steps down the external power supply voltage on an LSI chip has been developed as a means to configure the LSI with fine elements.・ E-Journal of Solid State Circuits, Vol. 21, No. 5, pp. 605-611 (1986) (IEEE J
ounal of Solid-State Circuits, vol. 21, No. 5, pp. 605
-611, October 1986). In this case, the value of the external power supply voltage and the value of the internal power supply
3.5V. Thus, the most highly integrated dynamic RAM (DRAM = Dynamic Random Access Memory)
In y), the problem of power consumption is becoming apparent. In response to this trend, there is a movement to reduce the external voltage of the LSI itself. For example, in a 64-Mbit DRAM using a 0.3 micron processing technology, the external power supply voltage will be reduced to about 3.3V. As the degree of integration increases, the external power supply voltage may further decrease.

In recent years, with the spread of portable electronic devices, low-voltage, low-power LSs that can operate on batteries and retain information in batteries
The demand for I is increasing. For such an application, an LSI operating at a minimum of 1 to 1.5 V is required. In particular, in the case of a dynamic memory, the degree of integration has already reached the megabit level, and there has been a movement to use the semiconductor memory also in the field of large-capacity storage devices, which could only use magnetic disk devices in the past. .
For that purpose, it is necessary to back up with a battery so that data is not lost even if the power is turned off. This backup period usually needs to be guaranteed for weeks to years. For this reason, it is necessary to reduce the current consumption of the memory as much as possible. To reduce the power, it is effective to reduce the operating voltage. However, if the operating voltage is set to around 1.5 V, only one dry battery is required as a backup power source, so that the cost is low and the occupied space is small.

In CMOS (Complementary MOS) LSIs consisting only of inverters and various digital logic circuits, such as processors, even if the power supply voltage is reduced to about 1.5 V,
With proper selection of the MOS transistor constant and threshold voltage, it is possible to operate at a low power supply voltage of about 1.5 V without causing a significant performance drop. However,
In addition to the external power supply voltage (VCC or VSS), an intermediate voltage between them or a voltage exceeding those ranges is generated on the LSI, and in an LSI that uses it, the drop in the power supply voltage causes a decisive decrease in performance Had been brought. The representative of such LSI is DRA
M. Therefore, when configuring an information device that operates at a low voltage with a plurality of types of LSIs such as a processor and a memory, a voltage other than the power supply voltage is generated on the LSI and used for the operation as represented by a DRAM. Low voltage operation of LSI is essential.

When the DRAM is operated at a low voltage, problems occur mainly in the following three types which have been conventionally used.

(1) A circuit for reading a small signal read from a memory cell.

(2) A circuit for generating a high voltage for driving a word line necessary for transmitting a signal without loss by setting a MOS transistor constituting a memory cell to a sufficiently high conductive state.

(3) A circuit for generating an intermediate voltage (VCC / 2) serving as a reference voltage for detecting a plate electrode of a memory cell storage capacitor and a read signal from a memory cell.

 These conventional examples will be described below in order.

(1) is as follows. As the integration and scale of LSIs increase, the problem that the operating speed decreases due to an increase in the parasitic capacitance of signal wiring is becoming apparent. In the case of dynamic memory, the speed at which a small signal read from each memory cell onto a data line is amplified by a sense amplifier, and an input / output control line (common I / O line) for reading information from a selected data line. The operation speed of the line occupies a large proportion of the operation speed of the entire memory, and a technology for increasing the operation speed is indispensable for improving the performance of the memory. Conventional input / output control circuits include, for example, IEE, Journal of Solid State Circuits, SC22 (1987)
Years 663 to 667 (IEEE, Journal of Solid-Sta)
te Circuits, Vol.SC-22, No.5, October, 1987, pp663-66
As mentioned in 7), two MISs (Metal
Insulator Semiconductor (FET) Field Effect Tra
In general, a selection signal is applied to those gate electrodes to control the connection between the data line pair and the common I / O line pair.

FIG. 9 shows a conventional example of (2). This is DRAM
1 shows circuits related to a memory cell array (MA) and a word driver (WD). FIG. 10 shows the waveform of each part. This circuit is, for example, IEEE JOURNAL OF
SOLID-STATE CIRCUITS, VOL.sc-21, NO.3, JUNE 198
6, pp. 381-387.

The conventional example of (3) is as follows. The DRAM method that precharges the data line to VCC / 2 voltage has the features of high speed, low power consumption, and noise immunity.
DRAM is the mainstream of 1 megabit and later along with circuits. Examples of conventional intermediate voltage generating circuits for generating this VCC / 2 voltage are described in IEEJ Journal of Solid State Circuits, Vol. 21, No. 5,
643-648 (1986) (IEEE Jounal of Solid-Stat)
e Circuits, vol.21, No.5, pp.643-648, October 1986)
[Problem to be Solved by the Invention] The following describes the problem to be solved by the present invention with respect to the conventional example described above.

First, the conventional example (1) is as follows.
FIGS. 2A and 2C show examples of the conventional system. This method is effective in reducing the area of the entire memory because it can be constituted by a minimum number of transistors, but has the following disadvantages.

(A) If the MIS-FETs (T50, T51) for I / O control are made conductive before the signal voltage of the data line (D0, ▲ ▼) is sufficiently amplified, the operation of the sense amplifier SA0 is hindered. Causes malfunction.

(B) For the above-mentioned reason, it is necessary to provide a time delay (timing margin) from when the sense amplifier operates to when the selection signal Y01 is input and the MIS-FET is turned on,
The operating speed is reduced (FIG. 2 (c)).

(C) In order to prevent such an erroneous operation, a design constraint is imposed on the ratio between the channel conductance of the MIS-FET (conductivity between the drain and the source) and the channel conductance of the MIS-FET constituting the sense amplifier. I do. In general, the former must be smaller than the latter,
It is difficult to increase the driving capability of the I / O line (IO0, ▲ ▼). Therefore, in addition to (b), the operation speed further decreases.

(D) As the degree of integration of memories increases, the internal power supply voltage tends to decrease in order to cope with a reduction in power consumption and a decrease in withstand voltage of elements. Accordingly, the driving capability of the MIS-FET is further reduced, and the operation speed is further reduced.

(E) One common, mainly for the reason (c) above
It is difficult to write or read in parallel between an I / O line and a plurality of data lines connected to the I / O line, and there are restrictions on test functions such as the degree of parallelism.

For these reasons, the conventional input / output circuit system cannot provide a circuit system suitable for a highly integrated memory that operates at high speed even at a low voltage.

Next, the conventional example of (2) is as follows. As shown in FIG. 9, the word driver is a transistor
It consists of QD and QT. Here, the X decoder output N1 is High
When the level (VL) is reached, the gate N2 of the QD is charged through the QT, and the QD is turned on. At this time, the voltage of N2 becomes VL-VT. Next, the word line drive signal φX generated by the peripheral circuit FX
When (amplitude is VL + VT or more) becomes high level, a current flows from the drain to the source of QD, and the word line W is made high level. At this time, the potential difference between the gate of QT and N1 is 0,
Since it is Vt, QT is cut off. Therefore, when φX rises, the voltage of N2 rises with φX due to the coupling between the gate and source capacitances of QD. Here, when the gate-source voltage of QD is equal to or higher than VT when φX reaches the maximum value, the voltage of the word line becomes equal to φX.
On the other hand, if φX becomes lower than VT while rising, the capacitance between the gate and the source of QD becomes 0, and the rise of N2 stops at that point, and VL− VT +
α (VL−2VT) / (1−α). The voltage of the word line is (V _DL −2V _T ) / (1−α). Where α is QD
And the total capacitance of the node N2.

Here, consider a case where VL drops to 1.1 V due to battery consumption. If α = 0.9 and VT = 0.5 (V), the voltage of N2 is 1.5 V from the above equation. Therefore, the word line voltage only rises to 1.0V. Normally, the threshold voltage of the switch transistor QS of the memory cell is higher than that of the peripheral circuit and is 0.5 V or more, so the amount of charge stored in the memory cell is less than half (CS × 0.5) of the maximum value (CS × 1.1). ), Which significantly reduces soft error resistance and S / N of the sense amplifier. That is, the stored data is likely to be destroyed.

As described above, when an attempt is made to operate a DRAM with a battery using the conventional technique, if the electromotive force of the battery drops to almost twice the threshold voltage VT of the MOS transistor, the operation of the memory cell due to a malfunction of the word driver may occur. There is a problem that the write voltage of the data is lowered and data is likely to be destroyed.
There was a problem that needed to be solved.

Regarding (3), by lowering the voltage and increasing the integration,
The conventional intermediate voltage generating circuit has the following two problems. (A) As the power supply voltage decreases, the voltage setting accuracy decreases, and the signal-to-noise (S / N) ratio deteriorates.

(B) Since the element operates with the source follower word, the response speed is determined by the value of the drive capacity and the load capacity of the transistor. Therefore, the load capacity is increased by the high integration, and the voltage is further reduced. As a result, the response speed decreases due to the reduction in the driving capability of the element.

FIG. 19 shows a conventional example of a DRAM intermediate voltage generating circuit. Hereinafter, the above problem will be described with reference to FIG. In FIG. 19, TN5 and TN6 are N-channel MIS type Fs.
ET, TP5 and TP6 are P-channel MIS type FETs, R1 and R2 are resistors, and CL is a load capacitance. The circuit in Fig. 19 is a kind of complementary push-pull circuit, where TN6 and TP6 are the power supply voltage.
A voltage divider that divides VCC (VSS is set to ground potential) to an intermediate voltage of HVC is configured, and TN5 and TP5 for applying a bias voltage to these gates configure a bias circuit.
In the DRAM of the VCC / 2 precharge method, the load capacity is almost equal to the capacity of all data lines, and in the case of the 4 Mbit DRAM, the load capacity is 5 times.
~ 10nF (nano farad), 20 for 16Mbit DRAM
The value is about 80 to 160 nF in the case of up to 40 nF and 64 megabit DRAM. In this circuit, a small current is constantly supplied to each FET, so that the output is stabilized to a constant voltage. If the current is small, the voltage difference between terminal 20 and terminal 22, ie, V (20) −V (22), is almost equal to the threshold voltage VTN of FQT TN5, and the voltage difference between terminal 22 and terminal 21, ie, V (2
2) -V (21) is almost the absolute value V of the threshold voltage of FET TP5.
Equals TP. Further, the gate width to gate length ratio W / L of the FETs TN6 and TP6 is selected to be several times to several tens times the W / L of TN5 and TP5, respectively. Therefore, TN6
Is several times to several tens times the bias current of TN5.

First, the first problem will be described. Now, FET vs T
Assuming that there is no difference in device characteristics (eg, threshold voltage, channel conductance per unit gate width, etc.) between N5 and TN6 and TP5 and TP6, the output HVC is equal to the voltage at terminal 22 A voltage is obtained. Output voltage It is expressed as Here, it is assumed that VSS is at the ground potential. Under the standard conditions, if the values of VTN and VTP are almost equal and R1 = R2, In other words, if the difference between VTN and VTP is negligible compared to VCC, Becomes In general, the variation in the threshold voltage of the element is considered to be constant and not reduced even with high integration, so that the setting accuracy of V (HVC) decreases as VCC is lowered. For example, assuming that VTN and VTP each fluctuate ± 0.1 V from the standard value, the power supply voltage becomes 5 V
(HVC is 2.5V), the fluctuation of the intermediate voltage is about ± 4%
On the other hand, when the power supply voltage is 1.5 V (HVC is 0.75 V), the fluctuation of the intermediate voltage reaches about ± 13%, which hinders the stable operation of the memory.

Next, the second problem will be described. Since the output MISFET operates in the saturation region when charging and discharging the load, its drain-in current ID is It is expressed as Where VGS is the gate-source voltage, VT
Is a gate threshold voltage of the MISFET, and β is a constant determined by the structure and dimensions of the device. Now, in the conventional circuit, the voltage of the load (load capacity = CL) is changed from 0V to 90% of the intermediate voltage VCC / 2.
The time required to start up t _r is It is expressed as It is assumed that the number of memory cells connected to one data line is 256, and the capacitance value per data line is 0.5 pF. Since these values are almost constant as the memory becomes more highly integrated, the value of the load capacity increases by four times for each generation. For example, CL ≒ 8.2 nF for a 4 Mbit DRAM, CL ≒ 33 nF for a 16 Mbit, and CL ≒ 131 nF for a 64 Mbit. On the other hand, when the power supply voltage decreases from 5 V to 3.3 V to 1.5 V for each generation, when the MISFET β is constant at 10 mA / V ² , the rise time _tr
Is about 5.9 μs → 36 μs → 314 μs, which is increased about 10 times for each generation. To keep the response speed constant, MISFET
Although the β it is necessary to ten times for each generation, increase in the layout area, because of the side effect of causing an increase in steady state current, in practice to maintain a constant rise time t _r is not is there.

Solving the conventional problems described above, even at low voltage,
It is an object of the present invention to provide a semiconductor device that operates stably. More specifically, the following three objects are aimed.

(1) To provide a method of an input / output control circuit for an ultra-highly integrated memory, which operates at high speed even at a low voltage, has excellent operation stability, and has a parallel test function.

(2) To provide a circuit capable of generating a sufficiently high word line voltage so that data destruction does not occur even when the electromotive force of the battery decreases.

(3) High accuracy even in LSI with high integration and low power supply voltage,
Provide a voltage supply circuit (voltage follower) that operates at high speed.

[Means for solving the problem]

In order to achieve the above-mentioned object (1), input / output control circuits for reading information from the data lines or writing information to the data lines are alternately arranged on the left and right sides of the memory array, and The circuit configuration is such that the transfer impedance between the I / O line and the data line is changed between when reading and writing information. Also, read lines (RO
Line) is selected as a sense circuit to detect
A current-voltage conversion means using a MISFET complementary to the ET is provided. This means is to operate at high speed even at a low voltage.

In order to achieve the object of (2), the following measures are taken as described in the claims. (A) The output of the data line power supply and the word driver, which apply a voltage 1.5 to 2 times the threshold voltage of the switch transistor of the memory cell array to the data line as the minimum operating voltage applied to the memory cell array and the data line And a voltage conversion circuit for converting the data line power supply voltage to a voltage higher than the data line voltage by the threshold voltage of the switch transistor of the memory cell array, and using the output of the voltage conversion circuit as a power supply. A word line drive is provided with an operating static word driver.

(B) The voltage conversion circuit according to the first aspect includes a charge pump circuit and a rectifier circuit.

(C) The charge pump circuit according to the second aspect includes first, second, third, and fourth MOS transistors and first and second capacitors, and the second, third, and fourth capacitors are provided. MO
The drain of the S transistor serves as a power supply, the gate of the second MOS transistor serves as the source of the fourth MOS transistor, the source of the third MOS transistor serves as the source of the second MOS transistor, and the third and fourth MOS transistors. Is connected to the power supply, and one terminal of the first capacitor is connected to the fourth terminal.
Of the second capacitor is connected to the source of the MOS transistor
One terminal is connected to the source of the second MOS transistor, and the other terminal of the first and second capacitors is connected to the other end of the charge pump circuit. The source of the MOS transistor is connected to the power supply, the source is connected to the source of the fourth MOS transistor, and the gate is connected to the source of the second MOS transistor.

This means is to further speed up the rise of the charge pump circuit even at a low power supply voltage, and to further increase the output voltage.

(D) The rectifier circuit according to the above item (2), wherein the rectifying element is constituted by a MOS transistor, the drain of which is an input and the source is an output, and the input is the charge pump circuit according to the item (3). The source is connected to a circuit for transmitting electric charge from the output, a capacitor for storing the electric charge, and a circuit for transmitting the electric charge to a power supply. When the voltage of the input is at a high level, one end of the capacitor is set to a high level. The gate voltage of the MOS transistor is determined by the input voltage and the MOS.
When the input voltage is low, the voltage at one end of the capacitor is set to a low level, and at the same time, the gate voltage of the MOS transistor is set to the power supply voltage.

This means is to obtain a high output voltage by reducing the voltage drop of the rectifying transistor.

(E) In the above-mentioned means (1) or (2), the MOS used for the memory cell array, the word driver, and the voltage conversion circuit may be used.
The threshold value of the transistor is set to three types, the memory cell array is the highest, the word driver is the middle,
The voltage conversion circuit was determined to be the lowest.

The present means achieves further stabilization, higher speed, and lower power consumption as an integrated circuit even at a low power supply voltage.

Further, in order to achieve the object of (3), in the semiconductor device of the present invention, an input of a reference voltage equal to the intermediate voltage;
A first complementary push-pull circuit comprising at least two first and second complementary push-pull circuits for connecting outputs in parallel to the same load, and a push-pull current amplifier circuit for amplifying and outputting a reference current The circuit includes an input of the reference voltage and a bias voltage source added to the input to the bias circuit. The bias circuit applies a bias voltage to the gate of the voltage dividing transistor of the push-pull circuit. The voltage circuit forms a reference current circuit of the current amplification circuit, and an output terminal of the current amplification circuit is connected to a bias circuit of the second complementary push-pull circuit.

That is, a generator of the reference voltage equal to the intermediate voltage is provided separately and independently from the bias circuit of the complementary push-pull circuit, and the load is driven in parallel by at least two complementary push-pull circuits, so that the output voltage and The difference between the input voltages is detected as a current flowing through one push-pull circuit, and the other push-pull circuit is driven by an amplified current substantially proportional to the current.

Here, it is preferable that the bias voltage of the first and second complementary push-pull circuits is substantially equal to the gate threshold voltage of the transistor of the push-pull circuit to which the voltage is applied. This suppresses the current flowing through these transistors to a low value in a steady state.

Alternatively, if the current amplifying circuit is a current mirror type push-pull amplifying circuit, a high driving capability with a simple circuit configuration and little variation can be easily obtained.

Alternatively, it is preferable to configure the first and second complementary push-pull circuits with field effect transistors because they can be operated at a low power supply voltage.

According to the semiconductor device of the present invention for achieving the object (3) more effectively, an input of a reference voltage equal to the intermediate voltage and at least two first and second outputs connected in parallel to the same load. Complementary push-pull circuit and tri-state drive circuit, and a push-pull current amplifier circuit for amplifying and outputting a reference current, the first complementary push-pull circuit, the bias circuit, the input of the reference voltage And a bias voltage source added to the input, and the voltage dividing circuit of the push-pull circuit forms a reference current circuit of the current amplifying circuit.
And an output terminal of the current amplifier circuit is connected to a bias circuit of the second complementary push-pull circuit. The tri-state drive circuit further includes a first determination voltage lower than the input voltage and the input of the input. A second judgment voltage higher than the first judgment voltage, and means for charging the output when the output voltage is lower than the first judgment voltage, and discharging the output when the output voltage is higher than the second judgment voltage. It is characterized by.

That is, in the present invention, the tri-state drive circuit is connected in parallel to the load together with the complementary push-pull circuit to supplement the driving capability of the push-pull circuit.

Here, the bias voltage of the first and second complementary push-pull circuits is set to a voltage substantially equal to the gate threshold voltage of the transistor of the push-pull circuit to which the voltage is applied, or the current amplifier circuit Is a current mirror type push-pull amplifier circuit, or the first and second complementary
As described above, it is preferable that the push-pull circuit is formed of a field effect transistor.

Here, it is preferable for application to a circuit such as a DRAM to set the input and output voltages to one half of the power supply voltage.

Furthermore, an integrated circuit (LS) including at least a plurality of blocks of the same type, and activating one or a plurality of blocks selected by a block selection signal during operation.
I) and, in the case of a semiconductor device having means for supplying a voltage and driving the block as a load, in order to achieve a high-speed response, the driving means for driving the block includes:
First and second drive circuits, and switching means provided for each block to connect an operating block to the first drive circuit and an emergency operation block to the second drive circuit, respectively. It shall be.

Such a means is suitable for an integrated circuit such as a large-capacity dynamic memory.

In such a case, the block includes at least a memory cell array, and the load includes a counter electrode of a memory cell storage capacitor and a precharge voltage supply line of a data line transmitting a signal from the memory cell to a signal detection circuit. Should be included at least.

Here, it is preferable for the application to the DRAM that the driving circuit generate half the power supply voltage.

Further, if the semiconductor device of the present invention is used as the driving circuit, high accuracy and high speed can be achieved even for a large-capacity LSI.

[Action]

Regarding (1), with the above configuration, the input / output control circuit can be laid out with twice the pitch of the data line pitch, so that the optimum input / output circuit configuration can be achieved without greatly increasing the chip area as compared with the prior art. Can be taken. This greatly improves the operating margin of the input / output circuit,
Even at a low voltage, stable and high-speed operation can be achieved. Further, since the operation is stable even when writing and reading are performed in parallel, a parallel test with a high degree of parallelism can be performed.

Regarding (2), in the static word driver, a P-channel transistor is connected to the power supply side, and an N-channel transistor is connected to the ground side. For this reason,
If the gate is set to the ground level (0 V) when driving the word line, if the power supply voltage is equal to or higher than the threshold voltage VT, the P-channel transistor is always on, and its output voltage rises to the power supply voltage. As described above, the static word driver operates with the gate voltage of the drive transistor at a low level, and thus operates stably even with a low power supply voltage.

Therefore, by using the output of the voltage conversion circuit as the power supply of the word driver, it becomes possible to apply a voltage higher than the data line voltage by the threshold voltage of the switch transistor of the memory cell array by at least the threshold voltage of the memory cell array. This makes it possible to stabilize the memory operation even when the power supply voltage drops to about 1V.

Furthermore, the charge pump circuit of the present invention feeds back its output voltage to the precharge transistor. By using this in a voltage conversion circuit, it is possible to obtain a fast rise and a high output voltage even with a low power supply voltage. become.

The rectifier circuit according to the fourth aspect of the present invention synchronizes the gate voltage of the rectifying transistor with the output voltage of the charge pump circuit. The voltage is increased by the value voltage or more, and when the signal is at the low level, the voltage is set to the same level. This makes it possible to reduce the voltage drop of the rectifying transistor and to prevent the backflow of electric charge.

When the threshold voltage of a transistor is reduced, the driving capability of the transistor generally increases. Therefore, it is effective to use such a transistor in a voltage conversion circuit that is not so large, as described in item 5 of the above means. However, as will be described later, in the case where a large number of transistors are used, such as a word driver, the leakage current flowing when the transistor is in the off state cannot be ignored. Therefore, a standard threshold voltage is used. Further, when the threshold voltage of the transistor of the memory cell array is reduced, the refresh interval is shortened as described later, which leads to an increase in power consumption. Therefore, it is preferable to use a transistor higher than the standard.

That is, the fifth term of the above-described means operates to further stabilize the integrated circuit even at a low power supply voltage, to increase the speed, and to reduce the power consumption.

Regarding (3), by dividing the generation section of the reference voltage equal to the intermediate voltage from the bias circuit of the complementary push-pull circuit, the voltage can be set independently of the bias circuit, and the output of the intermediate voltage can be increased. It is possible to improve accuracy.

Also, by converting the voltage difference between the input and the output to a current through the transistor of the first complementary push-pull circuit, and driving the second complementary push-pull circuit with an amplified current proportional to the current, As long as there is a voltage difference between the input and output, the driving capability of the push-pull circuit is increased to charge and discharge the load capacitance at high speed. In addition, the charging and discharging driving capacities at that time can be made uniform, so that it is possible to provide a voltage supply circuit (voltage follower) that operates stably at high speed even at a low voltage.

Further, as described above, if the bias voltage of the complementary push-pull circuit is substantially equal to the threshold voltage of the voltage application transistor and the current of the push-pull circuit is suppressed to a low value, the steady-state power of the semiconductor device is thereby reduced. While it is small, it is possible to obtain a high driving capability when the output voltage fluctuates.

Also, if a current mirror type amplifier circuit is used for the current amplifier circuit, current amplification can be performed with a simple circuit configuration, and the same type of element is used for the mirror circuit transistors that require the same characteristics. Driving capability can be easily obtained with little variation.

Since the field effect transistor can lower the gate threshold voltage by controlling the impurity concentration,
By configuring the first and second complementary push-pull circuits with field effect transistors, required operations can be easily obtained even when the power supply voltage is reduced.

In addition, a tri-state drive circuit is
According to the above-described means connected in parallel to the load together with the push-pull circuit, when the voltage error between the input and the output becomes larger than the above-described determination voltage, the voltage error is reduced by charging or discharging the load capacitance. The operation is performed so as to converge within the determination voltage, thereby acting to supplement the operation of the push-pull circuit and further increase the response speed in the transient state.

According to the means of the present invention, in which a plurality of blocks of the same type are included in an integrated circuit, and when a part of the blocks is operated, only a block in an operating state is switched to be selected as a load, such as a large-capacity DRAM, In this case as well, a part of the load is substantially carried, so that a high-speed response is possible without flowing a large transient current. Furthermore, if the device of the present invention is used in this drive circuit, it is possible to more effectively obtain high-accuracy high-speed response as described above.

〔Example〕

Hereinafter, the present invention will be described specifically with reference to examples. In addition,
In the following description, the present invention relates to a dynamic memory (DRAM).
In the following, an example in which the present invention is applied will be described. However, the present invention can be similarly applied to, for example, a static memory (SRAM) and a read-only memory (ROM). In addition to the memory using the MIS type FET element, a memory using a bipolar element, a so-called BiCMOS type memory combining a bipolar element and an MIS-FET, and further, a semiconductor material other than silicon is used. The same can be applied to a memory.

FIG. 1 shows an embodiment of the memory circuit of the present invention. First
In the figure, MA is a memory cell array in which a plurality of memory cells each composed of one MIS-FET and one storage capacitor are two-dimensionally arranged, and CKT0 and CKT1 detect a memory cell signal or read through a read line or a write line. , An input / output control circuit for exchanging information with the outside of the memory, D0 and ▲ ▼, D1 and ▲
▼ is a data line pair for transmitting a signal between the memory cell and the input / output control circuit, and WD is for specifying a row address of the memory cell array and supplying a drive signal to one word line. Word line drive circuit, W0 to Wm are word lines, YD
Represents a Y (column) decoder for designating a column address in the memory cell array, and Y01 represents a column selection signal line. In the input / output control circuit, SA0 and SA1 are detection circuits (sense amplifiers) for detecting minute signal voltages on data lines, CSN0 and CSP0, and CSN1 and CSP1 are driving detection circuits SA0 and SA1, respectively. A signal line, CD0 or CD1 is a drive signal generation circuit of a detection circuit, and PR0 and PR1 are precharge circuits for short-circuiting a data line pair and setting a voltage convenient for operation of a sense amplifier in a non-operation state, RG0. Alternatively, RG1 is a read gate for reading a signal (voltage difference) appearing on the data line pair to the outside of the memory array, and T1 to T4 are N-channel MISs constituting the read gate.
FET, WG0 or WG1 are write gates for driving data lines according to external information, and T5 to T8 are N-channel MIS-FETs, RO0, ▲ ▼, RO constituting one write gate.
1, ▲ ▼ is the reading line, WI0, ▲ ▼, WI1, ▲
▼ is a write line, RCS0, ▲ ▼, RCS1, ▲
▼ is a read control line, WR0, ▲ ▼, WR1, ▲
▼ indicates a write control line. Also, SW
R0 and SWR1 are common read lines CRO, ▲
A switch circuit for connecting to ▼, SWW0 and SWW1 are switch circuits for connecting a write line and a common write line CWI, ▲ ▼, and SEL0 and SEL1 are signals for selecting one of right and left switches. AMP is a sense amplifier for detecting and amplifying the signal appearing on the CRO, DOB is an output buffer, and DIB is an input buffer. In this embodiment, the input / output control circuits CKT0 and CKT1 are alternately arranged on the left and right sides of the memory cell array for each data line pair, and
I / O lines are separated into read lines (RO lines) and write lines (WI lines). Hereinafter, specific configurations and effects thereof will be described.

FIG. 1B shows a plan layout diagram of the read gate and the write gate circuit. In general, as the degree of integration of the memory increases, it becomes more difficult to lay out the input / output control circuit Ci with the data line pitch. However, by arranging the input / output control circuits alternately on the left and right sides of the memory cell array as in the present embodiment, the layout pitch of the input / output control circuit is twice the data line pair pitch, that is, 2dy.
Therefore, the layout can be performed without greatly increasing the chip area. In a highly integrated memory, for example, IEE, Journal of Solid State Circuits, 23 (1988), pp. 1113 to 1119 (IEEE, Journal of Solid-State Circuits,
vol.23, No.5, October 1988, pp.1131-1119), there is a problem that the signal-to-noise ratio is significantly reduced due to capacitive coupling between adjacent data lines. It is known that the capacitance coupling noise of the memory cell array can be reduced by crossing the data lines in the middle of the memory cell array, but in the input / output control circuit, the coupling capacitance between adjacent data lines may vary. Due to the non-uniformity, noise cannot be sufficiently reduced. In this embodiment, by arranging a shield wiring between the data line pairs of the input / output control circuit, the line-to-line capacitive coupling noise can be significantly reduced as compared with the conventional case. Hereinafter, this will be described.
In the layout of the input / output control circuit section as shown in FIG. 1B, another signal wiring formed simultaneously with the data line is arranged between the data line pair. Here, for example, for example, the read lines RO and ▲ ▼ and the read control lines RCS and ▲
▼ is connected to a wiring material formed at the same time as the data line through the through hole, and is arranged in parallel with the data line. By doing so, the parasitic capacitance between the data line and the adjacent data line can be reduced, the noise accompanying the read operation can be minimized, and a stable operation can be expected.

Next, specific configurations of the read switch SWR0, the write switch SWW0, and the sense amplifier circuit AMO will be described.

FIG. 1C shows a configuration example of the read switch SWRi (i = 0, 1). This circuit includes a plurality of read lines ROi, ▲
One of ▼ is selectively connected to the common read line CRO, ▲ ▼, and the voltage of the read control line RCSi, ▲ ▼ of the selected memory block is controlled to take out a signal to the read line. ing. In the figure,
T10 to T17 are N-channel MISFET, INV100 is inverter, NA
ND1 indicates a two-input NAND circuit that outputs a low level only when both inputs are a combination of a high level. When a memory block is selected and the selection signal SELi is at a high level, and the memory is in a read state and the write signal WE is at a high level, the MISFETs T10 to T13 are turned on and T14 to T17
Becomes non-conductive. Therefore, the read lines ROi, ▲
▼ are connected to the common read lines CRO and ▲ ▼, respectively, and the read control lines RCSi and RCSi are grounded. Thereby, for example, the column selection signal Y01 in FIG.
Is high, T3 and T4 conduct and the data line pair
Read line RO0, ▲ ▼ 0 according to the voltage difference between D0, ▲ ▼
, A signal is obtained as the difference between the currents flowing through the read control lines RCS0 and ▲ ▼. Here, the read control line RCS0, ▲
In the case of ▼, it is not always necessary to separate them when only the reading operation is considered. However, when performing a parallel test as described later, the separation is indispensable.

When the memory block is not selected and the selection signal SELi is low or the memory is in the write state and the write signal
When ▼ goes low, the MISFETs T10 to T13 are non-conductive and T14 to T17 are conductive. Therefore, read line RO
i, ▲ ▼ and read control line RCSi, ▲ ▼
Are connected to the same voltage (here, the intermediate voltage HVL).
As a result, for example, the column selection signal Y0 in FIG.
Even if T3 and T4 conduct when 1 goes high, the read control lines RCSi, ▲
Since current does not flow in ▼, for example, as shown in FIG. 4, a case where a column address of a plurality of memory blocks (including a selected block and an unselected block) is selected by one column selection signal line It is convenient.

FIG. 1D shows a configuration example of the write switch SWWi (i = 0, 1). This circuit includes a plurality of write lines WIi, ▲
One of ▼ is selectively connected to the common write line CWI, ▲ ▼, and the write control line WRI of the selected memory block is set to a high level to perform writing. In the figure, T20, T23 to T26 are N-channel MIs.
SFETs, T21 and T22 denote P-channel MISFETs, INV101 to INV103 denote inverters, and NAND2 denotes a two-input inverted AND circuit. Memory block is selected and select signal
When SELi is at a high level and the memory is in a write state and the write signal WE is at a high level, the MISFETs T20 to T23 become conductive and T24 to T26 become nonconductive. Therefore, the write line WI
i, ▲ ▼ are common write line CWI, ▲ ▼
And a high level is output to the write control line Wri. Thus, for example, when the column selection signal Y01 goes high in FIG. 1 (a), T5 and T6 become conductive, and the data line pair D0, ▲ ▼ becomes the write lines WI0, ▲.
The write information on the write line is written to the data line.

When the memory block is not selected and the selection signal SELi is low or when the memory is in the read state and the write signal WE is
Is low, MISFETs T20-T23 are non-conductive, T24
T26 becomes conductive. Therefore, the write lines WIi, ▲
▼ is connected to the same voltage (here, the intermediate voltage HVL), and the write control line Wri goes low. Thereby, for example, even if the column selection signal Y01 goes high in FIG. 1 (a) and T5 and T6 become conductive, the data line and the write line do not conduct. For example, as shown in FIG. This is convenient when column addresses of a plurality of memory blocks (including a selected block and a non-selected block) are selected by one column selection signal line.

Next, FIG. 1 (e) shows a configuration of a sense amplifier circuit for amplifying a signal read on the common read line CRO, ▲ ▼. In the figure, amp1 is a common read line CR.
O, ▲ ▼ is input, d1, d1 is the first sense amplifier circuit to output, amp2 is d1, ▲ ▼ input, the second sense amplifier circuit is d2, ▲ ▼ output, amp3 is d2, ▲ ▼
T42, T43 are MISFETs for initializing the third sense amplifier circuit before operation. The first sense amplifier circuit amp1 is composed of two current-voltage conversion circuits having the same configuration. The current-voltage converter is a differential amplifier AD1, a P-channel MISFET T
30 and an N-channel MISFET T31. The second sense amplifier circuit amp2 is composed of two differential amplifier circuits DA having the same configuration.
It is composed of 3, DA4. The third sense amplifier circuit amp3 includes two inverting OR circuits MOR1, NOR2 and two inverters INV105,
It is composed of INV106.

Next, the operation of this embodiment will be described with reference to the operation waveforms of FIGS. 1 (f) and 1 (g). Note that here, the data line
An example will be described in which information read out to D0, ▲ ▼ is read and information from the outside is written to D0, ▲ ▼. The same operation is performed selectively for all memory cells in the memory array. It is self-evident that you can do it. Although the case where the operation voltage is 1.5 V is described here, the present invention is not limited to this, and the present invention can be similarly applied and the same effect can be obtained even if the operation is performed at another voltage.

First, the read operation will be described with reference to FIG. The control signal PC of the precharge circuit unit PR0 falls at time t0, and the precharging operation for the data line ends. Subsequently, the selected word line W0 rises at t1, and a signal is read from the memory cell to the data line D0, ▼. Then, t3
The sense amplifier drive signal CSP from the intermediate potential to the high level, and CSN from the intermediate potential to the low level.
Drive 0. Thereby, the signal read out to the data line is amplified to High and Low by the sense amplifier. Here, in this embodiment, the data line is connected to the gates of the transistors T1 and T2 in the read gate RG0,
3, connected to read lines RO0, ▲ ▼ through T4. Read control line RCS0, ▲ of selected input / output circuit CKT0
▼ is driven low at t1. With this configuration, the data line and the read line are separated, so that the data line
In the middle of amplification before the High and Low levels are determined, the information of the data line is not destroyed even if the column selection signal line Y01 is input at t3 here. Therefore, since the information on the data line can be transmitted to the read line without destroying the data line, the speed of the read operation can be increased. The reason why the speed can be increased as compared with the related art and the effect will be described later in detail. Here, the signal voltages of the read line and the common read line, that is, RO0 and ▲ ▼ and CRO and ▲
The voltage difference of ▼ is about 20 mV, the output signal amplitude of the first sense amplifier circuit (voltage difference between d1 and ▲ ▼) is about 200 mV, and the output signal amplitude of the second sense amplifier circuit (d2 and ▲
▼) is about 1 to 1.5V. That is, the voltage gain of the first sense amplifier is about 10 and the voltage gain of the second sense amplifier is about 5 to 7. The voltage amplification rate of the third sense amplifier circuit is about 1-2. However,
The third sense amplifier circuit has a function of storing output information, a so-called latch function. That is, by amplifying the input signal and setting both inputs low, an output corresponding to the previous input is held until the next input is input. Thus, it is not necessary to always put all of the first to third amplifier circuits into operation, and after output, the first or second or both amplifier circuits are brought into a non-operation state to reduce power consumption. can do.

This figure also shows an example of a so-called static column operation in which a column address is switched and another information is read after reading one piece of information. That is, the information is read out by raising Y23 next to the column selection signal Y01.
According to this embodiment, the voltage amplitude of the read line and the common read line is reduced to 20 mV, which is 1/10 of the conventional voltage, by using the input of the sense amplifier circuit as a current as described later. As a result, the time required for charging and discharging the parasitic capacitance of the read line and the common read line can be reduced to about 1/10, and the delay from switching the address to outputting the information can be extremely reduced.

Next, an example in which a write operation is performed following a read operation will be described with reference to FIG. In the figure, the first read operation is the same as in FIG. 1 (f). t4
In, when WE goes high, the column selection signal line Y01 remains high, the control signal line RCS0 of RG0 goes to HVL (0.75V), and the control signal line WR0 of the write gate WG0 goes high. At the same time, when write data is given to the write I / O lines WI0, ▲ ▼, the transistor T
Data is written to data lines D0, ▲ ▼ through 5, T7, and T6, T8.

As shown in the above example, as a means to change the transfer impedance between the I / O line and the data line in the write operation and the read operation, the read operation margin is separated by separating the read line and the write line. And the write operation margin can be individually set, so that the operation can be speeded up and stabilized even at a low voltage operation.

Next, the effect of the sense amplifier circuit used in this embodiment will be described in the second.
This will be described with reference to the drawings. FIG. 2 (a) schematically shows a configuration of a conventional sense amplifier circuit, and FIG. 2 (b) schematically shows a configuration of a sense amplifier circuit according to the present invention. FIG. 2 (c) schematically shows operation waveforms of the conventional sense amplifier circuit and the sense amplifier circuit according to the present invention. In the conventional circuit, the minute signal read from the memory cell MC to the data line (D0, ▲ ▼) is amplified by the sense amplifier SA0, and then the column selection signal Y is amplified.
Turn on the MISFET T50, ▲ ▼ controlled by 01,
It was transmitted to the read line (IO0, ▲ ▼). Conventional circuits have two problems that hinder speeding up. One is that it is necessary to turn on the MISFET after it has been sufficiently amplified by the sense amplifier. Otherwise, the data line (CD approx.
This is because there is a difference of several tens of times between the readout line (CR about 8 pF) and the readout line (CR about 8 pF), so that a large charge flows from the readout line, and the information that has been prematurely amplified is destroyed. The other is that it is necessary to amplify a read line having a large parasitic capacitance to a large voltage of 200 mV with a sense amplifier having a small driving capability. This is due to the signal detection sensitivity of the second sense amplifier circuit in the next stage.

Therefore, in the present invention, the NMOS transistors T1 and T2 which receive the signal of the data line at the gate are provided, and the sense amplifier and the read line are separated. This allows the MISFET T controlled by the column select signal without waiting for the data line to be sufficiently amplified.
3. Since T4 can be turned on, the voltage information of the data line can be converted into current information and read at high speed. Further, a current sense circuit constituted by a P-channel MISFET and an amplifier circuit is provided so as to be suitable for low-voltage operation, so that a voltage output proportional to a current input can be obtained. By using current input, the voltage amplification of the signal line can be suppressed by about one digit (200mV → 20mV) smaller than before,
The time required for charging and discharging the parasitic capacitance CR is greatly reduced, and the speed is increased.

FIG. 2 (d) compares the operating speeds of the conventional sense amplifier circuit and the sense amplifier circuit according to the present invention based on computer simulation results. Here, the sense time is a delay time from when the signals CSN and CSP for starting the sense amplifier are applied to when a signal voltage of 200 mV is obtained on the I / O line (in the case of the related art), or the first time. It is defined as a delay time (in the case of the present invention) until an output of 200 mV is obtained as the output of the sense amplifier circuit. With the circuit of the present invention,
Since the speed is increased by 20 ns at 1.5 V as compared with the related art, it was shown that the present invention operates at low voltage and at high speed.

As described above, in the present embodiment, the input / output control circuits are alternately arranged on the left and right sides of the memory cell array, and the input / output lines for reading and writing are separated, so that the operation can be performed even at the low voltage operation. Speeding up and stabilization can be achieved. Further, the first sense amplifier circuit for detecting the signal on the read line is constituted by a current-voltage conversion circuit, and the MISFET for driving the read line and the MISFET for converting the voltage of the data line to the current of the read line are complemented. By adopting the configuration of 1 to
A sense amplifier circuit that operates at high speed even with a low power supply voltage of about 2 V can be provided.

FIG. 3 shows an embodiment for further stabilizing the operation. As described above, in the input / output control circuit section, the parasitic capacitance between the data lines could be reduced. Here, the operation is further stabilized by balancing the parasitic capacitance between the data lines in the memory cell array section. That is, the data lines intersect at the center of the memory cell array for each line pair. D1, ▲ ▼ and data line ▲
▼ The parasitic capacitances between are Cc01 _L and Cc01 _R , respectively.
_{Since L} and Cc01 _R match, D1, ▲ ▼ and data line ▲
The parasitic capacitance between ▼ can be equal. Similarly, the parasitic capacitance between D1, ▲ ▼ and the data line D2 can be equalized, so that the parasitic capacitance between adjacent data lines can be balanced between the paired data lines. Therefore, the reading operation can be further stabilized in the memory cell array.

FIG. 4 shows an embodiment in which a plurality of memory cell arrays exist, and the reading operation will be described here. The input / output control circuit CKTij is shared by the left and right memory cell arrays,
Switch transistors T60 to T63 are connected between ij and each memory cell array, and SHRij, which is a selection signal of the memory cell array, is input to their gates. SWRi
Is the common readout line CR shared by the readout line RO and multiple RO lines
This switch is connected to O, and the selection signal SHRij of the memory cell array is also input to this switch. SHRij is set to High in advance. For example, when the memory cell array MA2 is selected, only SHR1 _R and SHR3 _L are set to Low. Here, assuming that the column selection signal Y01 is selected, the signals read out to the data lines D1, ▲ ▼ and D0, ▲ ▼ are passed through the input / output control circuits CKT12, CKT23 to RO12, ▲ ▼.
Read to ▼, RO23, ▲ ▼. These are connected to the common I / O lines CRO0, ▲ through switches SWR1 and SWR2.
Read out to ▼, CRO1, ▲ ▼. In this way, even when a plurality of memory cell arrays exist, it is possible to arrange input / output control circuits alternately on the left and right sides of the memory cell array and to share the input / output control circuits with the left and right memory cell arrays without greatly increasing the chip area. The improvement in characteristics described above can be realized.

FIG. 5A shows an embodiment of a parallel test using the present invention. The parallel test is performed by simultaneously selecting a plurality of column selection signals (multiple selection). That is, at the time of the parallel test, the column selection signal is multiplexed by the test signal TEST. As a result, in the read operation, the read signals of the data lines are simultaneously read to the read lines according to the multiplicity. If all the information of the data lines read at the same time coincides, one of the read lines RO and ▲ ▼ has a “High” voltage level and the other has a “Low” voltage level according to the read information. . If at least one erroneous information is read, both RO and ▲ ▼ are at the “Low” voltage level. on the other hand,
In a write operation, data is written to a data line connected to a write gate selected from input / output lines for writing. Here, in the present invention, even in the case of a parallel test, the parallel test can be performed without providing a new test I / O line,
Information is transmitted from the data line to the AMP as in a normal test. In addition, since the read signal line and the write signal line are separated, the operation margin can be set individually for the read operation and the write operation as described above, and the limitation in increasing the multiplicity is limited. Lost, advanced parallel reading /
Writing becomes possible. In the figure, the drive signal RCS of the read gate RG is a pair line, and in the read operation, the read lines RO,
RCS connected to ▲ ▼ is separated. This is an effective means for determining one erroneous reading even when the multiplicity is increased. When the multiplicity is increased, it is necessary to increase the current flowing from the RO to the RCS. On the other hand, the current flowing from RCS to GND saturates at a certain constant due to the wiring resistance of the read line.
In other words, the potential of RCS rises. Therefore, if the RCS is not separated, the signal current of the I / O line on the side where the erroneous reading has occurred decreases with the multiplicity of operation, making detection difficult. By separating the RCS, the potential of the RCS on the side where the erroneous reading was performed does not increase, and only the current flowing from the RO to the RCS need be detected, so that more accurate detection can be performed. As mentioned above,
The present invention enables a highly parallel test, so that the test time can be significantly reduced.

FIG. 5 (b) shows an embodiment of a specific circuit for determining the multiplicity. Normally, Y0 to Yn-1 are input to the column decoder YD. Yn-1 divides the column direction into two, Yn-2 further divides each into two, and so on. Y0 repeats "0" (Low) and "1" (High) for each column selection signal. Here, the test signal TEST is set to High, and the OR gate output signals of ▲ ▼, Yn−1 and TEST are set to AYn−1, AYn−1 ′, which are input to the column decoder instead of ▲ ▼, Yn−1. AYn-1, AYn regardless of Yn-1 High or Low
-1 'can be made high and two column selection signals can be selected, so that the multiplicity can be made two.

FIG. 5C shows an embodiment in which the multiplicity is set to 4. Yn−
If the NAND gate outputs of 1 and Yn-2 are input to the NAND gate together with TEST, their outputs are set to AYn-20 to 3, and if they are input to the column decoder, the multiplicity can be set to 4. As described above, based on the embodiment shown in FIGS. 5 (b) and 5 (c), the column decoder can be multiplexed at the time of the parallel test, and the test signal TEST is set to low at the time of the normal test.
The column selection signal of the book can be selected. FIG. 5D shows an embodiment of a sense amplifier circuit for realizing a parallel test. A method of outputting a test result at the time of the parallel test will be described with reference to FIG. During a normal read operation, the output after current-voltage conversion is directly input to the inverting and non-inverting inputs of the two differential amplifier circuits DA4 and DA5 constituting the amp2T.
Input those outputs to amp3. During parallel test to the non-inverting inputs of the two differential amplifier circuit DA4, DA5 inputs the V _RT as the reference voltage. In the parallel test, if at least one erroneous information is included in the multiple data lines selected,
A current flows through both RO and ▲ ▼. Accordingly, the current-voltage conversion output d1, ▲ of the first sense amplifier circuit amp1
▼ are both low levels. On the other hand, the reference voltage _VRT is set to a voltage between the high level and the low level of the current-voltage conversion output. In this way, when at least one erroneous information is included, a high level is output to the outputs of the two differential amplifier circuits DA4 and DA5. That is, when both d2 and d2 are at a high level, it can be determined that the information read in parallel contains erroneous information. At the time of the parallel test, these outputs are taken into the judgment circuit TEJ by setting ▲ ▼ to Low. TEJ outputs High or Low to ERR according to the output voltage of d2, ▲ ▼. That is, if all the results of the parallel test are correct, ERR outputs Low, and if at least one is wrong, it outputs High. The determination of the parallel test result with the multiplicity increased as described above can be performed using the input / output circuit system and the sense amplifier circuit according to the present invention.

FIG. 5E shows an embodiment of the reference voltage _VRT generating circuit used for the parallel test. In the same figure, the current-
And using the voltage conversion circuit, and generates a V _RT by the High parallel test signal TEST during parallel test. In this circuit, a reference current corresponding to about half of the signal current is applied to the input of the current-voltage conversion circuit. As a result, when a signal current flows through both RO lines, the converted voltage becomes V _RT
Smaller. In addition, if the result of the parallel test is correct, the voltage after one conversion becomes larger than _VRT . Therefore, the test result can be determined by comparing the converted voltage with _VRT .

FIG. 5 (f) shows a specific embodiment of the write switch SWW. WE is a write signal. The present embodiment is based on FIG. 4 where a plurality of memory cell arrays exist, and it is assumed that the memory cell array on the right side of SWW operates (SELR is high and SELL is low). TEST is L during parallel test
ow. During the read operation, WE is low, and WI and ▲ ▼ are set to the same potential by the circuit WST. When the write operation starts, WE goes high. Since the signals input to GR are all high during the read operation, WER is low.
Then, one WEL becomes High. Accordingly, the write control signal WR goes high and the N-channel MISFET T7
CWI through 7, T78 and P-channel MISFET T75, T76
Data is written from CWI to WI, ▲ ▼.

FIG. 6 shows an embodiment in which a voltage level of a power supply line on a high voltage side of a sense amplifier for detecting and amplifying a signal read from a memory cell to a data line can be arbitrarily set. The write voltage level for writing “1” to the memory cell is the voltage level of the power supply line on the high voltage side of the sense amplifier.
Therefore, it is only necessary that the voltage level of the power supply line on the high voltage side can be arbitrarily set. Here, two types of power supply lines on the high voltage side are provided, and one of the power supply lines is used as a _VDL for normal writing. Other power supply line V _DM is to be arbitrarily set from outside the chip, for example. As a result, the signals MT0, MT1
Is low, the sense amplifier drive signal CSP is V _DL , and conversely, if the signals MT0 and MT1 are high, the sense amplifier drive signal C is
SP can be _VDM . According to the present embodiment, only the voltage level of the information “1” can be set arbitrarily. Further, the voltage level of the information “1” can be changed and set every other pair. Therefore, as in the case of testing the coupling noise between data lines, a voltage can be written as soon as information is inverted every other pair, which is effective when a margin test is desired. In addition, there is an effect that the test time for the information retention characteristics of the memory cell can be shortened.

7 and 8 show an embodiment of the word drive circuit according to the present invention. The feature of this embodiment is that a static word driver including QD1, QD2, QP, and QT is used instead of the conventional dynamic word driver. Further, a voltage conversion circuit VCHG that always generates a voltage higher than the data line voltage VL by VT of the switch transistor QS of the memory cell is provided as the power supply. Less than,
The operation of this embodiment will be described.

First, when the X decoder XD is selected by the address signal Ai, its output N1 goes low. Then, the charge of the node of N2 is extracted through the transistor QT, and N2 is also Lo.
It becomes w level. Then, the transistor QD1 turns on and the word line W rises to the level of VCH. Since the level of VCH is higher than VL + VT (QS), the maximum VL
Is written.

Next, in the precharge cycle, P first goes low, which turns on QP and sets node N2 to VCH. Then, since QD1 is turned off and QD2 is turned on, the word line W is at the low level, and the charge is held in the memory cell.

As described above, in the present embodiment, since the gate voltage of the drive transistor operates at the low level, the word driver operates stably even when the power supply voltage becomes low.

FIG. 11 shows a specific embodiment of the word line voltage conversion circuit VCHG of FIG. FIG. 12 shows an internal waveform and input timing at the time of starting the circuit. The feature of this embodiment is that the output voltage is fed back to the precharge transistor (QB in FIG. 11) in the charge pump circuit in order to obtain a fast rise and a high output voltage even at a low power supply voltage. The operation will be described below.

First, consider the case where the input pulse φ is High and Low, respectively. At this time, since the voltage of the node B is charged from VL through QC, it becomes VL-VT. On the other hand, node A is a capacitor
The value is determined by the charge stored in CA and CD and the amplitude of φ. In this embodiment, this voltage is assumed to be VL. Next, when the voltage of φ is replaced, the node B is boosted by CB and becomes VL−VT + αVL. Where α is CB and node B
Is the ratio of the total capacity. At this time, the voltage at the node A becomes a voltage VL-2VT + αVL lower than the voltage at B by VT of QA.

Next, when the voltage of φ is switched again, the voltage of the node A is boosted again. At this time, if it is higher than VL by δ, the voltage at node B is precharged to VL-VT by QC, so QB turns on and the voltage at node B is further raised by δ. Therefore, in the next cycle, the voltage of the node B is further increased, and the voltage of the node A is further increased. By repeating the above, the voltage of the node A rises, and finally, reciprocates between VL and 2VDL.

To this output, a rectifier circuit indicated by 2, that is, a diode-connected MOS transistor QD is connected, and a smoothing capacitor CD is further added to the output.
Becomes This output voltage becomes 2VL-VT in a no-load state.

Here, the circuit connecting QA and CA is divided into two, and one of the output points of each circuit, that is, one of the connection points between QA and CA, is connected to the rectifier circuit 2 and the other is connected to the gate of QB. Is separated from the load circuit, the gate voltage becomes high enough that no current flows through the load circuit, and the node A
Voltage can be raised.

The feature of this circuit is that the precharge voltage is increased by feeding back the output voltage to the precharge circuit as described above, and a high output voltage can be obtained even with a low power supply voltage. For example, assuming that VL = 0.8 (V) and VT = 0.5 (V), when there is no feedback, that is, when there is no QB, the voltage of the node B is only up to 1.1V (2VL-VT when α = 1). As a result, node A is 1.4V (3VL-2VT) and VCH is 0.9
V (3VL-3VT). If there is a QB, 1.6V (2VL), 1.6 (2VL), 1.1V (2VL-V
T) and both are higher than the former.

FIG. 17 shows the results of a computer simulation comparing the step-up ratios when there is a feedback transistor QB (the present invention) and when there is no feedback transistor (the conventional method). Here, a solid line indicates a transistor having a standard threshold voltage, and a broken line indicates a transistor having a low threshold voltage. From this figure, it can be seen that the power supply voltage drops sharply from 1 to 1.5 V in the conventional method, while it is constant up to 0.8 V in the present invention, and operates stably even at a low power supply voltage. Here, it is assumed that there is no voltage drop due to the threshold voltage of the transistor in the rectifier circuit.

The embodiment shown in FIGS. 13 and 14 is a circuit for obtaining a higher output voltage. The feature of this embodiment is that the gate voltage is synchronized with the output voltage of the charge pump circuit to reduce the voltage drop in the rectifying transistor,
When the output is at the high level (2VL), it is higher by VT or more, and when the output is at the low level (VL), it is set to VL.

In FIG. 13, CP and QD are the aforementioned charge pump circuit and rectifier circuit. In addition, Q1 to E19 and C1 to C4 are added elements, Q1 is a rectifying transistor, and Q3 to Q10 and C1 to C3 are Q1.
Circuit to control the gate voltage of Q11-Q13, Q15-Q18, C4
Is a charging circuit for the gate boosting capacitor C3, and Q19 is a precharge transistor for accelerating the rise of VCH.
PA and ▲ ▼ are PB and ▲ of the charge pump circuit.
▼ is a control signal of the gate voltage control circuit. The operation will be described below.

1 is the charge pump described above in which PA and PA are alternately Hi.
gh and Low, the voltage of node A is boosted and V
It reciprocates between L and βVL (β ≒ 2). At this time, PA and ▲ ▼ are set so that the High periods do not overlap each other as shown in FIG. This is shown in FIG.
When the voltage at the node B is still higher than VL + VT and the voltage at the node B is still higher than VL + VT, the φ corresponding to the PA rises and the voltage at the node A rises. This is because the charge stored in the CA leaks to the power supply side.

Next, for the rectifier circuit, PA and PB are Low, ▲ ▼, ▲
When ▼ is High, the voltage of the gate G of Q4 is equal to VL since the gate of Q4 is boosted to VL + VT or more by C1. At this time, since node A is VL, there is no backflow from VCH to node A. After the gate of Q11 precharges C4 to VCH (2VL) -VT by Q13 and Q18,
Since the voltage is boosted by (VL), it becomes 3VL-VT. Therefore, VL
If ≧ 2VT, the voltage is raised to VCH (2VL) + VT or more, and node C
CH. At this time, the voltage between the gate and source of Q10 is VCH
Since the voltage exceeds -VT at -VL, the transistor turns on, and the gate voltage of Q9 becomes equal to that of the node C. Therefore, Q9 turns off and no current flows from node C to node G.

Next, when PA and PB become High and ▲ and ▼ become Low, the node A becomes 2VL and the node C becomes VL + VCH. on the other hand,
Since the gate of Q7 is boosted to VL + VT or more by C3, its source is VL. That is, since the gate of Q9 becomes VL, the voltage between its gate and source becomes VCH, Q9 turns on, and the gate of Q1 becomes VL + γVCH (γ ≒ 1). Therefore, 2VL is output as it is without lowering by VT as in the embodiment of FIG.

In this embodiment, PB is set to a low level before PA, but this is because the gate voltage of Q1 is still VL.
This is to prevent PA from going low when the voltage is equal to or higher than + VT, causing the voltage at the node A to become VL, and preventing the electric charge from flowing back to the node A from the output. The reason why the minimum potential of the gate control circuit is set to VL like the sources of Q4 and Q7 is to reduce the potential difference between the electrodes of the transistors. As a result, the potential difference between the electrodes becomes 2 VL or less, and the same fine transistor as other portions can be used.

The above is the feature of the embodiment shown in FIG. 13. In FIG. 13, the same effect can be obtained by deleting Q7 and Q10 and connecting the gate of Q9 to the gate of Q4. For example, PB is VL, ▲
When ▼ is 0, node C is at VCH + VL, and the gates of Q4 and Q9 are at VL, so Q4 is off, Q9 is on, and node G is
VCH + VL. On the other hand, when PB is 0 and ▼ is VL, node C is VCH (2VL), and the gates of Q4 and Q9 are 2VL, so Q4 is on, Q9 is off, and node G is VL.

FIGS. 15 and 16 show circuits for generating the timing shown in FIG. In FIG. 15, inverters I5 to I8, resistor R2, capacitor C2, NAND gate NA2, and NOR gate NO1 are P
A, circuit to prevent duplication of ▲ ▼, I2, I3, R1, C1
Is a circuit to determine the delay time of the fall of PA and PB,
I9 to I13 and NA3 are circuits that create a delay when PA and PB fall. I14 to I25 are buffer inverters. This may be any number of steps as long as the odd number of steps is the same, and may be adjusted according to the magnitude of the load. FIG. 16 is an example of a circuit for generating the input pulse OSC of the circuit. This circuit is generally called a ring oscillator. The feature of this circuit is that the time constants of R and C are made sufficiently larger than the delay time of the inverter in order to suppress the fluctuation of the oscillation frequency due to the power supply voltage. For this reason,
Even if the ratio of the VT of the transistor to the power supply voltage is 1: 3 or less and the power supply voltage dependence of the delay time of the inverter is large, the oscillation frequency becomes stable.

In addition to the above countermeasures, by lowering the VT of the transistor of the embodiment shown in FIGS. 11 and 13, the operation at a lower voltage becomes more stable. This is because the driving capability of the transistor is increased by lowering the VT. Although the sub-threshold current increases with the reduction in VT, the number of elements of the voltage conversion circuit is at most several tens, so that it can be almost ignored when viewed on the entire chip. On the other hand, the driving capability of word drivers and memory cells also increases due to the lower VT, but the former is an M-bit class DRAM.
^{Since 3} to 10 ⁴ transistors are used, the leakage current flowing when the transistor is off cannot be ignored. In the latter case, there is a problem that the charge holding time is shortened and the refresh interval must be shortened. This leads to the highest power consumption. Therefore, VT has a low voltage conversion circuit,
It is best to set the word driver as standard and the memory cells higher than the standard.

As described above, according to the present embodiment, the gate voltage of the rectifying transistor can be made higher than the drain voltage by the threshold voltage VT or more, and the backflow of electric charge can be prevented. The value can be increased to 2VL. In addition, by using an oscillation circuit and a timing generation circuit using an RC delay, the delay time between the oscillation frequency and the timing becomes stable with respect to the power supply voltage fluctuation, so that the voltage conversion efficiency can always be kept in the best state. In addition, by providing three types of transistors VT, the voltage conversion circuit is low, the word driver is standard, and the memory cell is higher than standard, so that low voltage stabilization, high speed, and low power consumption can be achieved. Therefore, a semiconductor integrated circuit that operates stably even when the power supply voltage is the electromotive force of one battery can be realized.

Next, an embodiment in which the present invention is applied to an intermediate voltage generating circuit will be described. In the following description of the embodiment, VCC is used as a symbol representing the higher power supply voltage. However, it does not need to be different from the VL used so far, and may be replaced with VL as it is. Although HVC is used as a symbol representing the intermediate voltage, it does not need to be different from the HVL used so far, and may be replaced with HVL as it is. FIG. 18 is a configuration example of a voltage follower circuit according to the present invention. This circuit outputs a voltage substantially equal to the voltage applied to the input, and drives a large load capacitance. In FIG. 1A, reference numeral 1 denotes a first complementary push-pull circuit, which is composed of an N-channel MOS transistor TN2, a P-channel MOS transistor TP2, and bias voltage sources VN1 and VP1. Reference numeral 2 denotes a current mirror type push-pull amplifier circuit, which includes a pair of N-channel MOS transistors TN1 and TN forming a current mirror circuit.
3. P-channel MOS transistor pair TP1 and TP3. Reference numeral 3 denotes a second complementary push-pull circuit, which includes an N-channel MOS transistor TN4 and a P-channel MOS transistor TN4.
MOS transistor TP4 and bias voltage sources VN2, VP2
It consists of.

The constant setting of various transistors and voltage sources of this circuit and the operation in a steady state will be described. The values of voltage sources VN1 and VP1 are chosen to be approximately equal to the gate threshold voltages of transistors TN2 and TP2, respectively. This prevents both transistors TN2 and TP2 from being simultaneously cut off under any operating conditions.
For this reason, it is possible to prevent the output impedance from becoming high and the potential from being unstable or the output voltage from fluctuating depending on the load condition. By making the value of the voltage source substantially equal to the gate threshold voltage of the transistor, the current flowing through the two transistors in the steady state is suppressed to a low value, and the standby power of the integrated circuit is reduced while the power is increased. The load drive capability is obtained. Operation under such a bias condition is generally called class AB operation. Now, assuming that the current values flowing through TN2 and TP2 are IC1 and ID1, respectively, these currents are converted into TP3 by a current mirror circuit including P-channel MOS transistor pairs TP1 and TP3 and N-channel MOS transistor pairs TN1 and TN3. Is converted to a current ID2 flowing through TN3 and a current IC2 flowing through TN3. The current ratio between IC1 and IC2 is β of transistors TP1 and TP3.
The current ratio (mirror ratio) between ID1 and ID2 is
It is almost equal to the β ratio of TN1 and TN3. That is, It is. By setting this ratio to a value of 1 or more, the current can be amplified and the driving capability of the next stage load (terminals 6 and 7) can be increased. In the present invention, this ratio is selected to a value of about 1 to 10. Like the first push-pull circuit, the values of the voltage sources VN2 and VP2 are set to be substantially equal to the gate threshold voltages of the transistors TN4 and TP4, respectively. Thereby, the second push-pull circuit also performs the class AB operation.

Now, the first push-pull circuit is in the steady state,
A description will be given of what happens when the state deviates from the state where 1 = ID1 holds. Force the output voltage from steady state to voltage δ
The current value when V is changed is expressed as follows.

Here, β _N and β _P represent β of the transistors TN2 and TP2, respectively, and I represents a current flowing in the first push-pull circuit in a steady state (that is, I = IC1 = ID1).

Now, for simplicity, are aligned substantially the characteristics of TN2 and TP2, beta _N and beta when _P is assumed to be equal _{(β = β N = β P} ), the above equation Becomes Also, assuming that the mirror ratio of the two current mirror circuits is equal (M = M _N = M _P ), Becomes

For example, if M = 5, β = 1 mA / V ² , and I = 0.2 μA, when the output voltage decreases by 0.1 V (δV = −0.1 V), IC 2 −ID 2 = 20 μA.

In other words, the IC can respond to minute changes of 0.1V
A sufficiently large drive current of 20 μA is obtained with respect to a steady current of 2 and ID2 of 1, μA (0.2 μA × 5). Therefore, the terminal 6 can be driven to the minimum VSS and the terminal 7 can be driven to the maximum VCC even for a slight change in the output voltage, to the limit of the power supply voltage range. In the driving direction, the terminal 7 is driven to VCC when the output voltage decreases, and the terminal 6 is driven to VSS when the output voltage increases. Thus, when there is an error in the output voltage, the second push-pull circuit is driven by the signal obtained by amplifying the error, and the operation is performed to eliminate the error in the output voltage. Therefore, it is possible to provide a much higher driving capability than in the case of simply driving with a source follower circuit as in the conventional example. Further, even if the bias current in the steady state is suppressed to a sufficiently low value, a high drive current can be obtained by amplifying the error. Further, as can be easily understood from the above equation, this circuit operates symmetrically with respect to the direction of the error, so that the same driving capability can be obtained for the charging and discharging of the output.

Next, the accuracy of the present circuit as a voltage follower will be described. In this circuit, an error in the output voltage is detected by the first push-pull circuit, and the amplified signal is used to drive the second push-pull circuit. Therefore, the output voltage accuracy (input / output voltage difference) is determined by the voltage accuracy (input / output voltage difference) of the first push-pull circuit. In the first push-pull circuit, when the steady state, that is, the condition that IC1 = ID1 is satisfied, is obtained, the input voltage V (IN) and the output voltage V
(OUT) is obtained, and becomes as follows.

here, VTN and VTP are the absolute values of the gate threshold voltages of the N-channel and P-channel MOS transistors, respectively. As is apparent from this equation, by giving VN1 and VP1 characteristics that change in accordance with changes in VTN and VTP, respectively, and appropriately selecting the β of the transistor, the N-channel transistor and P Even if the element characteristics of the channel transistor change independently, the voltage difference between the output and the input can be made zero. As described in the next embodiment, the voltage source as described above can be easily configured by connecting the gate and the drain of the OMS transistor of each channel conductivity type and flowing a predetermined current to the OMS transistor. In general, even if there are variations in characteristics between elements of different conductivity types, since the transistors of the same conductivity type go through the same manufacturing process, the characteristic difference between the elements can be suppressed to a sufficiently small value. In particular, with respect to variations in the processing shape and the like, by designing the gate width and gate length to be sufficiently large compared to the processing accuracy, the characteristic difference between the element pairs can be further reduced. For example, taking the gate threshold voltage as an example, the difference between pairs of elements of the same conductivity type can be easily reduced to about 20 to 30 mV or less.
Variation in the difference between elements of different conductivity types is up to 20
In general, the value is about one digit, which is about 0 mV.
As described above, the voltage accuracy (input / output voltage difference) of the first push-pull circuit is suppressed to about 20 to 30 mV, which is determined by the threshold voltage difference between the transistor pair, which is about one digit lower than the conventional method.

Now, the operation during the next transition will be described with reference to FIG. Now, consider a case where the input voltage V (IN) decreases from time t0 to t1 and increases from time t4 to t5. Since the output does not immediately follow immediately after the input voltage drops, the transistor TN2 is cut off from the time t1 to t2, and the value of the current IC1 becomes almost zero. ID1
Increases, and the voltage V (6) at the terminal 6 is reduced to approximately VSS (0V). As a result, the driving capability of the transistor TP4 increases, and the output OUT is discharged at high speed. After time t2,
When the difference between the output voltage and the input voltage decreases, the transistor TN
2 starts to conduct, and at time t2 when the voltage difference between the input and the output finally disappears, IC1 = ID1, and a steady state is established. When the input voltage rises, symmetrically, the voltage at terminal 7 becomes VC
It rises to C and charges the output at high speed.

As described above, according to the present invention, even if there is a variation in the manufacturing process, the error between the input and output voltages is small, and the voltage follower that can charge and discharge a large-capacity load at high speed in a transient state. Can be provided. This circuit can be used not only as a voltage follower, but also as an output terminal OU
By inputting a signal current to T and extracting an output from the terminal 6 or 7, it can be used as a high-performance current detection circuit.

Next, an embodiment in which the above-described circuit is applied to an intermediate voltage (VCC / 2) generating circuit of a dynamic memory will be described with reference to FIG. FIG. 20 (a) is a configuration example of an intermediate voltage generating circuit according to the present invention. In the figure, 30 is a reference voltage generating circuit, 31 is a first complementary push-pull circuit, 32 is a current mirror type amplifier circuit, and 33 is a second complementary push-pull circuit. The reference voltage generation circuit generates an intermediate voltage at the terminal 34 by dividing the power supply voltage in half by two resistors R3 and R4 having the same resistance value. By using the same type of elements for the resistors R3 and R4, a fairly accurate value can be obtained for the intermediate voltage. Note that the element for obtaining the intermediate voltage is not limited to a resistor, and it is obvious that a similar circuit can be formed using, for example, a MOS transistor or the like. The first push-pull circuit is basically the same as the push-pull circuit 1 shown in FIG. Here, a resistor R5 and an N-channel MOS transistor TN10 are used instead of the voltage source VN1, and a resistor R6 and a P-channel MOS transistor TP10 are used instead of the voltage source VP1.
Are used respectively. By doing so, as described in the previous embodiment, the voltage of the terminal 35 is always applied to the input terminal.
34, it can be automatically set to a value which is higher by approximately the gate threshold voltage of the N-channel MOS transistor. The resistance value is selected so that the current flowing through R5 or R6 becomes a small value that is a fraction to one-tenth of the current flowing through R3 or R4. This is because even if the characteristics of the N-channel transistor and the P-channel transistor vary independently, and the current value flowing (or flowing) from the push-pull circuit to the reference voltage generating circuit fluctuates, the voltage at the terminal 34 is affected. This is to prevent fluctuation. The current mirror type amplifier circuit 32 has exactly the same configuration as the current mirror type amplifier circuit 2 shown in FIG. The second push-pull circuit is basically the same as the push-pull circuit 3 shown in FIG. Here, instead of the voltage source VN2, an N-channel MOS transistor TN14 is connected to the voltage source VN.
A P-channel MOS transistor TP14 is used instead of P2. By doing so, similarly to the case of the first push-pull circuit, the value of the bias current flowing through the push-pull circuit is kept from changing with the change in the threshold voltage of the transistor. With the above circuit configuration, an intermediate voltage with high accuracy can be obtained for the output HVC, and the load capacitance CL can be charged and discharged at high speed.

20 (b) and 20 (c) show the results obtained by computer analysis of the performance comparison between the present circuit system shown in FIG. 20 (a) and the conventional circuit system shown in FIG. In FIG. 20 (b), the horizontal axis represents the difference between the absolute values of the gate threshold voltages of the N-channel transistor and the P-channel transistor, and the vertical axis represents the value of the intermediate voltage. From this result, in the conventional circuit,
When the threshold voltage difference fluctuates by ± 0.2 V, the output voltage fluctuates by about ± 100 mV (about ± 13% with respect to 0.75 V), whereas in the circuit of the present invention, the output voltage fluctuates by about ± 8 mV ( (Approximately ± 1% with respect to 0.75V), which can be reduced by one digit or more compared to the conventional case. FIG. 20 (c) plots the rise time of the output voltage after the power is turned on against the power supply voltage.
The rise time is defined as the time when the output voltage reaches 90% of the steady state value. Also, the value of the load capacity is 64 Mbit D
The total capacity of the bit line precharge power supply and plate electrode of the RAM is assumed. As can be seen from this analysis result, according to the circuit of the present invention, it is possible to raise the load in about an order of magnitude shorter than the conventional circuit.

FIG. 21 (a) is a circuit diagram showing another embodiment of the present invention. In the figure, 40 is a complementary push-pull voltage follower circuit, and 41 is a tri-state voltage follower circuit.
It is a buffer. The voltage follower circuit is basically the 18th
This is the same as the push-pull circuit 1 in FIG. Here, the tri-state buffer operates so as to supplement the driving capability of the push-pull circuit. The tri-state buffer is a P-channel transistor TP21 and an N-channel transistor TN21 for driving a load, two differential amplifier circuits (comparators) AMP1 and AMP2 for driving these transistors, and two voltages for setting an offset amount. With source VOSL
VOSH. The operation of this circuit depends on which of the following three voltage conditions applies.

(1) V (OUT)> V (IN) + VOSH (2) V (IN) + VOSH> V (OUT)> V (IN) -VOSL (3) V (IN) -VOSL> V (OUT) (1) Under the voltage condition, the output voltage is higher than the voltage at terminal 43.
The voltage at OUT rises and the voltage at terminal 45 rises to a higher voltage level (V
CC). Also, the voltage of terminal 44 is high (VC
C). Therefore, N-channel transistor TN21
Is turned on, the P-channel transistor TP21 is cut off, and the load is discharged. Under the voltage condition (2), the voltage of the output OUT becomes lower than the voltage of the terminal 43, and the voltage of the terminal 45 becomes a low voltage level (VSS). In addition, the voltage of the terminal 44 maintains a high voltage level (VCC). Therefore, the two transistors TN21 and TP21 are both cut off, and the output is in a high impedance state. Under the voltage condition (3), the voltage of the output OUT becomes lower than the voltage of the terminal 42, and the voltage of the terminal 44 becomes a low voltage level (VSS). Further, the voltage of the terminal 45 maintains a low voltage level (VSS). Therefore, the N-channel transistor TN21 is cut off,
P-channel transistor TP21 becomes conductive and charges the load. Thus, there are three states (discharge when the output voltage increases beyond a certain range around the input voltage, charging when the output voltage decreases below the certain range, and neither charging nor discharging if within the certain range) ( (Tri-state). The operation of this circuit during a transition is shown in FIG. Now, consider the case where the input voltage V (IN) drops at time t0 and rises at time t2. At the time of the fall, the voltage of the terminal 45 is VC from the time t0 to the time t1 when the output voltage becomes equal to “(voltage in a steady state) + VOSH”.
C, the transistor TN21 is turned on, and the load is discharged. At the time of rising, the voltage of the terminal 44 becomes VSS until the time t3 when the output voltage becomes equal to “(voltage in a steady state) −VOSL” from the time t2, and the transistor TP21
To conduct and charge the load.

As described above, by combining the push-pull circuit with the tri-state buffer, when the voltage error between the input and the output becomes larger than a certain level, the transistor having a high driving capability is turned on to increase the response speed in the transient state. be able to. Setting the values of the two voltage sources VOSL and VOSH for setting the offset amount to a value as small as possible can speed up the convergence to the set voltage. However, in order to avoid malfunction, a differential amplifier circuit (comparator) AMP1 is used. And AM
The value must be sufficiently larger than the input offset voltage of P2. When configuring a circuit with MOS transistors,
This value is preferably set to 50 mV or more. Note that the circuit configuration of the tristate buffer is not limited to the example shown here, and any other system may be used as long as the same function is realized.

Next, referring to FIG. 22, a voltage follower using a tri-state buffer is connected to an intermediate voltage (VC
C / 2) An embodiment applied to a generation circuit will be described. FIG. 22 (a) is a configuration example of an intermediate voltage generating circuit according to the present invention. In FIG. 22 (a), 50 is a reference voltage generation circuit, 51
Is a voltage follower circuit described in FIG. 18, and 52 is a tri-state buffer. This enhances the restoring ability when a voltage error between input and output becomes large by adding a tri-state buffer to the intermediate voltage generating circuit shown in FIG. 20 (a). Hereinafter, the configuration and operation of the tri-state buffer will be described. The feature of this embodiment lies in that the first push-pull circuit is used as it is, an error voltage is detected using the difference in the mirror ratio of the current mirror circuit, and the tri-state buffer is activated. In FIG. 22 (a), TP36 and TP37 are P-channel MOS transistors, TN36 and TN37 are N-channel MOS transistors, INV1
And INV2 are inverters, TP38 is a P-channel MOS transistor that drives a load with the output of inverter INV1, T
N38 denotes an N-channel MOS transistor in which a load is driven by the output of the inverter INV2. TP32 and TP36, TP32 and TP37, TN32 and TN36, TN32 and TN37
Form a current mirror circuit.
Now, the current flowing through the transistor TN31 is denoted by IC1, the current flowing through the transistor TP31 is denoted by ID1, the current flowing through the transistor TN36 is denoted by ID2, and the current flowing through the transistor TP36 is denoted by IC2. The relationship between the output voltage error δV and IC1, ID1 is
As explained earlier, Can be approximated. The mirror ratio of the current mirror circuit is Then, the following equation is obtained.

Now, when the offset voltage Vos is applied to the output, IC2
= A becomes 1D2, placing the current value at that time and I _2, the offset voltage Vos is It is expressed as here, The β is β of the transistors constituting the first push-pull circuit, I ₁ is the current flowing in the first push-pull circuit in steady state. For example, I ₁ = 0.2 μA, I ₂ = 1 μ
A, if β = 1 mA / V ² , M _N1 = 1, M _P1 = 0.2, the value of the offset voltage Vos is −100 mV. That is, when the output voltage drops from the steady value by 100 mV or more, the input voltage of the inverter INV1 changes from the low level to the high level, the output voltage changes from the high level to the low level, and the driving P-channel MOS transistor TP38 is turned on. Charge the load. Similarly, by appropriately selecting the constants of the transistors TP37 and TN37, when there is a predetermined positive offset, N
The channel MOS transistor TN38 can be turned on to discharge the load.

As described above, by adopting the circuit configuration as shown in this embodiment, the same function as that shown in FIG. 21 can be realized. Further, in this circuit method, since the offset amount is determined by the mirror ratio of the current mirror circuit, the offset amount can be accurately set if care is taken to reduce the characteristic difference between the transistor pair. Further, since there is no need to separately provide a high-precision differential amplifier circuit, high performance can be realized with low power consumption and a simple configuration.

FIG. 22 (b) shows the result obtained by computer analysis of the performance comparison between the present circuit system and the conventional circuit system shown in FIG.
FIG. 22 (b) shows the rise time of the output voltage after the power is turned on preset to the power supply voltage. The rise time is defined as the time when the output voltage reaches 90% of the steady state value. The value of the load capacitance is assumed to be the total capacitance of the bit line precharge power supply and the plate electrode of the 64-Mbit DRAM. As can be seen from this analysis result, according to the circuit of the present invention, the rise time can be further reduced by about half an order as compared with the embodiment shown in FIG.
The load can be started in about one and a half digits shorter than the conventional circuit. As described above, by combining a tri-state buffer with a push-pull circuit,
Further, it is possible to provide a voltage follower circuit capable of following an input at a higher speed. Since the setting accuracy of the voltage is determined by the push-pull circuit, the voltage error between the input and the output can be made extremely small as in the case of the previous embodiment.

In the above embodiment, the circuit configuration for driving a large-capacity load in an integrated circuit (LSI) at high speed has been described. However, when driving at a higher speed, a transient current at the time of charging and discharging becomes a serious problem. For example, the load capacitance of the intermediate voltage generation circuit of a DRAM of about 64 Mbits is about 115 nF, and the current value when driving this with an amplitude of 1 V for 5 μs reaches 23 mA. This is comparable to the current consumption of a DRAM.
Influence on main circuit characteristics, such as power line noise generation,
Because there is a risk of lowering the reliability of the drive signal wiring,
Not preferred. Generally, in an ultra-highly integrated LSI, particularly in a memory, the entire LSI is often composed of a plurality of blocks of the same type, and at the time of operation, a configuration is often adopted in which only a part of the blocks is activated. In such an LSI, it is effective to apply the embodiments described below.

FIG. 23 shows an embodiment in which the present invention is applied to an intermediate voltage supply system of a dynamic memory (DRAM). In FIG. 3A, MB0, MB1 to MBi are i + 1 memories
Blocks, 60 to 62 are word line selection circuits, 68 to 70 are intermediate voltage lead lines from each memory block, 76 and 77 are two sets of intermediate voltage generation circuits, and 74 and 75 are two sets of intermediate voltage generation circuits. Signal lines for supplying the intermediate voltages HVC1 and HVC to each memory block, and 71 to 73 are used to store one of the two signal lines
This is a switch provided for each block so as to be supplied to the block. The memory block MB0 is a memory cell array MA0 in which memory cells are arranged two-dimensionally, an input / output control for amplifying a signal read from the memory cell and outputting the amplified signal to the outside or writing an external signal to the memory cell. It comprises a circuit block MC0, an input / output circuit 67 and the like. DL0, ▲
▼, DLj, ▲ ▼ are data lines for transmitting signals to memory cells, 63 is a plate electrode forming the opposite electrode of the storage capacitor, and 64 is a precharge voltage supply arranged to set the data line to an intermediate voltage when not selected. Line, PC is a precharge signal line, SA0 to SAj are sense amplifiers for detecting and amplifying signals read from memory cells, and 65 and 66 are common input / output lines for transmitting signals between the input / output circuit 67 and each data line. Vs. IO0 to IOj
Is an IO gate for controlling connection between the data line pair selected by the address designation signal and the common input / output line pair.

Now, let us consider a case where only one block MB0 is selected from the (i + 1) memory blocks to be in an operation state. At this time, one word line in MA0 is selected by the word line selection circuit 60, and transitions to a high level. At the same time, the switch 71 is controlled, and the intermediate voltage lead line 68 is connected to the intermediate voltage supply signal line 75. On the other hand, the lead lines 69 and 70 from the unselected memory blocks MB1 to MBi are:
It is connected to a signal line 74 for supplying an intermediate voltage. In this way, the load of i memory blocks is connected to the intermediate voltage generating circuit 76, whereas the load of only one memory block is connected to the intermediate voltage generating circuit 77. For example, when i = 15, the load capacitance driven by the intermediate voltage generation circuit 77 is equal to the load capacitance driven by the intermediate voltage generation circuit 76.
It becomes 1/15. Therefore, even if the same circuit is used for 76 and 77, the intermediate voltage of the selected block MB0 operates 15 times faster than the intermediate voltage of the non-selected block. From the viewpoint of the circuit performance, the response speed of the unselected memory block is independent of the performance of the memory. Therefore, the performance of the entire memory can be improved with almost no increase in transient current. FIG. 23 (b) shows a temporal change of the intermediate voltage when the power supply voltage fluctuates during the memory operation. That is, it is assumed that the voltage VCC has dropped between time t0 and time t2. Also, between time t0 and t1 and at time t3
Hereinafter, it is assumed that the memory block MB0 is selected and the memory block MB1 is selected from the time t1 to t3. From time t0 to t1
During the period, since the block MB1 is not selected, the intermediate voltage V
(69) responds slowly, whereas block MB
Since 0 is selected, the intermediate voltage V (68) follows at high speed. At time t1, block MB1 is selected, block MB0
Is switched to non-selection, this time, V (69) quickly changes toward the voltage to be set. As described above, according to the present embodiment, a large-capacity load such as an intermediate voltage of a dynamic memory can be supplied without substantially increasing a transient current.
It becomes possible to drive at a substantially high speed. In this example, an example in which the present invention is applied to an intermediate voltage of a dynamic memory has been described. However, the application range is not limited to this. The present invention can be applied to an integrated circuit in general.

As described above, the details of the present invention have been described with reference to the embodiments.
The scope of the present invention is not limited to these.
For example, here, the case where an LSI is composed of CMOS transistors has been mainly described, but an LSI using a bipolar transistor, an LSI using a junction type FET, a BiCMOS type LSI combining a CMOS transistor and a bipolar transistor, and a silicon Other materials, for example, LSI in which elements are formed on a substrate such as gallium arsenide can be applied as they are.

In this embodiment, the current mirror circuit is used as the current amplifier circuit, but another current amplifier circuit can be used.

The features of the semiconductor device according to the present invention are summarized as follows.

(1) A semiconductor device which operates by externally applying a first power supply voltage (VSS) and a second power supply voltage (VCC) higher than the first power supply voltage (VSS), and which is different from the first and second power supply voltages. Means for generating the power supply voltage is provided on the device, and is operated when the difference between the second and first power supply voltages is 2 V or less.

(2) In (1), the difference between the third power supply voltage and the first power supply voltage is the difference between the second power supply voltage and the first power supply voltage.
1.5 times or more.

(3) In (1), the third power supply voltage is an intermediate voltage between the first power supply voltage and the second power supply voltage.

(4) A semiconductor device which operates by externally applying a first power supply voltage (VSS) and a second power supply voltage (VCC) higher than the first power supply voltage (VSS), and which is different from the first and second power supply voltages. Means for generating a power supply voltage and a fourth power supply voltage on the device, and operates at a difference between the second and first power supply voltages of 2 V or less, and the third power supply voltage and the first power supply voltage. The voltage difference is at least 1.5 times the difference between the second power supply voltage and the first power supply voltage, and the fourth power supply voltage is an intermediate voltage between the first power supply voltage and the second power supply voltage. is there.

(5) In any one of (1) to (4), a voltage / current exchange means for connecting the input signal voltage to the gate of the MISFET and converting the current into a signal line current, and reconverting the current into an output signal voltage Having current / voltage means, and forming at least a current path of the voltage / current conversion means with a MISFET of a first conductivity type;
The current path of the current / voltage conversion means is formed of a second conductivity type MISFET complementary to the first conductivity type.

(6) In (5), the voltage of the signal line is an intermediate voltage between the first power supply voltage and the second power supply voltage.

(7) In (6), for the one signal line, a plurality of voltage / current converting means, one current / voltage means, and one of the plurality of voltage / current converting means are connected to a signal line. And selection means for connecting to

(8) In any one of (1) to (7), a dynamic memory is partially included.

(9) In (8), the dynamic memory includes at least one memory cell array including a plurality of data line pair groups, a word line group, and a memory cell group arranged at an intersection of the data line and the word line. A semiconductor memory having an input / output control circuit group for selecting a column address for reading information from a data line to a signal line shared by at least two pairs of data lines or writing information from the signal line to the data line, Input / output control circuits connected to the data lines of the cell array are arranged alternately on the left and right sides of the memory cell array, and change the transfer impedance between the data lines and the signal lines of the human output control circuit during read and write operations. Let it.

(10) In (9), as means for changing the transfer impedance of the input / output control circuit, a signal line called a reading operation and a signal line used for a writing operation are provided independently.

(11) In (10), as means for independently providing a signal line, at least one insulating gate (MI) is provided between the signal line and the data line used for the read operation of the input / output control circuit.
S) type transistor having a gate connected to a data line and a source connected to a signal line, and between a signal line and a data line used for a write operation of an input / output control circuit. Has at least one insulated gate (MIS) transistor, a data line is connected to its drain-in side, and a signal line is connected to its source side.

(12) In (10), the read input / output control circuit has a control line for controlling connection to the signal line, and the potential of the signal line and the control line used for the read operation of the input / output control circuit is ,
When the input / output control circuit is not selected, it is set to the same potential,
At the time of selection, the signal line is used as signal detection means, and the control line is changed to another potential different from the potential at the time of non-selection.

(13) In (9), the left and right input / output control circuits are arranged at least twice the data line pair pitch.

(14) In (9), the data line pairs cross each other in the memory cell array.

(15) In (9), a wiring other than the data line is formed between the data line pair of the input / output control circuit and the data line at the same time.

(16) In (9), a function of selecting a plurality of input / output control circuits with one column address at the time of an operation test of a memory is provided to enable a parallel test.

(17) In (16), the control lines of the input / output control circuit for reading are line pairs.

(18) In (16), there is provided a means capable of arbitrarily setting the voltage level of the power supply line on the high voltage side of the sense amplifier, which is means for detecting and amplifying a signal read from the memory cell to the data line.

(19) In the constitution (8), the dynamic memory comprises a memory cell array comprising a data line, a word line, a memory cell and a switch transistor on a chip, and a switch transistor as a minimum operating voltage applied to the data line. An output of a data line power supply for providing a voltage of 1.5 to 2 times the threshold voltage, and a word driver for outputting a required voltage to the word line based on the data line power supply voltage; In a semiconductor integrated circuit in which a word line voltage is applied to a gate of a transistor to take in data from a gate line into a memory cell, the data line power supply voltage is deviated from a data line voltage by a threshold voltage of the switch transistor. A voltage conversion circuit for converting the voltage to a higher voltage, and a static operation which operates using the output of the voltage conversion circuit as a power supply. And a word driver.

(20) In (19), the electric conversion circuit has a configuration of a charge bomb circuit and a rectifier circuit.

(21) In (20), the charge pump circuit includes first, second, third, and fourth MOS transistors and first and second MOS transistors.
, The drains of the second, third and fourth MOS transistors are connected to the power supply, the gate of the second MOS transistor is connected to the source of the fourth MOS transistor, and the third MOS transistor
The source of the transistor is connected to the source of the second MOS transistor, the gates of the third and fourth MOS transistors are connected to the power supply, and one terminal of the first capacitor is connected to the fourth MOS transistor.
One terminal of the second capacitor is connected to the source of the transistor, and one terminal of the second capacitor is connected to the source of the second MOS transistor. In the charge pump circuit, the drain of the first MOS transistor is connected to the power supply, the source is connected to the source of the fourth MOS transistor, and the gate is connected to the source of the second MOS transistor.

(22) In the rectifier circuit, the rectifier element is constituted by a MOS transistor, and a drain of the MOS transistor is input,
The source is an output, the input is connected to the charge pump circuit according to the above item 3, the source is connected to a circuit for transmitting charges from the output, a capacitor for storing the charges, and a circuit for transmitting the charges to a power supply. When the input voltage is at a high level, one end of the capacitor is set to a high level to make the gate voltage of the MOS transistor equal to or higher than the sum of the input voltage and the threshold voltage of the MOS transistor. When rubbing one end of the capacitor to low level,
The gate voltage of the transistor is set to the power supply voltage.

(23) In (20), the threshold values of the MOS transistors used in the memory cell array, the word driver, and the voltage conversion circuit are set to three types. The threshold value of the memory cell array is the highest, and that of the word driver is intermediate. The conversion circuit is the lowest.

(24) In any one of the constitutions (1) to (4), a voltage dividing circuit for dividing and outputting a voltage between terminals via a transistor connected between voltage terminals, and a bias for applying a bias voltage to a gate of the transistor. A semiconductor device having a complementary push-pull circuit including a circuit and converting a power supply voltage into an intermediate voltage thereof and outputting the intermediate voltage to a load, wherein an input of a reference voltage equal to the intermediate voltage and an output to the same load are output. At least two first and second complementary push-pull circuits connected in parallel, and a push-pull current amplifier circuit that amplifies and outputs a reference current,
The first complementary push-pull circuit includes, in its bias circuit, an input of the reference voltage and a bias voltage source added to the input, and a voltage dividing circuit of the push-pull circuit includes a reference current of the current amplifying circuit. A circuit is formed, and an output terminal of the current amplifying circuit is connected to the bias circuit of the second complementary push-pull circuit.

(25) In (24), the bias voltage of the first and second complementary push-pull circuits is substantially equal to the gate threshold voltage of the transistor of the push-pull circuit to which the voltage is applied.

(26) In (1) or (25), the current amplifier circuit is a current mirror type push amplifier circuit.

(27) In the constitutions (24) to (26), the first and second complementary push-pull circuits are constituted by field effect transistors.

(28) A complementary push-pull circuit including a voltage dividing circuit for dividing and outputting a voltage between terminals via a transistor connected between voltage terminals and a bias circuit for applying a bias voltage to a gate of the transistor. A semiconductor device that converts a power supply voltage to an intermediate voltage and outputs the intermediate voltage to a load; and
At least two first and second complementary push-pull circuits and a tri-state drive circuit that connect outputs in parallel to the same load, and a push-pull current amplifier circuit that amplifies and outputs a reference current, Complementary push-pull circuit has a bias circuit including a manual input of the reference voltage and a bias voltage source to be added to the input, and a voltage dividing circuit of the push-pull circuit includes a reference current circuit of the current amplifying circuit. And the output end of the current amplifier circuit is connected to the second complementary
Connected to a bias circuit of a push-pull circuit, the tristate drive circuit further includes a first determination voltage lower than the input voltage and a second determination voltage higher than the input voltage, and an output voltage Means for charging the output when the output voltage is lower than the first determination voltage, and discharging the output when the output voltage is higher than the second determination voltage.

(29) In (28), the bias voltage of the first and second complementary push-pull circuits is a voltage substantially equal to the gate threshold voltage of the transistor of the pulp-pull circuit to which the voltage is applied.

(30) In (5) or (29), the current amplifier circuit is a current mirror type push-pull amplifier circuit.

(31) In any one of the constitutions (28) to (30), the first and second complementary push-pull circuits are constituted by field effect transistors.

(32) In any one of the constitutions (24) to (31), the input and output voltages are one half of the power supply voltage.

(33) An integrated circuit (LSI) that includes at least a plurality of blocks of the same type and, when in operation, activates one or more blocks selected by a block selection signal
And a means for supplying and driving a voltage by using the block as a load, wherein the driving means for driving the block include first and second driving circuits, and a block provided for each block and in an operating state. One drive circuit includes switching means for connecting a block in a non-operating state to the second drive circuit.

(34) In (33), the integrated circuit is a dynamic memory.

(35) In the above (34), the block includes at least a memory cell array, and the loads include a counter electrode of a memory cell storage capacitor and a data line for transmitting a signal from a memory cell to a signal detection circuit. Including at least lines.

(36) In (35), the drive circuit is a means for generating a half voltage of the power supply voltage.

(37) (36) The drive circuit according to any one of (24) to (32).

〔The invention's effect〕

As described above, the present invention arranges input / output control circuits for connecting data lines and I / O lines alternately on the left and right sides of a memory cell array, and reduces the transfer impedance between the data lines and I / O lines. By adopting a circuit configuration that changes between the reading operation and the writing operation, it is possible to operate stably at high speed even at a low voltage.

Further, the present invention is also suitable for a parallel test, and can greatly reduce the test time.

Furthermore, according to the present invention, the drive transistor of the word line operates at a low gate voltage, so that
Even if the power supply voltage drops, it operates stably as a word driver. Further, the data line voltage VL is always higher than the data line voltage VL by the threshold voltage VT of the switch transistor of the memory cell.
A voltage conversion circuit that operates as a word driver power supply by boosting the voltage to a voltage VCH that is more than one minute higher can raise the gate voltage of the rectifying transistor by more than the threshold voltage than its drain voltage, and also prevent charge backflow. Therefore, the output voltage can be increased to 2VL, which is the logical value of the voltage doubler generation circuit. In addition, by using an oscillation circuit and a timing generation circuit using an RC delay, the delay time between the oscillation frequency and the timing becomes stable with respect to the power supply voltage fluctuation, so that the voltage conversion efficiency can always be kept in the best state. Further, by selecting three kinds of threshold voltages of the transistor, stabilization at low voltage, high speed, and low power consumption can be achieved. Thus, a semiconductor integrated circuit that operates stably even when the power supply voltage is the electromotive force of one battery can be realized.

Further, according to the present invention, in a highly integrated LSI, a circuit configuration for driving a large load capacitance with high voltage accuracy and high speed, or a circuit for driving a large load capacitance at high speed without flowing a large transient current We can provide a method.
For example, in a conventional circuit, the threshold voltage difference between transistors is
In the case where the output voltage fluctuates by about 13% with respect to 0.75V when there is 0.2V, according to the present invention, the voltage accuracy is improved by one digit or more so as to be suppressed to about 1%. High-speed response is obtained so that the subsequent rise time of the output voltage is improved by about one digit or more compared to the conventional circuit.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, FIG. 2 is a diagram showing the effect of the present invention, and FIG. 3 is a diagram showing an embodiment in which the effect of using FIG. 1 is further enhanced. FIG. 4 is a diagram showing an embodiment in which a plurality of memory cell arrays are present, FIG. 5 is a diagram showing an embodiment of a parallel test, and FIG. 6 is an embodiment for writing an arbitrary write voltage to a memory cell. Diagram showing an example,
FIG. 7, FIG. 11, FIG. 13, FIG. 15, and FIG. 16 are embodiments of the present invention, FIG. 8, FIG. 12, and FIG. 7 shows a conventional example and its timing chart. FIG. 17 is a diagram showing the effect of the embodiment of FIG. 11, FIG. 18 (a) is an embodiment illustrating the basic concept of the present invention, and FIG. 18 (b) is a description of the transitional operation. Figure, No.
FIG. 19 is a conventional example of a DRAM intermediate voltage generating circuit, and FIG.
FIG. 20 (b) and FIG. 20 (c) are diagrams for explaining the effect of the present invention, and FIG. 21 (a) is a diagram showing a specific embodiment in which the present invention is applied to an intermediate voltage generating circuit of a DRAM. FIG. 21 (b) is a diagram for explaining its operation, and FIG. 22 (a) is a specific embodiment in which it is applied to a DRAM intermediate voltage generating circuit. FIG. 23 (b) is a diagram for explaining the effect, FIG. 23 (a) is a diagram for explaining a specific embodiment in which another basic concept of the present invention is applied to an intermediate voltage driving method for a DRAM,
FIG. 23 (b) is a diagram for explaining a change in the intermediate voltage in the embodiment of FIG. 23 (a) when the power supply voltage fluctuates during the memory operation. MA: Memory cell array, CKT: Input / output control circuit, RG
0, RG1 …… Read gate, WG0, WG1 …… Write gate, SA0, SA1 …… Sense amplifier, SWR0, SWR1 …… Read switch, SWW0, SWW1… Write switch, RO, ▲ ▼ …… Read line , WI, ▲ ▼: Write I / O line, dy: Data line pitch, WD: Word driver, XD: X decoder, VLG: Voltage conversion circuit for memory array, VCHG: Voltage conversion for word line Circuit, W: Word line, P: Precharge signal, FX: Word line drive pulse generation circuit, φX: Word line drive pulse, CP: Charge pump circuit, RECT: Rectifier circuit, VL: Data Line voltage or internal (array) power supply voltage, VCH …… Word line voltage conversion circuit output voltage, φ, PA, ▲ ▼, PB, ▲ …… Word line voltage conversion circuit boost pulse, OSC …… Ring oscillator output pulse, C, C1, C2, C3, C4, CA, CB, CD… Capacitor, R, R1, R2 ...... resistance, QD1, QP, Q9, Q10 ...... P-channel MOS transistor, QT, QD2, QS, QD, QA, QB, QC, QP, Q1, Q8, Q11, Q19
… N-channel MOS transistor, I1, I25, I30, I33… Inverter, NA1, NA2… NAND circuit, NO1… NOR circuit, VEXT… External power supply voltage 1, 31, 40… First complementary Push-pull circuit, 2, 32 ... current mirror type push-pull amplifier circuit, 3, 33 ... second complementary push-pull circuit, 30, 50 ... reference voltage generating circuit, 41, 52 ... tri-state buffer , AMP1, AMP2 ... differential amplifier circuit, MB0-MBi ... memory block, 60-62 ... word line selection circuit, 71-73 ... switch, 76, 77 ... intermediate voltage generation circuit (drive circuit) ), MA0: Memory cell array, MC0: Signal amplification and input / output control circuit group, SA0 to SAj: Detection amplification circuit (sense amplifier), IO0 to IOj: Input / output gate, 67: Input / output circuit

──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Hitoshi Tanaka 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Inside Hitachi Ultra-LSE Engineering Co., Ltd. (72) Inventor Yasushi Watanabe Tokyo 5-20-1, Kamimizuhoncho, Kodaira-shi Within Hitachi Ultra-SII Engineering Co., Ltd. ) Inventor, Masanori Isoda 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Ultra-SII Engineering Co., Ltd. (72) Eiji Yamazaki 5--20, Josuihoncho, Kodaira-shi, Tokyo No. 1 Inside Hitachi Ultra-SII Engineering Co., Ltd. (56) References JP-A-1-155589 (JP, A) JP-A 1-98189 (JP, A) JP flat 2-350 (JP, A) (58 ) investigated the field (Int.Cl. ^7, DB name) G11C 11/4091

Claims (7)

(57) [Claims] 1. A semiconductor device having signal amplifying means, wherein said signal amplifying means comprises a first conductivity type first MISFE having a gate coupled to a signal source.
Voltage / current conversion means for converting a voltage signal output from the signal source including T, a signal line for transmitting the first current signal, and the first signal line connected to its source / drain path A second MISFET of the second conductivity type, receiving the first current signal and the reference voltage, outputting a voltage signal, and outputting the second MISFET.
Current / voltage conversion means including a differential amplifier circuit for controlling a gate of T; wherein the semiconductor device has an externally supplied voltage of 2 V or less. A plurality of memory cells provided at intersections of a plurality of data lines and a plurality of word lines; and a plurality of memory cells provided corresponding to each of the plurality of data lines, and a gate connected to the corresponding data line. A plurality of first MISFETs of the first conductivity type, and a plurality of first MISFETs provided for each of the plurality of first MISFETs;
A plurality of first switches each having one end connected to one end of a corresponding source / drain path of the first MISFET; and a first switch commonly connected to the other end of the plurality of first switches.
A signal line; and an amplifier circuit coupled to the signal line, wherein the amplifier circuit has a second conductivity type receiving a first current signal transmitted through the first signal line in a source / drain path thereof.
2MISFET, a first node to which the first signal line is connected, a second node to which a reference voltage is connected, and a differential amplifier circuit including an output node, wherein the gate of the second MISFET is connected to the output node. A semiconductor device, wherein a voltage supplied from the outside is 2 V or less. 3. The semiconductor device according to claim 2, wherein the semiconductor device includes a pair of N-type MISFETs and a pair of P-type MISFETs provided corresponding to each of the plurality of data lines and having a drain and a gate cross-coupled. A plurality of sense amplifiers each including: when reading a signal from the memory cell, before a signal read from the memory cell on the corresponding data line is sufficiently amplified by the sense amplifier, A semiconductor device, wherein one of a plurality of first switches is selected and a read signal is transmitted to the amplifier circuit. 4. The semiconductor device according to claim 2, wherein the semiconductor device is provided corresponding to each of the plurality of data lines, and a plurality of second switches each having one end connected to the corresponding data line. A second switch commonly connected to the other ends of the plurality of second switches;
And a signal line, wherein the first signal line is used for reading signals from the memory cells, and the second signal line is used for writing to the memory cells. 5. The semiconductor device according to claim 3, further comprising a control line commonly connected to the other ends of the source / drain paths of the plurality of first MISFETs. A non-read state, a potential intermediate between the first potential amplified by the sense amplifier and a second potential higher than the first potential; and a read potential, the first potential. 6. The semiconductor device according to claim 2, wherein each of the plurality of memory cells is a dynamic memory cell. 7. The semiconductor device according to claim 1, wherein said first conductivity type is N-type and said second conductivity type is P-type.