JP2006173643A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of reducing crosstalks and performing read and write operations in the same cycle. <P>SOLUTION: A semiconductor storage device has sense global bit lines connected to a sense amplifier, writing global bit lines connected to a write amplifier, and a selection circuit for selectively connecting at least one of the sense global bit lines and the write global bit lines with bit lines. First and second writing global bit lines are arranged between first and second sensing global bit lines, with the first writing global bit line held adjacent to the first sensing global bit line and with the second writing global bit line, held adjacent to the second sensing global bit line. The distance between the first writing global bit line and the first sensing global bit line, or the distance between the second writing global bit line and the second sensing global bit line is set longer than the distance between the first and second writing global bit lines. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device, and more particularly to a technique effective when applied to a cache memory built in a data processing device such as a microprocessor or a microcomputer.

In order to increase the speed of the cache memory, it is desirable that the cache can be written and read simultaneously. For this purpose, Japanese Patent Application No. 9-16223 discloses a configuration in which read / write processing is performed in parallel using two global bit lines.
JP-A-9-16223

    However, the problem of signal crosstalk is derived by operating two global bit lines in parallel. An object of the present invention is to realize high-speed access while avoiding such a problem of crosstalk.

  Another object of the present invention is to propose a layout or structure of a semiconductor memory device suitable for a cache memory capable of realizing high-speed access.

    In order to solve the above problems, a semiconductor memory device according to one aspect of the present invention includes a plurality of word lines, a plurality of bit lines, memory cells connected to the word lines and the bit lines, and a sense amplifier. A sense global bit line connected to the write amplifier, a write global bit line connected to the write amplifier, and a selection circuit for selectively connecting the bit line to at least one of the sense and write global bit lines. is doing.

  The first and second write global bit lines are arranged between the first and second sense global bit lines, and the first write global bit line and the first sense global bit line are arranged. Are adjacent to each other, the second write global bit line and the second sense global bit line are adjacent to each other, and the distance between the first write global bit line and the first sense global bit line, or The distance between the second write global bit line and the second sense global bit line is set larger than the distance between the first and second write global bit lines. With such a configuration, it is possible to reduce the crosstalk between the write and read global bit lines, particularly the influence of the write bit line on the read bit line.

  As a specific device structure, the write global bit line and the sense global bit line are composed of the same wiring layer, and the horizontal distance between the write global bit lines and the horizontal distance between different types of global bits. Assume that the distance in the direction is different. At this time, the first wiring layer constituting the bit line, the second wiring layer constituting the word line, and the third wiring layer constituting the write and sense global bit lines are configured from the substrate side. can do.

  As another example, the write global bit line and the sense global bit line are configured with different wiring layers, and the distance between the write global bit lines and the distance between different types of global bits are different. In this way, the effect of reducing crosstalk can be obtained without changing the pitch between the bit lines.

  Specifically, from the substrate side, the first wiring layer constituting the bit line, the second wiring layer constituting the word line, the third wiring layer constituting the sense global bit line, and the write global bit line A semiconductor memory device having a fourth wiring layer that constitutes the semiconductor device can be obtained.

  Further, it is also preferable to provide a portion where the first write global bit line and the second write global bit line intersect. That is, when the first write global bit line and the second write global bit line cross each other, the positions thereof are periodically switched. With such a configuration, the influence of the write global bit line can be further reduced.

  Another aspect of the present invention provides a plurality of word lines, a plurality of bit lines, memory cells connected to the word lines and the bit lines, a sense global bit line connected to the sense amplifier, and a write amplifier. A portion having a write global bit line to be connected and a selection circuit for selectively connecting the bit line to at least one of the sense and write global bit lines, and two adjacent write global bit lines intersecting each other Have

  Here, two adjacent write global bit lines may be disposed between two sense global bit lines. Furthermore, it is desirable that the shortest distance between the write global bit lines is larger than the shortest distance between the write global bit line and the sense global bit line.

  As a specific circuit layout, a plurality of word lines, a plurality of bit lines, and memory cells connected to the word lines and the bit lines constitute a rectangular first region, and extend along one side of the first region. A second rectangular region in which the selection circuit is disposed, and the sense global bit line and the write global bit line cross the first and second regions in a direction perpendicular to the one side. Can be configured to.

  Then, it may be configured such that two write global bit lines intersect in the second region. A plurality of sets of first and second regions may be arranged along the extending direction of the sense global bit line and the write global bit line to constitute a memory bank column. Furthermore, a third region having a sense amplifier and a write amplifier may be provided at one end of the memory bank column. Further, two memory bank columns may be arranged in parallel, and a decoder and a word driver may be arranged between them.

  The overall layout of the semiconductor memory device proposed by the present invention is that a plurality of word lines, a plurality of bit lines, and memory cells connected to the word lines and the bit lines constitute a rectangular first region. , A sense global bit line connected to the sense amplifier, a write global bit line connected to the write amplifier, and a selection circuit for selectively connecting the bit line to at least one of the sense and write global bit lines Have

  Then, a rectangular second area in which the selection circuit is arranged along one side of the first area is arranged, and the sense global bit line and the write global bit line are arranged in a direction perpendicular to the one side. Cross the first and second regions. Further, a plurality of pairs of first and second regions are arranged along the extending direction of the sense global bit line and the write global bit line to form a memory bank column, and a sense amplifier is provided at one end of the memory bank column. And a third region having a write amplifier.

  Specifically, the sense amplifier is desirably arranged closer to the memory bank column than the write amplifier. This is because the sense amplifier handles weak signals. The sense amplifier is composed of the first, middle and subsequent sense amplifiers from the side closer to the memory bank column, and the gate length of the transistors constituting the first stage is set to be larger than the gate length of the transistors constituting the first and second stages. Good. From the process aspect, a dummy transistor that does not operate may be included in the transistors constituting the first stage.

  In the transistor constituting the middle stage or the latter stage, the source, gate, and drain may be arranged in the extending direction of the sense global bit line and the write global bit line. The selection circuit may include a read selection switch and a write selection switch, and the read selection switch may be arranged closer to the first region than the write selection switch.

  In addition to this, two write global bit lines are arranged in parallel, and if the left and right positions are periodically crossed, the influence of the write global bit line on the sense global bit line is reduced. Can be reduced. At this time, it is preferable that the write global bit lines cross in the second region.

  Further, when the location where the write global bit line crosses in one second region is closer to the first region than the selection circuit, the location where the write global bit line crosses in the other second region adjacent thereto Are alternately arranged so as to be farther to the first region than the selection circuit, the right and left positional relationship of the two global bit lines is the same in any memory bank column, so that the design and manufacture are easy. Become.

  High speed access can be realized while avoiding the problem of crosstalk.

  Several preferred embodiments of the semiconductor memory device according to the present invention will be described below with reference to the drawings.

<Example 1>
FIG. 1 is a circuit diagram showing an embodiment of a semiconductor memory device according to the present invention. The semiconductor memory device 100 is formed on a single semiconductor substrate such as single crystal silicon by using a semiconductor integrated circuit manufacturing technique. A plurality of memory cells CELL are arranged in a matrix (matrix) to form a memory array. The memory array is divided into n banks (BANK1 to BANKn).

   Here, PC1 to PCn are precharge circuits, YSW1 to YSWn are Y switches, SA is a sense amplifier shared by each bank, WA is a write amplifier shared by each bank, and RPC is a global bit line precharge circuit for reading. , WPC is a write global bit line precharge circuit, READ DATA is read data, WRITE DATA is write data, WGBL and WGBLB are write global bit lines, RGBL and RGBLB are read global bit lines, LBL0, LBLB0, LBL1, LBLB1, LBL2, LBLB2, LBL3, and LBLB3 are local bit lines, and 101 is a decoder and a word driver.

  FIG. 2 shows the configuration of the memory cell CELL in FIG. 1 in detail. The memory cell CELL has a flip-flop (consisting of P-channel MOS transistors MP01 and MP02, N-channel transistors MN01 and MN02) configured by connecting the input and output of a pair of CMOS inverters to each other, and N-channel MOS transistors MN03 and MN04 that selectively connect the flip-flop node N and node NB to local bit lines (LBL0 and LBLB0). A word line WL is connected to the gates of the N-channel MOS transistors MN03 and MN04.

  FIG. 3 shows in detail the configuration of the precharge circuit PC1 and the Y switch circuit YSW1 in FIG. The local bit lines (LBL0, LBLB0, LBL1, LBLB1, LBL2, LBLB2, LBL3, and LBLB3) that are bit lines in the bank can be precharged to "HIGH" level using the P-channel MOS transistor MP1. Yes. The local bit lines (LBL0, LBLB0, LBL1, LBLB1, LBL2, LBLB2, LBL3, and LBLB3) are connected via P-channel MOS transistors MP13 to MP20 and N-channel MOS transistors MN1 to MN8 with 4 columns as a unit. Thus, it is connected to global bit lines (RGBL, RGBLB, WGBL, WGBLB) formed in parallel with the local bit lines so as to cross the bank.

  The global bit lines are divided into read bit lines (RGBL, RGBLB) and write bit lines (WGBL, WGBLB). A signal line RSW0 is connected to the gates of the P-channel MOS transistors MP13 and MP14. At the time of reading data, the local bit lines (LBL0, LBLB0) are precharged once to the “HIGH” level by the precharge circuit PC1 and only swing around the “HIGH” level. The signals of the lines (LBL0, LBLB0) can be transmitted to the global bit lines (RGBL, RGBLB) for reading data.

  A signal line WSW0 is connected to the gates of the N-channel MOS transistors MN1 and MN2. When writing data, it is necessary to accurately transmit the “LOW” level signal of the global bit lines (WGBL, WGBLB) for data writing to the local bit lines (LBL0, LBLB0), but the “HIGH” level signal is Since there is no problem even if the level is slightly lowered, it is only necessary to connect the local bit lines (LBL0, LBLB0) and the global bit lines for data writing (WGBL, WGBLB) with only N-channel MOS transistors. Data read global bit lines (RGBL, RGBLB) are connected to local bit lines via Y switches (YSW1 to YSWn), and are connected to the read global bit line precharge circuit RPC and the sense amplifier / latch circuit SA. Connected.

  FIG. 4 shows in detail the configuration of the read global bit line precharge circuit RPC and the sense amplifier / latch circuit SA in FIG. The read global bit line precharge circuit RPC includes P-channel MOS transistors MP21, MP22, and MP23, and can read the read global bit lines (RGBL, RGBLB) to the “HIGH” level. The sense amplifier / latch circuit SA includes differential sense amplifiers (first stage) composed of P-channel MOS transistors MP24 and MP25 and N-channel MOS transistors MN9, MN10, MN11, MN12, and MN13, MP26, MP27, MN14, and MN15. , MN16, MN17, MN18 differential sense amplifier (middle stage), MP28, MP29 and MN19, MN20, MN21, MN22, MN23 differential sense amplifier (rear stage), latch circuit composed of two NAND circuits It is composed of an LT and an output buffer BUF. Global bit lines (RGBL, RGBLB) are connected to the gates of the N-channel MOS transistors MN9, MN10. The ground potential VSS is connected to the gates of the P-channel MOS transistors MP24 and MP25. The read data READ DATA is output to the outside from the output buffer BUF.

  The global bit lines (WGBL, WGBLB) for data writing are connected to the local bit lines via the N-channel MOS transistors of the Y switches (YSW1 to YSWn), and the write global bit line precharge circuit WPC, write Connected to the amplifier circuit WA.

  FIG. 5 shows the configuration of the write global bit line precharge circuit WPC and the write amplifier circuit WA in FIG. 1 in detail. The write global bit line precharge circuit WPC includes P-channel MOS transistors MP30, MP31, and MP32, and can precharge the write global bit lines (WGBL, WGBLB) to "HIGH" level. The write amplifier circuit WA includes inverter circuits INV1, INV2, INV3, MN24, and MN25. The write data WRITE DATA is output to the write global bit lines (WGBL, WGBLB) via INV1, INV2, INV3 and MN24, MN25.

  As shown in FIG. 6, INV1 and INV3 can be replaced with MN26 and MN27. At this time, when WT_EN becomes “HIGH” level, either WGBL or WGBLB is set to “LOW” level, and the other is kept at the precharge level (ie, “HIGH” level). Write to the cell. The decoder and word driver 101 is a circuit that selects one word line of any one bank.

  FIG. 7 shows operation waveforms in continuous operation of reading and writing to the same address of the semiconductor memory device of FIG. First, data is read and then data is written.

  Before starting the operation, read global bit lines (RGBL, RGBLB), local bit lines (LBL0, LBLB0, LBL1, LBLB1, LBL2, LBLB2, LBL3, LBLB3) and write global bit lines (WGBL, WGBLB) The signal lines REQ (see FIG. 3) and EQ and WEQ (see FIG. 5) are set to “L” (“LOW” level), so that the precharge circuits RPC, PC and WEQ make “H” (“HIGH”). Level). Also, the read global bit lines (RGBL, RGBLB) and the local bit lines (LBL0, LBLB0) are connected by setting the control signal RSW0 of the Y switch YSW1 to “L” and setting the RSW1, RSW2, RSW3 to “H”. Keep it.

  In the read operation, first, the signal lines REQ and EQ are set to “H”, the precharge is stopped, and at the same time, the word line WL is set to “H”, and the precharged local bit lines (LBL0 and LBLB0) are stored in the memory. The cell CELL is discharged and a potential difference is generated. Since the local bit lines (LBL0, LBLB0) and the read global bit lines (RGBL, RGBLB) are connected, the potential difference between the local bit lines (LBL0, LBLB0) generated by the memory cell CELL is the read global bit line ( RGBL, RGBLB). Further, this potential difference is transmitted to the sense amplifier / latch circuit SA, amplified by setting the sense amplifier activation signal SA_EN (see FIG. 4) to “H”, and data is output to the signal line READ DATA.

  When the potential difference is transmitted to the sense amplifier, the control signal RSW0 of the Y switch YSW1 is changed from "L" to "H", the P channel type MOS transistor of the Y switch YSW1 is turned off, and the local bit lines (LBL0, LBLB0) ) And the read global bit lines (RGBL, RGBLB) are separated. At the same time, the control signal WSW0 of the Y switch YSW1 is changed from “L” to “H”, the N channel type MOS transistor of the Y switch YSW1 is turned on, the local bit lines (LBL0, LBLB0) and the write global bit line (WGBL). , WGBLB) and the write operation is started. Since the write global bit lines (WGBL, WGBLB) have been charged / discharged in advance by setting the write amplifier activation signal WT_EN (see FIG. 5) to “H” during the read operation, the write operation has started. If only the small-capacity local bit lines (LBL0, LBLB0) are charged / discharged, a signal is transmitted to the memory cell CELL, and writing is completed.

  After writing, the word line WL is set to “L”, the control signal RSW0 is set to “L”, the control signal WSW0 is set to “L”, and the signal lines REQ, EQ, and WEQ are set to “L” for the next cycle. Read global bit lines (RGBL, RGBLB), local bit lines (LBL0, LBLB0, LBL1, LBLB1, LBL2, LBLB2, LBL3, LBLB3) and write global bit lines (WGBL, WGBLB) are precharged. Reading, writing, and precharging are executed in one cycle.

  In FIG. 7, it is described that the precharge is performed at the end of one cycle, but the precharge may be performed before the reading. That is, it is the same as that described to precharge at the beginning of one cycle.

  In this embodiment, the memory cell CELL attached to the bit line during operation has only 1 / n as compared with the method not using the global bit line, so that the capacity of the bit line is reduced and the charge / discharge speed is increased. As a result, there is an effect that reading and writing operations are speeded up. Power consumption can also be reduced by reducing the capacity of the bit line.

  FIG. 8 shows a layout of the metal layer of the memory mat portion of the semiconductor memory device of FIG. Data read global bit lines (RGBL, RGBLB) and data write global bit lines (WGBL, WGBLB) are connected to four pairs of local bit lines (LBL0, LBLB0, LBL1, LBLB1, LBL2, LBLB2, LBL3, LBLB3). They are wired at a ratio of one pair.

  FIG. 9 shows a cross-sectional view taken along the broken line AB in FIG. The local bit lines (LBL0, LBLB0, LBL1, LBLB1, LBL2, LBLB2, LBL3, LBLB3) are configured using a second layer of metal (metal wiring). The reinforcement line WLG for reducing the resistance of the word line is configured using a third layer metal. The ground line VSS and the power supply line VDD are configured using a third layer metal. The read global bit lines (RGBL, RGBLB) are configured using a fourth layer of metal. The write global bit lines (WGBL, WGBLB) are configured using a fifth layer metal. Although not shown, the first layer metal is used in the memory cell portion. A region surrounded by a thick line represents one memory cell CELL.

  Since the global bit lines (RGBL, RGBLB, WGBL, WGBLB) are formed at a ratio of one to one column of memory cells (for example, a pair of bit lines (LBL0, LBLB0)), the global bit lines (RGBL, RGBLB) are formed. , WGBL, WGBLB) can be reduced to increase the operation speed.

  FIG. 10 shows a layout and a cross-sectional view of the case where the write global bit lines (WGBL, WGBLB) are configured using the fourth layer metal. In this case, since the read global bit lines (RGBL, RGBLB) and the write global bit lines (WGBL, WGBLB) are the same metal layer, the inter-wiring capacitance Cn0 takes a large value.

  FIG. 11 shows operation waveforms when the inter-wiring capacitance Cn0 between the read global bit lines (RGBL, RGBLB) and the write global bit lines (WGBL, WGBLB) is large. The write global bit lines (WGBL, WGBLB) are charged and discharged in advance during the read operation. At this time, since the inter-wiring capacitance Cn0 is large, the crosstalk of the write data causes the read global bit lines (RGBL, RGBLB). Occurs against.

  The read global bit lines (RGBL, RGBLB) transmit a weak voltage amplitude from the memory cell, and the write global bit lines (WGBL, WGBLB) transmit write data having the same amplitude as the power supply voltage. Therefore, when crosstalk occurs, the data on the read global bit lines (RGBL, RGBLB) is easily broken, and as a result, erroneous data is output.

  On the other hand, in FIGS. 8 and 9, since the wiring layers of the read global bit lines (RGBL, RGBLB) and the write global bit lines (WGBL, WGBLB) are changed, the interwiring capacitance Cn2 is smaller than Cn0, and the write data Crosstalk can be suppressed.

  FIG. 12 shows a layout and a cross-section when the read global bit lines (RGBL, RGBLB) and the write global bit lines (WGBL, WGBLB) are formed using the fourth layer metal, and the wiring pitch between them is changed. The figure is shown. Also in this case, since the inter-wiring capacitance Cn1 between the read global bit line (RGBL, RGBLB) and the write global bit line (WGBL, WGBLB) can be made smaller than Cn0, crosstalk of write data can be suppressed. . Further, in the embodiments of FIGS. 8, 9, and 12, the inter-wiring capacitances Cn2 and Cn1 are reduced, so that the operation of the global bit line can be speeded up and the power consumption can be reduced.

  8, 9 and 12, the write global bit lines (WGBL, WGBLB) are formed between the read global bit lines (RGBL, RGBLB), thereby having the same amplitude as the power supply voltage. Write data prevents crosstalk from occurring in an adjacent global bit line (not shown). In general, crosstalk causes unnecessary potential change (glitch), and thus wasteful power is consumed. Therefore, in this embodiment, low power consumption can be achieved at the same time.

  In the embodiments of FIGS. 8 and 9, it is also important that the write global bit lines (WGBL, WGBLB) are formed using the fifth layer metal. Crosstalk between the read global bit lines (RGBL, RGBLB) and the write global bit lines (WGBL, WGBLB) is a write out of parasitic capacitances (for example, Cd0 and Cn2) of the read global bit lines (RGBL, RGBLB). This occurs when the value of the capacitance (Cn2) to the global bit line (WGBL, WGBLB) for use is not negligible.

  If the read global bit lines (RGBL, RGBLB) are configured using the fifth layer metal, the capacitance between the lines corresponding to Cd0 in FIG. 9 becomes a small value and Cn2 looks relatively large. Data crosstalk will occur. From the viewpoint of data transmission between the memory cell and the global bit line, the read global bit line (RGBL, RGBLB) having the purpose of transmitting a weak signal from the memory cell uses a lower layer metal. There is a need to. This is because, in order to connect to the upper metal layer, the via (metal contact) must be passed many times, so the resistance value and parasitic capacitance decrease the operating speed and increase the power consumption. It is.

  FIG. 13 shows a layout image of a memory configured using this circuit technology. The area 110 is a memory array, which is roughly divided into two, and each memory array is divided into eight banks (BANK1 to BANK8). A region 111 is a precharge circuit PCi and a Y switch YSWi (i = 1 to 8), and is arranged adjacent to eight banks (BANK1 to BANK8). In the region 113, a decoder and word driver 101 are arranged.

  In the region 112, a read global bit line precharge circuit RPC, a sense amplifier / latch circuit SA, a write global bit line precharge circuit WPC, and a write amplifier circuit WA are arranged. For simplicity, only one set of read global bit lines (RGBL, RGBLB) and write global bit lines (WGBL, WGBLB) are shown. The write global bit lines (WGBL, WGBLB) are twisted in layout on the region 111. When the write global bit lines (WGBL, WGBLB) are not twisted, the read global bit line RGBL and the write global bit line WGBL run in parallel for a long distance, so that the capacitance between the wirings increases.

  As shown in FIG. 7, since the write global bit lines (WGBL, WGBLB) are charged / discharged in advance during the read operation, if the interwiring capacitance with one of the read global bit lines is large, the write data The effect of crosstalk will increase. In order to prevent this, the write global bit lines (WGBL, WGBLB) may be laid out so as to run in parallel by the same length as both of the read global bit lines (RGBL, RGBLB).

  FIG. 14 shows a layout of a portion where the write global bit lines (WGBL, WGBLB) are twisted and the left and right are switched. In this figure, the WGBLB of the fifth layer metal is arranged on the lower right side of the center, and once the layout is switched to the fourth layer metal and wired to the left channel, the layout is switched to the fifth layer metal again. It is shown. In the twist portion that appears next, the same layout as that of FIG. 14 can be used only by arranging the WGBL of the fifth layer metal on the lower right side of the center.

  FIG. 15 shows the layout image of the area 112 in FIG. 13 and the area 111 placed adjacent thereto in more detail. The upper side of FIG. 15 corresponds to the memory array side indicated as BANK8 in FIG. Local bit line precharge circuit PC8, Y switch YSW8, read global bit line precharge circuit RPC, sense amplifier SA, latch circuit LT, write global bit line precharge circuit WPC, write amplifier WA, output buffer BUF in order from the top Is laid out. Here, since the local bit line is connected to the local bit line precharge circuit PC8 and the Y switch YSW8, it must be placed adjacent to the memory array. Further, the read global bit line precharge circuit RPC, the sense amplifier SA, and the latch circuit LT (hereinafter RPC, SA, and LT are collectively referred to as a sense amplifier unit) handle a signal having a weak amplitude on the read global bit line. Therefore, it is arranged on the side close to the memory array.

  Conversely, the write global bit line precharge circuit WPC and the write amplifier WA (hereinafter, WPC and WA are collectively referred to as a write amplifier unit) are arranged on the side farther from the memory array than the sense amplifier unit. This is because the write amplifier unit handles write data having the same amplitude as the power supply voltage, and there is a risk of adverse effects such as noise on the sense amplifier unit. Since the read data also has the same amplitude as the power supply voltage after the latch circuit LT of the sense amplifier section, the output buffer is placed at the very end of the layout. In this way, the output signal wiring connected to the tip of the output buffer can be shortened.

  FIG. 16 is a transistor level layout diagram of local bit line precharge circuit PC8 and Y switch YSW8 in FIG. In this figure, only one set of global bit lines (four sets of local bit lines) is shown for simplicity. FG is polysilicon forming a gate electrode of the transistor, L is a diffusion layer, CONT is a diffusion layer, or a contact hole for connecting the polysilicon and the first layer metal. The P channel type MOS transistor and the N channel type MOS transistor constituting the YSW 8 are arranged so that the gate width direction of each transistor is horizontal.

  FIG. 17 shows an example in which the gate width direction of the transistors constituting the Y switch is arranged vertically. Whether the layout of FIG. 16 or the layout of FIG. 17 is used may be set such that the vertical length of the layout of the Y switch portion becomes smaller depending on the gate width size of the transistors constituting the Y switch.

  FIG. 18 shows a transistor level layout of the sense amplifier SA. From the top, the first-stage sense amplifier, the middle stage, and the subsequent-stage sense amplifier are arranged in this order. The transistors constituting the first-stage sense amplifier have a gate length larger than that of the transistors constituting the middle-stage and subsequent-stage sense amplifiers. This is to realize high-speed reading by suppressing the offset of the sense amplifier due to manufacturing variations of transistors in the first-stage sense amplifier. Since the weak signal output from the memory cell is input to the first-stage sense amplifier, even a slight offset leads to an increase in read time. Dummy N-channel MOS transistors are arranged above and below the N-channel MOS transistors MN9 and MN10 to which the read global bit line is connected. In this transistor, the source electrode, the drain electrode, and the gate electrode are all connected to the ground potential VSS. Thus, by sandwiching MN9 and MN10 with the dummy transistors, it is possible to suppress variations in gate length during manufacturing and to reduce the sense amplifier offset. In addition, the layout of the sense amplifiers may be arranged at a ratio of one for each of the four sets of local bit lines. Therefore, the sense amplifiers can be arranged in the horizontal direction like the middle stage and the subsequent stage sense amplifiers. In this way, the vertical length of the sense amplifier can be reduced.

  FIG. 19 shows the layout of the metal layer of the first-stage sense amplifier. The power supply line VDD, the ground line VSS, and the sense amplifier activation signal SA_EN are formed of a third layer metal so as to be orthogonal to the read global bit lines (RGBL, RGBLB) formed of the fourth layer metal. In this embodiment, the global bit lines for data reading (RGBL, RGBLB) and the global bit lines for data writing (WGBL, WGBLB) are four sets of local bit lines (LBL0, LBLB0, LBL1, LBLB1, LBL2, LBLB2). , LBL3, and LBLB3), a set ratio may be set for eight sets of local bit lines, or a set ratio for two sets.

<Example 2>
FIG. 20 is a block diagram of a direct-mapped cache memory using the semiconductor memory device according to the present invention described in the first embodiment as a data array of the cache memory. The cache memory 200 is formed on a single semiconductor substrate such as single crystal silicon using a semiconductor integrated circuit manufacturing technique. The cache data array 124 is connected to an address bus 122 having a 12-bit length. Write data is selectively supplied from a 32-bit write data bus 120 or a 32-bit main memory data bus 129, and read data is read from a 32-bit read data bus 121 or a read buffer 128. Output to. Data input / output to / from the cache data array 124 is performed with a 32-bit width.

  The read buffer 128 is used for temporarily storing data read from the cache data array 124, and is configured of a 32-bit width register, for example. The selector 131 selects whether to write data from the write data bus 120 to the cache data array 124 or to write data from the main memory data bus 129. The selector 131 is controlled by a control signal 134. The selector 132 selects whether to output the data 135 read from the cache data array 124 or the data of the read buffer 128 to the main memory data bus 129. The selector 132 is controlled by a control signal 133.

  The cache tag array 123 receives the tag address from the address bus 122 and outputs the address 130 to the comparator 125. The comparator 125 compares the address 130 received from the cache tag array 123 with the physical address 136 received from the address translation buffer TLB of the memory management unit (not shown). If they match, the hit signal 126 is set to “H” (hit). Is sent to the control circuit 127. If they do not match, “L” (miss) is output to the hit signal 126 and sent to the control circuit 127. The control circuit 127 controls the selector 131 and the selector 132 with a control signal 134 and a control signal 133, respectively.

  FIG. 21 shows operation waveforms when an associative write operation is performed on the cache memory 200 of FIG. 20 and a cache miss occurs.

  At the time of associative writing, the address is received from the address bus 122 and the write data is received from the write data bus 120, and the data of the memory cell is read into the recovery buffer 128 and then the data is written into the memory cell. When the associative write operation is completed, the hit signal 126 is also determined, and it is determined whether writing is permitted (hit) or not permitted (miss). When the hit signal 126 is “hit”, the next process can be executed without any problem. However, when the hit signal indicates “miss”, the corresponding entry of the cache data array 124 needs to be written back to the main memory. . In this case, it is necessary to perform the following write-back processing.

  In the write-back process, the selector 132 is controlled to select the data in the read buffer 128 to output the data in the read buffer 128 to the main memory bus and issue a write request to the main memory not shown. To do. However, since the possibility that the normal hit signal 126 indicates “miss” is small, almost no write back processing is required. Therefore, normally, the associative write operation is completed in one cycle.

  Since the conventional associative write operation performs writing after the hit signal is confirmed, it takes two cycles to complete the associative write. However, in this embodiment, half the store processing time is required as compared with the conventional method. That is, the memory access stage of the microprocessor pipeline is only one cycle, and the high-speed performance can be improved without disturbing the pipeline flow.

    The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  In other words, it is possible to reduce the crosstalk of the write data to the read data, to realize a memory in which reading and writing are performed in the same cycle, and a configuration in which a plurality of local bit lines share a set of global bit lines. By taking it, the area can be reduced.

1 is a circuit diagram of a semiconductor memory device according to the present invention. FIG. 2 is a circuit diagram of a cell of the memory device in FIG. 1. FIG. 3 is a circuit diagram of a Y switch and a local bit line precharge circuit when one global bit line is formed for four sets of local bit lines. FIG. 3 is a circuit diagram of a sense amplifier and a read global bit line precharge circuit. The circuit diagram of a write amplifier. The circuit diagram of the modification of a write amplifier. FIG. 2 is an operation waveform diagram of the embodiment of FIG. The top view of the layout of a memory mat part. Sectional drawing of the layout of a memory mat part. FIG. 5 is a two-side view of a layout of a memory mat portion in which write data crosstalk is likely to occur. FIG. 6 is an operation waveform diagram when read data is destroyed due to crosstalk of write data. The layout two views of a memory mat part. 1 is an overall layout plan view of a storage device to which the present invention is applied. The layout plan view when twisting the bit line. The layout diagram of a sense amplifier part and a write amplifier part. The layout diagram of a Y switch. Another layout diagram of the Y switch. The layout diagram of a sense amplifier. The layout diagram of the first stage sense amplifier. The block diagram showing the cache memory of the other Example of this invention. FIG. 21 is an operation waveform diagram of FIG. 20.

Explanation of symbols

101... Decoder and word driver 110... Memory array 111... Precharge circuit, Y switch circuit 112... Sense amplifier unit, write amplifier unit 113. , LBL 3, LBLB 3 ...... Local bit line 120 ...... Write data bus 121 ...... Read data bus 122 ...... Address bus 123 ...... Cache tag array 124 ...... Cache data array 125 ...... Comparator 126 ...... Hit signal 127 ... Control circuit 128 ... Read buffer 129 ... Main memory bus 130 ... Output from the cache tag array 131 ... Write data selector 132 to the cache data array ... ... to the main memory bus Force data selector 133... Selector 132 control signal 134... Selector 131 control signal 135... Read data 136 from the cache data array... Physical address WGBL, WGBLB .. write global bit lines RGBL, RGBLB. Bit line MN ... N-channel MOS transistor MP ... P-channel MOS transistor INV ... Inverter circuit CELL ... Memory cell WL ... Word line N, NB ... Memory cell storage nodes EQ, REQ, WEQ ... Pre Charge circuit control signals RSW0, RSW1, RSW2, RSW3... Signals SWW0, WSW1, WSW2, WSW3... For controlling YSW P-type MOS transistors. Kn ... Bank PC1, PCn ... Precharge circuit YSW1, YSWn ... Y switch SA ... Sense amplifier SA_EN ... Sense amplifier activation signal WA ... Write amplifier WT_EN ... Write amplifier activation signal RPC ... For reading Global bit line precharge circuit WPC …… Write global bit line precharge circuit WLG …… Word line reinforcement line VSS …… Ground line VDD …… Power supply line READ DATA …… Read data WRITE DATA …… Write data.

Claims (9)

Sense global bit line connected to the sense amplifier,
A write global bit line connected to the write amplifier;
A rectangular first region having a plurality of word lines, a plurality of bit lines, and memory cells connected to the word lines and the bit lines;
A rectangular second region in which a selection circuit for selectively connecting at least one of the sense and write global bit lines and the bit line is disposed;
The first area and the second area as one set, and a memory bank having a plurality of the sets;
In a semiconductor memory device having a third region having the sense amplifier and the write amplifier,
The selection circuit is disposed along a first direction along one side of the first region,
The sense global bit line and the write global bit line cross the first and second regions in a direction orthogonal to the first direction,
The memory bank is disposed along a direction in which the sense global bit line and the write global bit line extend,
The third region is provided at one end of the memory bank column,
A semiconductor memory device in which the sense amplifier is arranged closer to the memory bank column than the write amplifier. The sense amplifier is composed of a sense amplifier circuit in the first stage, the middle stage, and the latter stage from the side close to the memory bank column,
The gate length of the transistors constituting the first stage sense amplifier circuit is:
The semiconductor memory device according to claim 1, wherein the semiconductor memory device has a gate length longer than that of transistors constituting the middle-stage and subsequent-stage sense amplifier circuits. The first stage sense amplifier circuit is:
3. The semiconductor memory device according to claim 2, further comprising a dummy transistor having a gate electrode, a source electrode, and a drain electrode connected to a ground potential.   4. The semiconductor memory device according to claim 2, wherein in the transistor constituting the middle-stage or subsequent-stage sense amplifier circuit, a source, a gate, and a drain are arranged in a direction in which the sense global bit line and the write global bit line extend. The selection circuit includes a selection switch for reading and a selection switch for writing,
5. The semiconductor memory device according to claim 1, wherein the read selection switch is disposed closer to the first region than the write selection switch. 6.   6. The semiconductor memory device according to claim 1, wherein the two write global bit lines are arranged in parallel, and the left and right positions cross periodically.   7. The semiconductor memory device according to claim 6, wherein said write global bit line crosses in said second region. In one set, when the location where the write global bit line crosses is closer to the first region included in the set than the selection circuit of the second region included in the set,
In the second region included in the other set adjacent to the one set, the location where the write global bit line crosses is included in the set by the selection circuit in the second region included in the set. The semiconductor memory device according to claim 7, wherein the semiconductor memory device is configured to be far from the first region. A global bit line for writing,
A global bit line for reading,
A first region having a plurality of word lines, a plurality of bit lines, and memory cells connected to the word lines and the bit lines;
A second region having a selection circuit for connecting the write global bit line, the read global bit line, and the plurality of bit lines;
The first area and the second area as one set, and a memory bank having a plurality of the sets;
In a semiconductor memory device having a third region including a write amplifier connected to the write global bit line and a sense amplifier connected to the read global bit line,
The write global bit line and the read global bit line cross the memory bank along a first direction in which the bit line extends,
The third region is disposed at an end of the memory bank that intersects the first direction,
The sense amplifier amplifies information from the memory cell,
A semiconductor memory device in which the write global line and the read global line overlap in operating periods.