JPH05274883A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To speed up operation by arranging and connecting bit line load circuits on the center of plural memory cells or bit lines. CONSTITUTION:The bit line load circuits 11, 21 are arranged and connected on the center of plural aligned memory cells, i.e., the center of plural bit lines 1, 2. Resistance from the circuits 11, 21 up to the uppermost part of the bit lines is R/2 and resistance from the circuits 11, 21 up to the lowermost part is also R/2. Thereby the resistance of the bit line influenced by reading is R/2 independently of the selected memory cell. Consequently the voltage drop of the bit lines 1, 2 is reduced to a half as compared with a convensional memory increasing a potential difference in reading data. Since resistance on the endmost part of the bit lines 1, 2 is reduced to a half of a convensional value in the case of charging the disccharged bit lines 1, 2 by the circuits 11, 12, the precharging time can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. In particular, it relates to a bit line load circuit.

[0002]

2. Description of the Related Art A conventional static RAM circuit is shown in FIG.
Shown in. Different word lines X0 are provided for the complementary bit lines 1 and 2.
A plurality of memory cells connected to Xn are connected.
Although only two memory cells at the top and the bottom of the bit line are shown in the figure, the memory cells are actually connected by the number of rows of the memory cell array. In the case of a static RAM of 256 kbit, one bit line has 5
Twelve memory cells are connected on a long aluminum wiring, and the resistance thereof is several hundred Ω and the electrostatic capacitance is several pF. In Figure 5, this resistance is R / 2 at two locations and the capacitance is C /
It is shown divided into three parts, each of which is three. The total values are R and C, respectively. MO between bit lines 1 and 2 and power supply
The SFETs 11 and 21 are bit line load circuits for supplying a voltage to the bit lines. In the static RAM, the data is read by extracting the potential of the bit line, which is determined by the current supply from the load circuit to the bit line and the current flow from the bit line to the memory cell, as the potential difference between the complementary bit lines. Column gates 14 and 24 are for selecting bit lines, and the signal of the bit line selected by Yi is transmitted to the common data lines 3 and 4 and amplified by the sense amplifier.

To write data to a memory cell, complementary bit lines are driven to H level and L level according to the data. In the static RAM, when the node of the memory cell is pulled to the L level, the transistor forming the memory cell causes switching and the state is switched, so that the bit line on the L level side is almost 0 V at the time of writing.
To the voltage of.

[0004]

The current flowing through the memory cell at the time of reading is several hundred μA, and the potential difference of the obtained data is as small as several hundred mV. If the resistance of the bit line is large, the potential difference of the data becomes small accordingly. .. In the conventional semiconductor memory device, since only one set of bit line load circuits is placed at the end of the bit line as shown in FIG. 5, the load circuit 1 is read when the memory cell at the bottom of the bit line is read.
A current flows from 1 and 21 to the memory cell through the total resistance R of the bit line, and the potential difference decreases due to the voltage drop. Further, when the data of a certain memory cell on the same bit line is read and then the reading of another memory cell is continued, if the previous data remains on the bit lines 1 and 2, it takes time to reach the state of the next data. Therefore, before reading data, the bit line must be precharged to a sufficient level through the load circuit so that no potential difference remains. This problem is the same when writing. Especially at the time of writing, since the voltage of the bit line is lowered to near 0 V, precharging requires a longer time. In the conventional circuit of FIG. 5, it took the longest time to precharge the lowermost part of the bit line from 11 through the resistor R.

The present invention has been made in order to solve such a problem and has a high stability at a high speed by obtaining a large potential difference between read data of bit lines and precharging the bit lines in a short time. Static R
The purpose is to provide AM.

[0006]

The above object is to arrange and connect a bit line load circuit for supplying a potential to a bit line to which a plurality of memory cells are connected, in the central portion of the plurality of memory cells or bit lines. This is achieved by arranging and connecting the bit line load circuit in at least two or more different locations of the plurality of memory cells or bit lines.

[0007]

Since the present invention has the above-mentioned structure, the resistance between the bit line load circuit and the memory cell is reduced at the time of reading data, and the voltage drop on the way is reduced, so that a large data potential difference can be obtained. Precharging of the bit line is also performed rapidly from the center or a plurality of locations.

[0008]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a static RAM showing a first embodiment of the present invention. Bit line load circuit 11,
Reference numeral 21 is arranged and connected in the center of the memory cells arranged in a line, that is, in the center of the bit lines 1 and 2. The resistance from the load circuit to the top of the bit line is R / 2, and the resistance to the bottom is R / 2. Therefore, no matter which memory cell is selected, the resistance of the bit line that is affected during reading is R
In the case of the maximum, in the circuit of FIG. 5, it is half as compared with the case where the resistance R is used. For example, assume that the uppermost memory cell is selected and the bit line 1 is in the H level and 2 is in the L level. The current flowing into the memory cell on the H level side is 0, and 1 is held at a voltage lower than the power supply voltage by the threshold voltage of the MOSFET. A current I flows from the load 21 to the memory cell on the bit line 2 side through the resistance R / 2 and the path of the uppermost memory cell. Assuming that the bit line voltage of the memory cell portion is A, the voltage of the central portion of the bit line is A + I · R / 2
become. Also, since no current flows from the center to the bottom,
The voltage of the common data line 4 which is the input of the sense amplifier is also A +
Due to the voltage drop of the bit line at I · R / 2, the data voltage difference is reduced by I · R / 2. Therefore, the voltage drop on the bit line is halved as compared with the conventional case, and the potential difference of the read data can be obtained correspondingly. Next, when the discharged bit line is charged by 11 and 21, the top and bottom of the bit line become the slowest, but this is also the case when reading the memory cell. Since the resistance up to the part is half that of the conventional one, the time required for precharging is shortened. Bit line load circuit 1
The power supply voltage is supplied to the gates of 1 and 21 to precharge the bit lines at all times, but there is also a method of giving a signal to the gates to control. For example, when data is read out, a power supply voltage is applied to make it conductive, and at the time of writing, ground voltage is applied to make it non-conductive.

FIG. 2 is a circuit diagram of the second embodiment of the present invention. In this example, the bit line load circuits are 11, 12 and 21,
There are 22 and there are two on each side, and they are placed apart and connected to each other. 11 and 21 are at the top of the bit line and 12 and 22 are at the bottom. Since the number of load circuits is increased to 2, the current capacity of each load is set to 1
Distribute every two. The resistance of the bit line from the load circuit to the memory cell is maximum at the center, but only R / 2. When reading, half of the current flowing from the load circuit to the central memory cell is 11 or 21 and the other half is 12 or 22. Therefore, the voltage drop of the bit line is the product of I / 2 and R / 2, which is 1 compared to the conventional case.
It decreases to / 4. The bit line precharge is also performed through two loads, resulting in high speed.

FIG. 3 shows a third embodiment of the present invention. The bit line load is applied to the uppermost portions 11 and 21 of the bit line and the central portion 12,
22 and the lowermost portions 13 and 23 are divided into three parts, each of which is divided into three parts. In this case, the current capacity as a load is divided into three. As is apparent from the above two embodiments, both the voltage drop of the bit line and the precharge time at the time of reading are further reduced.

In the second and third embodiments, the current capability of the load circuit of the bit line has been divided evenly, but the current capability of the load circuit is particularly required after the voltage of the bit line has dropped. At the time of precharge, it is sufficient to simply hold the level at the time of reading. In the embodiment of the present invention shown in FIG. 4, the load circuits are separately arranged for precharging and level holding. Reference numerals 11 and 21 are precharge loads, the level of the bit line of which is lowered, and the control signal 5 becomes H level and conducts when rapid charging is performed. 12,
22 mainly acts as a load for holding the level at the time of reading, and the power supply voltage is given to the gate. Therefore 1
The current capabilities of 11 and 21 are set to be larger than those of 2 and 22. At the time of reading, 11 and 21 are non-conductive, and 12 and 22 in the center of the bit line function as a load. Therefore, the resistance from the load to both ends of the bit line is R / 2, and the voltage drop is suppressed. Precharging is also performed through 12 and 22 as well as when 11 and 12 are conducting.

Although the above embodiments have been described based on the N-channel MOSFET as the bit line load circuit, the P-channel MOSFET may be used. P channel M
In the case of OSFET, the level of the gate voltage which conducts only changes by connecting the gate to the bit line or setting it to the ground voltage. Also, regarding the device used, MOSF
The same method can be applied not only to ET but also to a bipolar transistor, MESFET and the like. Further, other semiconductor memory devices such as a dynamic RAM, a ROM, and a PROM have a configuration in which a large number of memory cells are arranged on a bit line and have a common load circuit like the static RAM, and the present invention can be applied. is there.

[0014]

According to the present invention, since a large read voltage can be obtained on the bit line, the data can be amplified quickly and the bit line can be precharged in a short time, so that a high-speed memory device can be realized. Further, since a sufficient data amplitude can be obtained, malfunction due to noise can be prevented.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the semiconductor memory device according to the present invention.

FIG. 3 is a circuit diagram showing a third embodiment of the semiconductor memory device according to the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of a semiconductor memory device according to the present invention.

FIG. 5 is a circuit diagram of a conventional semiconductor memory device.

[Explanation of symbols]

1, 2 bit lines 3, 4 common data lines 11, 12, 13, 21, 22, 23 bit line load circuit MOSFETs 14, 24 column gates

Claims (2)

[Claims] 1. A bit line load circuit for supplying a potential to a bit line to which a plurality of memory cells are connected, the bit line load circuit being arranged and connected in the central portion of the plurality of memory cells or bit lines. A semiconductor memory device characterized by the above. 2. A bit line load circuit for supplying a potential to a bit line to which a plurality of memory cells are connected, the bit line load circuit being provided in at least two or more different locations of the plurality of memory cells or bit lines. A semiconductor memory device characterized in that it is arranged and connected to.