CN116564387B - non flash reading method, device, memory chip and equipment - Google Patents
non flash reading method, device, memory chip and equipment Download PDFInfo
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- CN116564387B CN116564387B CN202310804308.0A CN202310804308A CN116564387B CN 116564387 B CN116564387 B CN 116564387B CN 202310804308 A CN202310804308 A CN 202310804308A CN 116564387 B CN116564387 B CN 116564387B
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- 239000000725 suspension Substances 0.000 claims abstract description 9
- 238000007599 discharging Methods 0.000 claims description 38
- 239000003990 capacitor Substances 0.000 claims description 22
- 230000001960 triggered effect Effects 0.000 claims description 4
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- 230000003071 parasitic effect Effects 0.000 description 4
- 230000009471 action Effects 0.000 description 3
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application relates to the technical field of memory chips, and particularly discloses a non flash reading method, a non flash reading device, a memory chip and non flash reading equipment, wherein the non flash reading method comprises the following steps of: opening the pre-discharge enable to start all the discharge modules, so that all bit lines are discharged to 0 potential; turning off the pre-discharge enable to make all the bit lines in a floating state and floating at 0 potential, and establishing a read voltage to read the stored data of the target memory cell; the method is applied to a memory array in which all bit lines are provided with a discharge module based on the same pre-discharge enabling control switch, so that all bit lines are discharged to 0 potential before the stored data of a memory cell is read by opening the pre-discharge enabling, and then a suspension state is maintained, so that the electric quantity required by establishing the bit line voltage in the process of reading the stored data of a target memory cell is greatly reduced, the time consumed in the process of establishing the bit line voltage is further reduced, and the data reading speed of a nor flash is improved.
Description
Technical Field
The application relates to the technical field of memory chips, in particular to a non flash reading method, a non flash reading device, a memory chip and non flash reading equipment.
Background
When the Nor flash executes the reading operation, corresponding reading voltages are required to be applied to the bit line and the word line where the target memory cell is located, so that the memory data of the target memory cell can be read out through a reading circuit; the implementation mode of the existing bit line connection structure and the existing reading method is limited, and a cap (capacitor charge amount required for voltage establishment) in the bit line voltage establishment process is large, so that the establishment time of the bit line voltage is too long, and the data reading speed of the nor flash is restricted.
In view of the above problems, no effective technical solution is currently available.
Disclosure of Invention
The application aims to provide a method, a device, a memory chip and equipment for reading non-flash, so that the data reading speed of the non-flash is improved by improving the speed of bit line voltage establishment.
In a first aspect, the present application provides a method for reading a nor flash, which is applied to a storage array of the nor flash, where the storage array includes:
a plurality of bit lines, adjacent bit lines are connected through a first capacitor;
each bit line is connected with a discharge module, and the discharge module is based on a pre-discharge enabling control switch;
the discharging module is positioned at one side of the first capacitor close to the bit line power supply end;
the method comprises the following steps:
opening the pre-discharge enable to start all the discharge modules so as to discharge all the bit lines to 0 potential;
the pre-discharge enable is turned off to make all the bit lines in a floating state and float at 0 potential, and a read voltage is established to read the stored data of the target memory cell.
The nor flash reading method is applied to a memory array in which all bit lines are provided with a discharging module based on the same pre-discharging enabling control switch, so that all bit lines are enabled to discharge to 0 potential before the stored data of a memory cell are read by opening the pre-discharging enabling, then a suspension state is maintained, the electric quantity required by establishing the bit line voltage in the process of reading the stored data of a target memory cell is greatly reduced, the time consumed in the process of establishing the bit line voltage is further reduced, and the data reading speed of the nor flash is improved.
The step of turning off the pre-discharge enable to make all the bit lines in a floating state and floating at 0 potential, and establishing a read voltage to read the stored data of the target memory cell includes:
establishing a word line voltage corresponding to a target memory cell;
turning off the pre-discharge enable to make all the bit lines in a floating state and floating at 0 potential;
precharging a bit line where a target memory cell is located;
the stored data of the target memory cell is read based on the read circuit.
In this example, the word line voltage setup process is performed before the pre-discharge enable is turned off, thereby shortening the entire read process so that the timing of the entire read process is reasonable and compact.
According to the nor flash reading method, the time of each opening of the pre-discharge enabling is longer than the duration of the pre-charge in the step of pre-charging the bit line of the target memory cell.
The method of the example sets the duration of each opening of the pre-discharge enable to be longer than the duration of the pre-charge in the pre-charge step of the bit line where the target memory cell is located, and can ensure that the discharge module can completely release the electric quantity on each bit line so as to ensure that the bit line is in a floating state before the bit line voltage is established.
According to the nor flash reading method, the duration of each opening time of the pre-discharge enabling is 1.5-2.5 times of the duration of the pre-charge in the step of pre-charging the bit line where the target memory cell is located.
The step of reading the storage data of the target storage unit based on the reading circuit comprises the following steps:
comparing magnitudes of a conduction current and a reference current generated by a target memory cell at the word line voltage and the bit line voltage based on the read circuit to generate read data;
locking the read data and outputting the read data as the stored data.
In the nor flash reading method, the step of closing the pre-discharge enabling and the step of pre-charging the bit line where the target memory cell is located are triggered and executed simultaneously.
According to the nor flash reading method, the discharging module comprises an MOS tube, the pre-discharging enabling device is connected with the grid electrode of the MOS tube, the drain electrode of the MOS tube is connected with the bit line, and the source electrode of the MOS tube is grounded.
In a second aspect, the present application further provides a nor flash reading device, which is applied to a nor flash storage array, where the storage array includes:
a plurality of bit lines, adjacent bit lines are connected through a first capacitor;
each bit line is connected with a discharge module, and the discharge module is based on a pre-discharge enabling control switch;
the discharging module is positioned at one side of the first capacitor close to the bit line power supply end;
the device comprises:
the discharging module is used for opening the pre-discharging enabling to start all the discharging modules so as to enable all the bit lines to discharge to 0 potential, and is also used for closing the pre-discharging enabling to enable all the bit lines to be in a suspension state and to suspend at 0 potential;
and the reading module is used for establishing a reading voltage to read the storage data of the target storage unit.
The nor flash reading device is applied to a storage array in which all bit lines are provided with a discharge module based on the same pre-discharge enabling control switch, so that all bit lines are enabled to discharge to 0 potential before the stored data of a storage unit are read by opening the pre-discharge enabling, and then a suspension state is maintained, so that the electric quantity required by establishing the bit line voltage in the process of reading the stored data of a target storage unit is greatly reduced, the time consumed in the process of establishing the bit line voltage is further reduced, and the data reading speed of the nor flash is improved.
In a third aspect, the present application further provides a memory chip, where the memory chip includes a control circuit, and the memory chip operates the nor flash reading method provided in the first aspect to read the memory data based on the control circuit.
In a fourth aspect, the present application also provides an electronic device, including a memory chip provided in the third aspect.
As can be seen from the above, the present application provides a nor flash reading method, apparatus, memory chip and device, where the nor flash reading method is applied to a memory array in which all bit lines are provided with a discharge module based on the same pre-discharge enabling control switch, so that all bit lines are discharged to 0 potential before reading the stored data of a memory cell by opening the pre-discharge enabling, and then a suspension state is maintained, thereby greatly reducing the amount of electricity required for establishing the bit line voltage in the process of reading the stored data of a target memory cell, further reducing the time consumed in the process of establishing the bit line voltage, and improving the data reading speed of the nor flash.
Drawings
Fig. 1 is a schematic diagram of a connection structure of bit lines in a memory array to be read according to a nor flash reading method provided by an embodiment of the present application.
Fig. 2 is a flowchart of a nor flash reading method provided by an embodiment of the present application.
Fig. 3 is a timing chart of a nor flash reading method according to an embodiment of the present application.
Fig. 4 is a schematic structural diagram of a nor flash reading device according to an embodiment of the present application.
Fig. 5 is a schematic diagram of a connection structure of bit lines in a nor flash memory array in the prior art.
Fig. 6 is a timing chart of a read method of the nor flash to which the structure shown in fig. 5 belongs.
Reference numerals: NM and MOS tube; C2C, a first capacitance; c2gnd, a second capacitor; 201. a discharge module; 202. and a reading module.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the application, as presented in the figures, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 5, in the connection structure of bit lines in some prior nor flash memory arrays, a discharge module on a bit line is disposed at a side of a filter module far away from a power supply end, and the discharge module is respectively configured with two types of enable to control according to odd-even numbers of the bit lines, wherein the discharge module on an even-numbered bit line is controlled by an even-numbered discharge enable even_dis, the discharge module on an odd-numbered bit line is controlled by an odd-numbered discharge enable odd_dis, and the even-numbered discharge enable even_dis and the odd-numbered discharge enable odd_dis are mutually reverse signals; the capacitance of the bit lines is divided into three categories: the capacitance between the same layer of bit lines, the capacitance between the upper layer of bit lines and the lower layer of bit lines, and the parasitic capacitance of the MOS tube connected with the bit lines, wherein the first two capacitances are equivalent to the capacitance to ground; in fig. 5, C2gnd is a parasitic capacitance to ground (gnd) of the corresponding bit line, and is denoted by a capacitance symbol.
As shown in FIG. 6, the 1-4 phases in the sequence constitute the process of reading the memory data for the memory cells on an odd-numbered bit line, respectively: a word line voltage set up (WL set up) phase, a bit line precharge (bit BL) phase, a data read (sense) phase, a data latch data phase; before entering the word line voltage establishment phase, even discharge enable even_dis is turned on (pulled up to 1, i.e. high level) and odd discharge enable odd_dis is turned off (dropped to 0, i.e. low level), and the read operation continues until the memory cell is finished, and after the read operation is finished, the memory cell jumps (the high-low level state is interchanged) and starts to read the memory data of the memory cell positioned on the next bit line; assuming that the read process is to read data of a memory cell on the bit line BL1, the even discharge enable even_dis of the high level is equivalent to discharging the bit line BL0 and the bit line BL2 to ground and pulling to 0V, and in the process of performing the precharge, cap (capacitance charge amount required for establishing voltage) is 2·c2c+c2gnd (capacitance connected between the filter module and the adjacent bit line needs to be charged, where the capacitance value of the capacitance is represented by a reference symbol of the capacitance), the precharge process (i.e., the bit line voltage establishment process) needs a larger amount of charged electricity, and a longer time is required to establish a stable bit line current, i.e., the establishment speed of the reference current for performing the magnitude comparison in the data read is restricted to determine the read data.
In a first aspect, referring to fig. 1 to fig. 3, some embodiments of the present application provide a nor flash reading method, which is applied to a nor flash memory array, where the memory array includes:
a plurality of bit lines, adjacent bit lines are connected through a first capacitor C2C;
each bit line is connected with a discharge module, and the discharge module controls a switch based on the pre-discharge enable Col_dis;
the discharging module is positioned at one side of the first capacitor C2C close to the bit line power supply end;
the method comprises the following steps:
s1, opening a pre-discharge enabling Col_dis to start all discharge modules, and discharging all bit lines to 0 potential;
s2, turning off the pre-discharge enable Col_dis to enable all bit lines to be in a floating state and to be in a 0 potential, and establishing a read voltage to read the storage data of the target storage unit.
Specifically, the target memory cell is a memory cell to be read for storing data, in the embodiment of the present application, the plurality of bit lines are identical bit lines, and the discharging modules of the identical bit lines all control the switch by the same pre-discharge enable col_dis, that is, trigger the discharging function when the pre-discharge enable col_dis is turned on (output is 1, i.e., high level), and turn off the discharging function when the pre-discharge enable col_dis is turned off (output is 0, i.e., low level); the discharging module is equivalent to the high side of the first capacitor C2C, and can release all electric quantity on the bit line when discharging, including the parasitic capacitance C2gnd of the bit line to the ground and the electric quantity in the first capacitor C2C, and can release the electric leakage of the power supply end of the bit line, and the discharging module positioned on the high side can avoid the electric leakage of the power supply end to affect the discharging of the first capacitor C2C, so as to improve the discharging efficiency and ensure the discharging effect.
More specifically, before formally performing the read operation (before establishing the voltage required for reading), the method according to the embodiment of the present application discharges all the bit lines to 0 potential based on step S1, and turns off the pre-discharge enable to keep all the bit lines in a floating (floating) state and to suspend at 0 potential by step S2, i.e. to make all the first capacitors C2C empty the electric quantity and make all the bit lines reach a floating state; in the process of establishing the read voltage, the bit line in a floating state does not have adverse effect on the word line voltage establishing process, but in the process of establishing the bit line voltage (namely, the bit line pre-charging stage), the bit line where the storage unit for storing data to be read is located and the bit lines adjacent to two sides are in a floating state, so that in the process of establishing the bit line, the first capacitor C2C cannot be charged, the cap established by the bit line voltage is only C2gnd (the capacitance value of the capacitor is represented by the reference symbol of the capacitor, namely, the capacitance of the parasitic capacitor of the bit line to the ground), and compared with the existing read method, the bit line connection structure and the read method of the memory array can reduce the charge amount required in the bit line voltage establishing process, further greatly reduce the time consumed in the bit line voltage establishing process, and further improve the data reading speed of a nor flash.
The nor flash reading method is applied to a storage array in which all bit lines are provided with a discharge module based on the same pre-discharge enabling Col_dis control switch, so that all bit lines are discharged to 0 potential before the stored data of a storage unit are read by opening the pre-discharge enabling Col_dis, and then a suspension state is maintained, so that the electric quantity required by establishing the bit line voltage in the process of reading the stored data of a target storage unit is greatly reduced, the time consumed in the process of establishing the bit line voltage is further reduced, and the data reading speed of the nor flash is improved.
It should be noted that, when the nor flash read method of the embodiment of the present application is applied to a continuous read operation, when a read operation needs to be performed on a memory cell on a next bit line, the step S1 and the step S2 need to be repeatedly performed.
It should be noted that, the step S1 may also be performed before the nor flash receives the read request command, for example, when the nor flash is idle, the step S1 is performed in advance to discharge the bit line to the 0 potential, so as to further improve the reading efficiency.
In some preferred embodiments, the step of turning off the pre-discharge enable col_dis to put all bit lines in a floating state and floating at 0 potential, and establishing a read voltage to read the stored data of the target memory cell includes:
s21, establishing word line voltage corresponding to a target memory cell;
s22, closing the pre-discharge enabling Col_dis to enable all bit lines to be in a floating state and to be in a 0 potential;
s23, precharging a bit line where a target memory cell is located;
s24, reading the storage data of the target storage unit based on the reading circuit.
Specifically, since the discharging module does not have an adverse effect on the word line voltage establishing process, the word line voltage establishing process is performed before step S22, so that the whole reading process is shortened, and the time sequence of the whole reading process is reasonable and compact.
More specifically, step S23 is a bit line voltage establishing process, and thus needs to be performed with the discharge function of the discharge module being ensured to be turned off.
In some preferred embodiments, each turn-on time of the pre-discharge enable col_dis is longer than the pre-charge duration in the pre-charge step for the bit line where the target memory cell is located.
Specifically, the duration of each opening of the pre-discharge enable col_dis is set to be longer than the duration of the pre-charge in the pre-charge step for the bit line where the target memory cell is located, so that the discharge module can be ensured to completely release the electric quantity on each bit line, and the bit line can be ensured to be discharged to 0 potential and be in a floating state before the bit line voltage is established.
In some more preferred embodiments, each turn-on duration of the pre-discharge enable col_dis is 1.5-2.5 times, and preferably 2 times, the duration of the pre-charge in the pre-charge step for the bit line where the target memory cell is located.
In some preferred embodiments, the step of reading the stored data of the target memory cell based on the read circuit includes:
s241, comparing the magnitudes of the conduction current and the reference current generated by the target memory cell under the word line voltage and the bit line voltage based on the read circuit to generate read data;
s242, locking the read data and outputting the locked read data as storage data.
Specifically, a reading circuit (not shown in the drawing), that is, a sense circuit, may adopt a reading circuit structure in the prior art, and in this embodiment of the present application, the reading circuit determines whether the stored data of the target memory cell is data 1 or data 0 according to the established magnitude relationship between the on current and the reference current of the target memory cell output by the word line voltage and the bit line voltage, so as to implement data reading.
More specifically, the Pre-charge bit line voltage in fig. 3 establishes a corresponding precharge enable, sa_latch is a corresponding latch enable for the data latch process.
In some preferred embodiments, as shown in fig. 3, the step of turning off the pre-discharge enable col_dis and the step of pre-charging the bit line where the target memory cell is located are triggered to be performed simultaneously.
Specifically, the simultaneous execution of step S22 and step S23 enables more compact timing of the entire reading process to improve the data reading efficiency of the entire reading method.
In some more preferred embodiments, the step of turning off the pre-discharge enable Col_dis and pre-charging the bit line where the target memory cell is located is triggered based on the same trigger signal or based on the same clock rising edge, thereby ensuring timing synchronization of the two and ensuring that the whole reading process can be performed in order.
In some preferred embodiments, the discharging module includes a MOS tube NM, a pre-discharge enabling Col_dis is connected with a gate of the MOS tube NM, a drain of the MOS tube NM is connected with a bit line, and a source of the MOS tube NM is grounded.
Specifically, in this embodiment, the MOS transistor is preferably an NMOS transistor, so that when the pre-discharge enable col_dis is turned on, the NMOS transistor is turned on to discharge the bit line through the NMOS transistor ground.
In some other embodiments, the MOS transistor may further be a PMOS transistor, the pre-discharge module further includes an inverter, the pre-discharge enable col_dis is connected to a gate of the PMOS transistor through the inverter, a source of the PMOS transistor is connected to a bit line, and a drain of the PMOS transistor is grounded; this embodiment enables the PMOS transistor to be turned on to discharge the bit line through the PMOS transistor ground when the pre-discharge enable col_dis is turned on.
In a second aspect, referring to fig. 4, some embodiments of the present application further provide a nor flash reading device, which is applied to a nor flash memory array, where the memory array includes:
a plurality of bit lines, adjacent bit lines are connected through a first capacitor C2C;
each bit line is connected with a discharge module, and the discharge module controls a switch based on the pre-discharge enable Col_dis;
the discharging module is positioned at one side of the first capacitor C2C close to the bit line power supply end;
the method comprises the following steps:
a discharging module 201 for turning on the pre-discharge enable col_dis to turn on all the discharging modules to discharge all the bit lines to 0 potential, and for turning off the pre-discharge enable to make all the bit lines in a floating state and floating at 0 potential;
the read module 202 is configured to establish a read voltage to read the storage data of the target storage unit.
The nor flash reading device is applied to a storage array in which all bit lines are provided with a discharge module based on the same pre-discharge enabling Col_dis control switch, so that all bit lines are discharged to 0 potential before the stored data of a storage unit are read by opening the pre-discharge enabling Col_dis, and then a suspension state is maintained, so that the electric quantity required by establishing the bit line voltage in the process of reading the stored data of a target storage unit is greatly reduced, the time consumed in the process of establishing the bit line voltage is further reduced, and the data reading speed of the nor flash is improved.
In some preferred embodiments, the nor flash reading device according to the embodiment of the present application is configured to perform the nor flash reading method provided in the first aspect.
In a third aspect, some embodiments of the present application further provide a memory chip, where the memory chip includes a control circuit, and the memory chip operates the nor flash read method according to the first aspect to read the stored data based on the control circuit.
In a fourth aspect, some embodiments of the present application also provide an electronic device including a memory chip as provided in the third aspect.
In summary, the embodiment of the application provides a nor flash reading method, a device, a memory chip and equipment, wherein the nor flash reading method is applied to a memory array in which all bit lines are provided with a discharge module based on the same pre-discharge enabling Col_dis control switch, so that all bit lines are discharged to 0 potential before the stored data of a memory cell are read by opening the pre-discharge enabling Col_dis, and then a suspension state is maintained, thereby greatly reducing the electric quantity required by establishing the bit line voltage in the process of reading the stored data of a target memory cell, further reducing the time consumed in the process of establishing the bit line voltage, and improving the data reading speed of the nor flash.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. The above-described apparatus embodiments are merely illustrative, for example, the division of the units is merely a logical function division, and there may be other manners of division in actual implementation, and for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some communication interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form.
Further, the units described as separate units may or may not be physically separate, and units displayed as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Furthermore, functional modules in various embodiments of the present application may be integrated together to form a single portion, or each module may exist alone, or two or more modules may be integrated to form a single portion.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and variations will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the protection scope of the present application.
Claims (9)
1. A nor flash reading method is applied to a nor flash memory array, and is characterized in that the memory array comprises:
a plurality of bit lines, adjacent bit lines are connected through a first capacitor;
each bit line is connected with a discharge module, and the discharge module is based on a pre-discharge enabling control switch;
the discharging module is positioned at one side of the first capacitor close to the bit line power supply end;
the method comprises the following steps:
opening the pre-discharge enable to start all the discharge modules so as to discharge all the bit lines to 0 potential;
turning off the pre-discharge enable to enable all bit lines to be in a floating state and to be in a 0 potential, and establishing a read voltage to read the stored data of the target memory cell;
the turning off the pre-discharge enable to make all the bit lines in a floating state and floating at 0 potential, and establishing a read voltage to read the stored data of the target memory cell includes:
establishing a word line voltage corresponding to a target memory cell;
turning off the pre-discharge enable to make all the bit lines in a floating state and floating at 0 potential;
precharging a bit line where a target memory cell is located;
the stored data of the target memory cell is read based on the read circuit.
2. The nor flash read method of claim 1 wherein each turn-on time of the precharge enable is longer than a precharge duration in the step of precharging the bit line where the target memory cell is located.
3. The nor flash read method according to claim 2, wherein each turn-on duration of the precharge enable is 1.5-2.5 times the precharge duration in the step of precharging the bit line where the target memory cell is located.
4. The nor flash read method according to claim 1, wherein the step of reading the stored data of the target memory cell based on the read circuit includes:
comparing magnitudes of a conduction current and a reference current generated by a target memory cell at the word line voltage and the bit line voltage based on the read circuit to generate read data;
locking the read data and outputting the read data as the stored data.
5. The nor flash read method of claim 1 wherein the step of turning off the pre-discharge enable and the step of pre-charging the bit line where the target memory cell is located are triggered to be performed simultaneously.
6. The nor flash reading method according to claim 1, wherein the discharging module comprises a MOS transistor, the pre-discharge enable is connected to the gate of the MOS transistor, the drain of the MOS transistor is connected to the bit line, and the source of the MOS transistor is grounded.
7. The nor flash reading device is applied to a nor flash storage array, and is characterized in that the nor flash storage array comprises:
a plurality of bit lines, adjacent bit lines are connected through a first capacitor;
each bit line is connected with a discharging module and a discharging enable control switch based on pre-discharging;
the discharging module is positioned at one side of the first capacitor close to the bit line power supply end;
the device comprises:
the discharging module is used for opening the pre-discharging enabling to start all the discharging modules so as to enable all the bit lines to discharge to 0 potential, and is also used for closing the pre-discharging enabling to enable all the bit lines to be in a suspension state and to suspend at 0 potential;
the reading module is used for establishing a reading voltage to read the storage data of the target storage unit;
the turning off the pre-discharge enable to make all the bit lines in a floating state and floating at 0 potential, and establishing a read voltage to read the stored data of the target memory cell includes:
establishing a word line voltage corresponding to a target memory cell;
turning off the pre-discharge enable to make all the bit lines in a floating state and floating at 0 potential;
precharging a bit line where a target memory cell is located;
the stored data of the target memory cell is read based on the read circuit.
8. A memory chip, characterized in that the memory chip comprises a control circuit, and the memory chip reads the stored data based on the control circuit operating the nor flash read method according to any one of claims 1 to 6.
9. An electronic device comprising the memory chip of claim 8.
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