JPH0773678A - Semiconductor static memory - Google Patents

Abstract

PURPOSE:To accelerate information read operation by arranging a load element pulling up a bit line in an SRAM on the central part of the bit line. CONSTITUTION:When a specified word line is made H level, a memory cell current flows through the bit line according to an information content of a relevant memeory cell. A voltage drop when the current flows through the bit line load element consisting of e.g. a MOSFET is detected by a sense amplifier mounted on one end of the bit line to be outputted as the bit data. When the bit line is long and thin, since the voltage drop due to resistance of the bit line itself is added to that also, a difference occurs to the level of a detection signal according to the position of the cell. As a countermeasure, the bit line load element is arranged on the central part of the bit line in the direction of prolongation. Thus, the resistance of the bit line is reduced substantially.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to increasing the scale and speed of a semiconductor static memory.

[0002]

2. Description of the Related Art In a current large-capacity semiconductor static random access memory (SRAM), the bit line length is increased due to an increase in the number of cells connected to a pair of bit lines in accordance with the increase in size, and on the other hand, Due to the miniaturization of LSIs, the line width of bit lines has been reduced. Due to these factors, the resistance of the bit line itself tends to increase,
This causes deterioration of the information reading time and reduction of the operation margin. In FIG. 4, in SRAM,
An example of a circuit from a bit line to a sense amplifier is shown. In this circuit, the information of the memory cell is the word line WL1.
Becomes high (H) level, and is read as the memory cell current ICI, and this current is read by the load MOSFE.
By flowing into TMP41, a voltage drop occurs and a potential difference of ΔV is applied to the input of the sense circuit SA. However, here, when the bit line itself has a parasitic resistance Rb, the input amplitude ΔV to the sense circuit differs depending on the position of the selected memory cell. In FIG. 4, when the memory cell connected to the word line WL2 is selected, the memory cell current IC2 is the same as ICI, but because IC2 flows with respect to the sum of the ON resistance of the bit line load MP41 and the bit line resistance Rb. In addition, the voltage drop of the bit line B becomes larger than that when the memory cell 1 is selected, and Δ
V will increase. For high speed operation, it is preferable that the input signal amplitude ΔV of the sense circuit is small. More than necessary △
The increase of V deteriorates the inversion time of the bit line and causes an increase in read time.

[0003]

However, LS in recent years
Since the bit line resistance has increased remarkably with the increase in I, the difference in the bit line amplitude value depending on the position of the selected memory cell cannot be ignored. Another problem is that the bit line resistance increases the signal delay time on the bit line. It is expected that this problem will become more prominent as the integration further progresses in the future, and will become a major problem in realizing a high-speed SRAM.

It is an object of the present invention to minimize the deterioration of the read operation speed by optimizing the arrangement position of the bit line load even when the resistance of the bit line is high.

[0005]

SUMMARY OF THE INVENTION According to the present invention, a read static current from a selected memory cell is applied to a resistive load connected through a pair of bit lines to generate a potential difference, thereby reading information. In the memory, the resistive load is arranged at the center of the bit line.

According to the present invention, even if the bit line resistance increases, the deterioration of the information reading time of the SRAM can be minimized and a larger scale high speed SRAM can be realized.

[0007]

EXAMPLES Next, examples of the present invention will be described with reference to FIG. FIG. 1 shows the configuration of the first embodiment of the present invention. Conventionally, as shown in FIGS. 2A and 2B, the bit line load has been arranged at the end of the bit line. This is because the arrangement at the end portion is easy because it is sufficient to connect to the bit line on only one side. In the present invention, as shown in FIG. 1, the bit line load is arranged at the center of the bit line. next,
The effect of the present invention will be described with reference to FIG. FIG. 3 shows the relationship between the arrangement position of the bit line load on the bit line and the bit line delay time. As a design parameter, a large capacity SRAM equivalent to 16 Mb is assumed. This bit line delay time indicates the maximum delay time when switching and reading two arbitrary memory cells on the same bit line.
The bit line resistance values are 0Ω, 500Ω, and 1KΩ. The greater the bit line resistance, the more noticeable the influence of the delay time on the bit line load placement position, and the highest speed is achieved when the bit line load is placed slightly from the center of the bit line to the sense amplifier. This is because if the bit line load is placed in the center of the bit line, the pull-up current of the bit line is supplied from the center of the bit line, so the bit line resistance appears to be half and high-speed bit line pull-up can be performed. Is.

Therefore, in the actual layout of the memory cell, the bit line delay time can be minimized by disposing the bit line load MOS in the center of the bit line.

[0009]

According to the effects of the present invention, the object of achieving the minimum deterioration of the read operation speed even when the bit line resistance is high is achieved by the structure described in the claims. Is.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of a conventional method.

FIG. 3 is a diagram showing simulation results showing the effect of the present invention.

FIG. 4 is a diagram of a bit line peripheral circuit of a semiconductor static memory.

[Explanation of symbols]

MP41, MP42 p channel MO for bit line load
S transistor WL1, WL2 Word line B, B bar Bit line Rb Bit line resistance Ic1, Ic2 Memory cell current ΔV Input signal amplitude to sense circuit VCC Power supply voltage

Claims (1)

[Claims] 1. A semiconductor static memory for reading information by causing a read current from a selected memory cell to flow through a resistive load connected through a pair of bit lines to generate a potential difference, and the resistive load is applied to the semiconductor static memory. A semiconductor static memory characterized by being arranged in the center of a bit line.