JPH09147562A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize remarkable reduction of power consumption by providing a transistor for precharging of the bit lines between a transistor for selection of bit line pair and a current detection type sense amplifier. SOLUTION: The MOS transistors TR PT1 and PT2 for precharging the bit lines are connected only to the selected bit line pair. Therefore, even when the predetermined word lines WL are selected depending on the address input and the read transistor of the non-selected memory cells connected to these selected word lines is turned on, the nMOS transistors for selecting bit line pairs between the non-selected bit line pairs and the nMOS transistors PT1 and PT2 for precharging are all turned off. Since the non-selected bit line pair is perfectly separated from the nMOS transistor for precharging, ineffective power consumption is never generated in the non-selected bit line pair.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device using a current detection type sense amplifier.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional configuration. In the figure,
BL ₀ , BL ₁ , ..., BL _n are each a plurality of memory cells (MC ₀₀ , MC ₀₁ , ..., MC _0m ), (MC ₁₀ , MC
_{, 11} , MC _1m ), ..., (MC _n0 , MC _n1 , ..., M
C _nm ) is the connected bit line pair. Corresponding memory cells of each bit line pair have the same word line W.
It is connected to L ₀ , WL ₁ , ..., Or WL _m .

The structure of the memory cell is shown in FIG. 6 n
SR composed of MOS transistors T _{11 to} T ₁₆
It is an AM cell.

Returning to FIG. 2, the CDA is a current detection type sense amplifier, PT ₀₁ , PT ₀₂ , PT ₁₁ , PT ₁₂ , ..., PT _n1 , P provided commonly for the plurality of bit line pairs.
T _n2 is an nMOS transistor for precharging. Further, ST ₀₁ , ST ₀₂ , ST ₁₁ , ST ₁₂ , ..., ST _n1 , S
T _n2 is an nMOS transistor for selecting a bit line pair.

Word line selection and bit line pair selection are performed based on the output of the address decoder, and the stored information of a specific memory cell is detected by the current detection type sense amplifier CDA and output.

The structure of the current detection type sense amplifier CDA is shown in FIG. The sense amplifier consists of four pMOS transistors T ₁ , T ₂ , T ₃ and T ₄ and two nMOS transistors T ₅ and T ₆ .

When the memory cell MC is not selected, the bit lines BL and BL bar are exactly the same,
The same current flows respectively. Now, let this value be I + i, and let I be the current value that the memory cell draws from the bit line when the memory cell is selected. If the memory cell is selected, the bit line BL on the side storing 0 The current value decreases by I due to the drawing of the memory cell, so that it becomes i, while the bit line B on the side storing 1 is B.
Since the current value of L bar is not pulled in by the memory cell,
It remains at I + i. Both of these currents are input to the current detection type sense amplifier CDA, amplified by the positive feedback operation of the transistors T ₁ and T _2, converted into voltage by the load MOS transistors T ₅ and T _6, and output.

[0008]

In FIG THE INVENTION An object you try solving], for example, to select the memory cell MC ₀₀ is the word line WL
₀ is at H level (other word lines are at L level), bit line pair selection signal S ₀ is at H level (other bit line pair selection signals are at L level)
, And the memory information of the memory cell MC ₀₀ is output, but at this time, the non-selected memory cells MC ₁₀ , ..., MC _n0 connected to the selected word line WL ₀ are also connected to the bit line pair. Therefore, a current is drawn into the memory cell by the bit line on the side storing 0, resulting in unnecessary power consumption. As the number of memory cells connected to the same word line increases, this wasteful power consumption also increases.

The present invention solves the above-mentioned conventional problems.

[0010]

The above problems are caused by the fact that the bit line precharge transistor (constant current source) is directly connected to each bit line. In other words,
Only the selected bit line pair is connected to the current supply source, and the other unselected bit line pairs are not connected to the current supply source, so that unnecessary power consumption in the unselected bit line pair is prevented. It

The present invention realizes the above.

That is, the semiconductor memory device of the present invention includes a plurality of bit line pairs each having a plurality of memory cells connected thereto, a single current detection type sense amplifier, the plurality of bit line pairs and the single bit line pair. And a bit line pair selection circuit for connecting only a selected bit line pair of the plurality of bit line pairs to the single current detection type sense amplifier, and the bit line. In a semiconductor memory device comprising a current supply source for supplying a predetermined current to a pair, the current supply source is provided between the bit line pair selection circuit and the current detection type sense amplifier. It is characterized by.

In the semiconductor memory device, the memory cells are SRAM cells, and the memory cells corresponding to each bit line pair are connected to the same word line. is there.

According to the present invention, only the selected bit line pair is connected to the current supply source. Therefore, no useless power consumption occurs in the unselected bit line pair.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

The difference from the prior art lies in the positions of the bit line precharge nMOS transistors PT ₁ and PT ₂ (constant current supply sources). That is, the bit line precharge transistors PT ₁ and PT ₂ are provided between the bit line pair selection transistors ST ₀₁ , ST ₀₂ , ..., ST _n1 , ST _n2 and the current detection type sense amplifier CDA.

In the figure, BL ₀ , BL ₁ , ..., BL
_n is a plurality of memory cells (MC ₀₀ , MC ₀₁ ,
..., MC _0m ), (MC ₁₀ , MC ₁₁ , ..., MC _1m ), ...,
(MC _n0 , MC _n1 , ..., MC _nm ) are connected bit line pairs. The corresponding memory cell (M
_{C 00, MC 10, ...,} MC n0), (MC 01, MC 11, ...,
MC _n1 ), ..., (MC _0m , MC _1m , ..., MC _nm ) are connected to the same word lines WL ₀ , WL ₁ , ..., WL _m , respectively. The memory cell MC is an SRAM cell composed of six nMOS transistors as in the conventional case. Incidentally, instead of the load transistors T ₁₃ and T ₁₄ ,
The structure may be such that a poly-Si high resistance load is provided, or p
It goes without saying that a CMOS configuration in which a MOS transistor is provided may be used.

The CDA is a current detection type sense amplifier, PT ₁ and P, which is commonly provided for the plurality of bit line pairs.
T ₂ is a bit line precharge nMOS transistor (constant current supply source) provided in common for the plurality of bit line pairs, ST ₀₁ , ST ₀₂ , ST ₁₁ , ST ₁₂ , ..., S
T _n1 and ST _n2 are bit line pair selection signals S ₀ , S ₁ , ..., S
nMO for bit line pair selection controlled on / off by n
It is an S transistor. A pMOS whose gate is grounded is used as a bit line precharge transistor.
A transistor may be provided.

Word line selection and bit line pair selection are performed based on the output of the address decoder, and the stored information in a specific memory cell is detected by the current detection type sense amplifier CDA and output.

The configuration of the current detection type sense amplifier CDA is the same as the conventional one. That is, as shown in FIG. 4, it comprises four pMOS transistors T ₁ , T ₂ , T ₃ and T ₄ and two nMOS transistors T ₅ and T ₆ .

In order to increase the speed, as shown in FIG. 5, an analog switch (a pair of pMOS transistor and nMOS transistor) AS ₁ which is turned on immediately before the read operation and turned off immediately after the read operation is set. It may be provided. When the analog switch AS ₁ is turned on, the potentials of the output terminals D and D become the same potential, and the positive feedback operation of the cross-coupled pMOS transistors T ₁ and T ₂ weakens. After that, the predetermined word line WL and the bit line pair selection signal S become H level, the selected memory cell MC starts to draw a current, and the analog switch AS during the signal transition period during which the current flowing through the bit lines BL and BL bar starts to change. Turn off ₁ and operate the sense amplifier CDA. The analog switch AS ₁ weakens the positive feedback operation of the sense amplifier, which enables high-speed reading. Further, as shown in FIG. 6, in addition to the analog switch AS ₁ , an analog switch AS ₂ that operates in the same manner may be provided. When the second analog switch AS ₂ is turned on, the input currents to the sense amplifiers become equal and the positive feedback operation of the transistors T ₁ and T ₂ is weakened. As a result, it is possible to read data at a higher speed.

According to the structure of this embodiment, the precharge nMOS transistors PT ₁ and PT ₂ are connected only to the selected bit line pair. Therefore, a predetermined word line WL is selected (becomes H level) according to the address input, and the read (write) transistors (T ₁₅ and T in FIG. 3) of the non-selected memory cells connected to the selected word line are selected.
_{Even when 16} ) is turned on, all the nMOS transistors for selecting the bit line pair between the unselected bit line pair and the precharge nMOS transistors PT ₁ and PT ₂ are turned off, and the unselected bit line pair and the precharge Since the nMOS transistors for use are completely separated from each other, there is no waste of power consumption in the unselected bit line pair.

[0024]

As described in detail above, according to the present invention, it is possible to significantly reduce power consumption in a semiconductor memory device having a structure using a current detection type sense amplifier. Further, since the number of current supply sources can be remarkably reduced, the LSI chip area can be remarkably reduced.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention.

FIG. 2 is a circuit configuration diagram of a conventional semiconductor memory device.

FIG. 3 is a circuit configuration diagram of an SRAM cell.

FIG. 4 is a circuit configuration diagram of a current detection type sense amplifier.

FIG. 5 is a circuit configuration diagram of another configuration example of the current detection type sense amplifier.

FIG. 6 is a circuit configuration diagram of still another configuration example of the current detection type sense amplifier.

[Explanation of symbols]

BL ₀ , ..., BL _n Bit line pair WL ₀ , ..., WL _m Word line MC ₀₀ , ..., MC _nm Memory cell PT ₁ , PT ₂ Precharge nMOS transistor CDA Current detection type sense amplifier ST ₀₁ , ST ₀₂ , , ST _n1 , ST _n2 bit line pair selection nMOS transistor S ₀ , ..., S _n bit line pair selection signal

Claims (2)

[Claims] 1. A plurality of bit line pairs each having a plurality of memory cells connected thereto, a single current detection type sense amplifier, a plurality of bit line pairs and the single current detection type sense amplifier. A bit line pair selection circuit that is provided between the bit line pair selection circuit and connects only the selected bit line pair of the plurality of bit line pairs to the single current detection type sense amplifier, and supplies a predetermined current to the bit line pair. A semiconductor memory device provided with a current supply source, wherein the current supply source is provided between the bit line pair selection circuit and the current detection type sense amplifier. 2. The memory cell is an SRAM cell,
2. The semiconductor memory device according to claim 1, wherein the memory cells corresponding to each bit line pair are connected to the same word line.