JP3317334B2 - Semiconductor memory device and data reading method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device capable of high-speed operation.

[0002]

2. Description of the Related Art As this kind of semiconductor memory device, Japanese Patent Laid-Open Publication No.
Japanese Patent Application Laid-Open No. 4-188496 discloses a semiconductor memory device having one bit line for each memory cell column. FIG. 4 shows a schematic circuit configuration of the semiconductor memory device.

In the circuit shown in FIG. 4, word lines WL1, W
L2 and the bit line BL1 are provided so as to be orthogonal to each other.
Are provided respectively. The memory cell 21 selected by the word line WL1 and the memory cell 21 selected by the word line WL2 are both connected to the bit line BL1.

The bit line BL1 has a precharge transistor N1 at one end and a sense amplifier circuit 22 at the other end. The sense amplifier circuit 22 includes two bipolar transistors Q1, Q2, a sense amplifier activation transistor N2 commonly connected to the emitters of the bipolar transistors Q1, Q2, and a collector between the bipolar transistors Q1, Q2 and a power supply. Load resistors R1 and R2 connected to each other, a diode D1 for inputting the collector output of bipolar transistor Q1 to the base of bipolar transistor Q2, and a base bias load connected between the base of bipolar transistor Q2 and a ground line. R3. In this circuit, one bit line is arranged for each memory cell column.

In the semiconductor memory device configured as described above, data from a memory cell selected by word lines WL1 and WL2 is input to sense amplifier circuit 22 via bit line BL1. In the sense amplifier circuit 22,
The input signal is input to the base of bipolar transistor Q1, and is differentially amplified by inputting the signal from the collector of bipolar transistor Q1 to the base of bipolar transistor Q2, and the output signal from the collector of each bipolar transistor Q1, Q2. / D0 and D0 are obtained.

[0006]

The above-described conventional semiconductor memory device has a configuration in which one bit line is provided for each memory cell column, and all memory cells in one column have the same one bit. Connected to the wire. In this configuration, of the transfer gates connecting the memory cells and the bit lines, the gates other than those selected by the word lines are merely loads, and the greater the number, the greater the load on the bit lines. As described above, in the conventional semiconductor memory device, since the load on the bit line is increased, it is difficult to perform the read / write operation at high speed.

An object of the present invention is to provide a semiconductor memory device which solves the above problem and reduces the load on a bit line so that the read / write operation can be performed at high speed. Another object of the present invention is to provide a data read method capable of performing a data read operation at high speed.

[0008]

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a first memory cell means connected to a first bit line and selected by a first word line; Second memory cell means connected to a second bit line and selected by a second word line, and connected to the first bit line so that the potential of the bit line is at a first potential level. And a second precharge means connected to the second bit line and precharged so that the potential of the bit line becomes a second potential level lower than the first potential level. The first memory cell means, and a sense amplifier means for receiving the potentials of the first and second bit lines as inputs and amplifying and outputting a potential difference between the bit lines. Is the data And maintaining a high potential for maintaining the first bit line at a precharged potential or a low potential for maintaining the potential of the first bit line lower than the second potential level; The second memory cell means may store, as data, a low potential for maintaining the second bit line at a precharged potential, or
And the sense amplifier means keeps the potential level of the second bit line lower than the potential level of the first bit line. In the state, 0 is output, and the potential level of the second bit line rises and exceeds the potential level of the first bit line, or the potential level of the first bit line falls and the second bit line falls. below the potential level of the bit line, and outputs a 1.

A data read method according to the present invention includes first memory cell means connected to a first bit line, and second memory cell means connected to a second bit line. A data read method performed in a semiconductor memory device for selectively reading data from said first and second memory cell means based on a potential difference between lines, wherein said first bit line is connected to a first bit line. The second bit line is precharged to a second potential level lower than the first potential level, and the second bit line is precharged to a second potential level lower than the first potential level. A high potential that maintains the first bit line at a precharged potential, or a low potential that causes the potential of the first bit line to be lower than the second potential level. And the second memory cell means has a low potential for maintaining the second bit line at a precharged potential, or the potential of the second bit line is the first potential. To hold a high potential that is higher than the potential level of
After precharging the first and second bit lines, the data held in the memory cell means selected from the first and second memory cell means is
A state in which the potential level of the second bit line is lower than the potential level of the first bit line is set to 0, and the potential level of the second bit line rises and exceeds the potential level of the first bit line. The read state is read as 1 when the potential level of the first bit line falls or falls below the potential level of the second bit line.

(Operation) In the present invention configured as described above, the memory cell conventionally connected to one bit line is replaced with the first memory cell means connected to the first bit line. Since the second memory cell means connected to the two bit lines is divided into two, the load of the bit line on each bit line is reduced by half compared to the conventional case, and the write / read operation is correspondingly reduced. Can be performed at high speed.

In addition, in the present invention, although the number of bit lines is two, at least one of the bit lines is always maintained at the precharged potential level. The capacity of the electric charge charged / discharged in the above depends on the load capacity of one bit line, and the load capacity per one bit line depends on the number of memory cells connected to the bit line. Therefore, if the number of memory cells connected to one bit line is reduced, the amount of charge and discharge is reduced.

Further, in the semiconductor memory device and the data reading method of the present invention, when the first memory cell means is selected, if the first memory cell means holds high-potential data, 1 bit line is maintained at the precharged potential, and if low potential data is held,
The potential of the first bit line becomes lower than the potential of the second bit line. On the other hand, when the second memory cell means is selected, if the second memory cell means holds high-potential data, the potential of the second bit line is higher than the potential of the first bit line. When the data is high and low-potential data is held, the second bit line is maintained at the precharged potential. Therefore, the state in which the potential level of the second bit line is lower than the potential level of the first bit line is set to 0, and the potential level of the second bit line rises and exceeds the potential level of the first bit line. Alternatively, by setting the state in which the potential level of the first bit line falls below the potential level of the second bit line to 1, the data held in the first and second memory cell means is read out. Becomes possible.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a schematic configuration of a semiconductor memory device according to one embodiment of the present invention. In this circuit, word lines W1 and W2 are provided so as to be orthogonal to bit lines B1 and B2, and memory cell 11 selected by word line W1 is connected to bit line B1 and memory cell 11 selected by word line W2 12 is connected to the bit line B2. Each of the bit lines B1 and B2 is an input to the sense amplifier circuit 15, and the sense amplifier circuit 15
Can obtain an output result based on the potential difference between the bit lines.

The memory cell 11 is composed of a flip-flop circuit and an N-type MOS transistor, and performs writing / reading when the connected word line W1 goes high. This memory cell 11 has a bit line B1
Is maintained as data, or a low potential such that the potential of the bit line B1 becomes lower than the potential level of the bit line B2.

The memory cell 12 comprises a flip-flop circuit and a P-type MOS transistor, and performs writing / reading when the connected word line W2 goes low. This memory cell 12 has a bit line B2
Is maintained as data, or a low potential such that the potential of the bit line B2 is higher than the potential level of the bit line B1.

The word lines W1 and W2 are connected to decoders 16 and 17 which receive the address signal line AD, respectively. When the decoder 16 is in the selected state, the word line W
1 is set to the high level, and the decoder 17 sets the level of the word line W2 to the low level in the selected state. These decoders 16 and 17 are configured such that when one is in a selected state, the other is in a non-selected state.

Bit line B1 connected to memory cell 11
Are connected to the power supply potential via an N-type MOS transistor 13 whose gate is connected to the clock line C2. Here, the source of the N-type MOS transistor 13 is connected to the power supply potential, and the drain is connected to the bit line B1. On the other hand, the bit line B2 connected to the memory cell 12 is
The gate is connected to the ground potential via a P-type MOS transistor 14 connected to the clock line C1. Here, the source of the P-type MOS transistor 14 is connected to the ground (ground) potential, and the drain is connected to the bit line B2.

The clock line C2 is connected to the clock buffer 18,
19 is connected to the clock line CLK, and the clock line C1 is connected to the clock line CLK via the clock buffer 18.
It is connected to the. The clock line CLK is connected to a clock line C3 which is a sense amplifier activation signal line of the sense amplifier circuit 15 via a clock buffer 18, and when the clock line CLK is at a low level, the clock line C3 is at a high level. Sense amplifier circuit 15
Is activated.

The sense amplifier circuit 15 outputs 0 when the potential level of the bit line B2 is lower than the potential level of the bit line B1, and when the potential level of the bit line B2 rises and exceeds the potential level of the bit line B1. Alternatively, when the potential level of the bit line B1 falls and falls below the potential level of the bit line B2, the potential difference between the bit lines is amplified and output.

In the above configuration, the memory cell 1
1 is an N-type MOS transistor, a memory cell 12 is a P-type MOS transistor, and the bit line B1 is an N-type M transistor.
The reason why the configuration is such that the power supply potential is precharged via the OS transistor 13 and the bit line B2 is precharged to the ground potential via the P-type MOS transistor 14 is as follows.

For example, when the input is at the ground potential, the output of the N-type MOS transistor is at the ground potential. When the input is at the power supply potential, the output is at a potential level one step lower than the power supply potential. On the other hand, in the case of a P-type MOS transistor, when the input is at the power supply potential, the output is at the power supply potential level. When the input is at the ground potential, the output is at a level one step higher than the ground potential. From this,
Since the N-type MOS transistor 13 is provided, the bit line B1 is precharged to the first potential level (one level lower than the power supply potential), and the bit line B2 is
By providing the type MOS transistor 14, it is precharged to the second potential level (one level higher than the ground potential level). Therefore, in reading data from the memory cell 11, the electric charge is discharged through the N-type MOS transistor, so that the bit line B1 is maintained at the precharged potential if the high potential (power supply potential) data is held. When the low potential (ground potential) data is held, the potential of the bit line B1 becomes lower than the second potential level of the bit line B2 (a level one level higher than the ground potential level). In reading the memory cell 12, P
Since the electric charge is discharged through the type MOS transistor, if data of a high potential (power supply potential) is held,
The potential of the bit line B2 rises to the power supply potential level, and if low potential (ground potential) data is held, the bit line B2 is maintained at the precharged potential.

Next, the operation of the semiconductor memory device will be specifically described. Here, the case of reading data from the memory cell 11 and the case of reading data from the memory cell 12 will be described separately. In the following description, data “0” and “1” held in each of the memory cells 11 and 12 correspond to “0” and “1” in the output of the sense amplifier circuit 15.

(1) In the case of reading data from the memory cell 11 FIG. 2 is a flowchart in the case of reading data from the memory cell 11, and FIG. Potential) is held,
FIG. 3B shows a case where data “1” (low potential) is held in the memory cell 11. Hereinafter, the operation will be described with reference to FIG.

When a high-level signal is input to the clock line CLK, the precharge transistor 1
Both the transistors 3 and 14 are turned on, the bit line B1 is precharged to the power supply potential via the N-type MOS transistor 13, and the bit line B2 is precharged to the ground potential via the P-type MOS transistor 14. The level of each of the precharged bit lines B1 and B2 is
1 is higher. Specifically, the bit line B1 has a potential level one step lower than the power supply potential, and the bit line B2 has the ground potential.

When the clock line CLK goes low, the precharge transistors 13 and 14 are both turned off, and data can be read from the memory cells.

The decoder 16 is connected to the address signal line AD.
Operates, the word line W1 goes high, and the operation of reading data from the memory cell 11 is started.
At this time, since the decoder 17 is in the non-selected state, the word line W2 is at the high level, and data is not read from the memory cell 12. Therefore, the bit line B2 maintains the precharged level.

When the memory cell 11 holds data "0" (high potential), the bit line B1 is
As shown in (a), the precharged level is maintained. Since the level of the bit line B2 is lower than the level of the bit line B1, "0" is read from the output OUT of the sense amplifier circuit 15.

When the memory cell 11 holds data "1" (low potential), the bit line B1 is
As shown in (b), the level drops to a level lower than the level of the bit line B2. When the level of the bit line B1 becomes lower than the level of the bit line B2, the sense amplifier circuit 15 operates and "1" is read out to the output OUT.

(2) In the case of reading data from the memory cell 12 FIG. 3 is a flowchart in the case of reading data from the memory cell 12. FIG. Potential) is held,
FIG. 3B shows a case where data “1” (high potential) is held in the memory cell 12. Hereinafter, the operation will be described with reference to FIG.

As in the case of the above-described memory cell 11, when a high-level signal is input to the clock line CLK, both the bit lines B1 and B2 are precharged.
Also in this case, the precharge is performed so that the level of the bit line B1 is higher. Here, when the clock line CLK goes low, the transistors 13 for precharging,
14 are both in the OFF state, and data can be read from the memory cells.

The decoder 17 is connected to the address signal line AD.
Operates, the word line W2 goes low, and the operation of reading data from the memory cell 12 is started.
At this time, since the decoder 16 is in the non-selected state, the word line W1 is at the low level, and the memory cell 11
No data is read from the. Therefore, the bit line B1 maintains the precharged level.

When the memory cell 12 holds data "0" (low potential), the bit line B2 is
As shown in (a), the precharged level is maintained. Since the level of the bit line B1 is higher than the level of the bit line B2, "0" is read to the output OUT of the sense amplifier circuit 15.

When the memory cell 12 holds data "1" (high potential), the bit line B2 is
As shown in (b), the level rises to a level higher than the level of the bit line B1. Then, when the level of the bit line B2 becomes higher than the level of the bit line B1, the sense amplifier circuit 15 operates and "1" is read to the output OUT.

In the above description, only one memory cell 11, 12 is connected to each of the bit lines B1, B2. However, in an actual semiconductor memory device, a plurality of memory cells are connected. For example, the memory cells 11 and 12
A first memory cell group (a group of memory cells 11) in which a plurality of data are mixed in one column and writing / reading is enabled by a high selection signal and a writing / reading operation by a low selection signal are performed. The second that can read
Of memory cell groups (groups of memory cells 12) are connected to the bit lines B1 and B2, respectively.

[0036]

According to the present invention constructed as described above, the load on the bit line is reduced by half compared with the conventional case, and accordingly, the write / read operation can be performed at a higher speed. effective.

In addition, since the number of memory cells connected to one bit line is reduced, and the amount of charge / discharge is reduced, power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram illustrating a schematic configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining a read operation of the semiconductor memory device shown in FIG.
1 shows data reading when data “0” is held in 1, and FIG. 2B shows data reading when data “1” is held in the memory cell 11.

FIG. 3 is a flowchart for explaining a read operation of the semiconductor memory device shown in FIG.
2 shows data reading when data “0” is stored in the memory cell 12, and FIG. 2B shows data reading when data “1” is stored in the memory cell 12.

FIG. 4 is a circuit diagram showing a schematic configuration of a semiconductor memory device disclosed in Japanese Patent Application Laid-Open No. 4-188496.

[Explanation of symbols]

 11, 12 memory cell 13 N-type MOS transistor 14 P-type MOS transistor 15 sense amplifier circuit 16, 17 decoder 18, 19 clock buffer B1, B2 bit line W1, W2 word line CLK, C1, C2, C3 clock line AD address signal world

Claims (6)

(57) [Claims] 1. A first memory cell means connected to a first bit line and selected by a first word line, and a first memory cell means connected to a second bit line and selected by a second word line. Two memory cell units, a first precharge unit connected to the first bit line and precharging the bit line to a first potential level, and a second precharge unit. A second precharging means connected to the second bit line for precharging the potential of the bit line to a second potential level lower than the first potential level; and setting the potentials of the first and second bit lines respectively. Sense amplifier means for inputting and amplifying and outputting a potential difference between the bit lines, wherein the first memory cell means stores the first
A high potential for maintaining the bit line at a precharged potential, or a low potential for keeping the potential of the first bit line lower than the second potential level; The means may include, as data, the second
A low potential for maintaining the bit line at a precharged potential, or a high potential for maintaining the potential of the second bit line higher than the first potential level, wherein the sense amplifier means comprises: When the potential level of the second bit line is lower than the potential level of the first bit line, 0 is output, and the potential level of the second bit line rises to increase the potential level of the first bit line. Or when the potential level of the first bit line falls and falls below the potential level of the second bit line, the semiconductor memory device outputs 1 . 2. The semiconductor memory device according to claim 1, wherein said plurality of first memory cells are commonly connected to said first bit line.
And a plurality of second memory cells commonly connected to the second bit line.
And a second memory cell group comprising the memory cell means of (1), wherein the first and second memory cell groups exist in one column. 3. The semiconductor memory device according to claim 1, wherein said first memory means selects said first memory cell means via said first word line, and said second memory cell means via said second word line. And second decoder means for selecting the second memory cell means. When the first and second decoder means are in a selected state, the other is in a non-selected state. A semiconductor memory device characterized in that: 4. The semiconductor memory device according to claim 1, wherein said first precharge means includes one source / drain.
A first N-type MOS transistor having a source / drain connected to the power supply potential and the other source / drain connected to the first bit line, wherein the second precharge means includes one source / drain
A first P-type MOS transistor having a source connected to the ground potential and the other source / drain connected to the second bit line, wherein the first memory cell means holds the ground potential as a low potential A second N-type MOS transistor configured to hold a power supply potential as a high potential, and to discharge the held potential to the first bit line; A second P-type MOS transistor configured to hold a ground potential as a potential and a power supply potential as a high potential, and discharge the held potential to the second bit line. Semiconductor storage device. 5. The semiconductor memory device according to claim 4, wherein said first word line is a second word line of said first memory cell means.
And the second word line is connected to the gate of the second memory cell means.
A first decoder means connected to the gate of the P-type MOS transistor for activating the second N-type MOS transistor via the first word line to select the first memory cell means; Second decoder means for activating the second P-type MOS transistor via a second word line to select the second memory cell means, wherein the first and second decoders are provided. The semiconductor memory device is characterized in that, when one is in a selected state, the other is in a non-selected state. 6. A semiconductor memory device comprising: first memory cell means connected to a first bit line; and second memory cell means connected to a second bit line, based on a potential difference between these bit lines. A data read method performed in a semiconductor memory device for selectively reading data from the first and second memory cell means, wherein the first bit line is set to a first potential level. Precharging, and precharging the second bit line to a second potential level lower than the first potential level, and for the first memory cell means, setting the first bit line to A high potential for maintaining a precharged potential or a low potential for keeping the potential of the first bit line lower than the second potential level as data; As for the second memory cell means, a low potential for maintaining the second bit line at a precharged potential, or a potential for the second bit line higher than the first potential level High potential is retained as data, and after precharging the first and second bit lines, data retained in a memory cell means selected from the first and second memory cell means To
A state in which the potential level of the second bit line is lower than the potential level of the first bit line is set to 0, and the potential level of the second bit line rises and exceeds the potential level of the first bit line. A data reading method wherein a read state or a state in which the potential level of the first bit line falls and falls below the potential level of the second bit line is set to 1.