JPH0555515A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce an effect due to variations of a process by keeping the pull-down effect of a bit line unchanged by constructing a transistor by connecting in series memory transistors. CONSTITUTION:n Channel bypassing transistors 31 to 34 are constructed in the same structure as that of a memory transistor using a minimum design rule, and those transistors are disposed in series to ensure a predetermined transistor size. This structure is accordingly such that the c channel current bypassing transistors 31-34 and the transistor using a minimum design rule, are changed, interlocked upon the variations of a process. Thus, since performance of the transistor for supplying a potential to bit lines BL1-BL4 is varied as in the n channel current bypassing transistors 31-34, the pull-down effect of the bit lines is kept unchanged. Thus, stable operation is ensured without being affected by process variations.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 2 shows a conventional parallel type memory cell reading device having an n-channel current bypass transistor at a bit line end. In the figure, 1 to 4 are n-channel transistors for columns, 11 to 18 are n-channel transistors for memory cells, 21 to 28 are source wiring resistors,
31 to 34 are n-channel current bypass transistors, 41 is a sense amplifier, CL1 to CL4 are column selections, BL1 to BL4 are bit lines, WL1 to W
L2 is a word line. The gate of the current bypass transistor is connected to the power supply and is in a conductive state when the read-only device is in operation. The bit line is grounded via the transistor and has a structure for discharging the residual charge of the bit line when it is not selected.

[0003]

However, this n
The L dimension of the transistor for bypassing the channel current is usually several times larger than the L dimension of the transistor using the minimum design rule, so the effect of process variation is using the minimum design rule. It will be different from the transistor. Since the transistor using the minimum design rule is used for a column gate or the like that supplies a potential to the bit line, if the process changes, the current supply capability to the bit line also changes. However, since the pull-down capability of the n-channel current bypass transistor does not change, access delay or malfunction occurs. Therefore, the present invention has been made to solve such a problem, and the structure of an n-channel current bypass transistor has a minimum design rule.
It is an object of the present invention to obtain a semiconductor memory device which is less affected by process variations by arranging transistors having the same structure as the transistor using a line in a series to make the pull-down effect of the bit line constant.

[0004]

In the semiconductor memory device of the present invention, the bit line forming the memory cell is connected to the first power supply through at least one current bypass transistor, and the gate of the semiconductor transistor is In the semiconductor memory device connected to the second power source, the structure of the transistor is one in which memory transistors are connected in series.

[0005]

According to the above means of the present invention, since the pull-down effect of the bit line can obtain a constant value without being affected by the process variation, a semiconductor memory device having stable operation can be obtained.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a parallel type memory cell reading device having an n-channel current bypass transistor of the present invention at a bit line end. In the figure, 1 to 4 are n-channel transistors for columns, 11 to 18 are n-channel transistors for memory cells, 21 to 28 are source wiring resistors,
31 to 34 are n-channel current bypass transistors,
41 is a sense amplifier, CL1 to CL4 are column selections, BL1 to BL4 are bit lines, and WL1 to WL2
Is the word line. In the figure, the n-channel current bypass transistor has the same structure as the memory transistor using the minimum design rule, and these transistors are arranged in series to obtain a predetermined transistor size. Therefore, when the process changes, the transistor size of the n-channel current bypass transistor and the transistor using the minimum design rule change in conjunction with each other. Therefore, the ability of the transistor for supplying the potential to the bit line and the ability of the transistor for n-channel current bypass change similarly, and the effect of pulling down the bit line is constant. Therefore, a stable operation of the semiconductor memory device can be obtained, which is not affected by process variations.

[0007]

As described above, according to the present invention, n
Since the channel current bypass transistor and the memory transistor have the same structure, the effect of the bit line pull-down becomes constant regardless of process variations, and stable operation of the semiconductor memory device can be obtained.

[Brief description of drawings]

FIG. 1 is a memory cell read circuit diagram according to the present invention.

FIG. 2 is a circuit diagram of a memory cell read circuit according to a conventional technique.

[Explanation of symbols]

1 to 4 column n-channel transistor 11 to 18 memory cell n-channel transistor 21 to 28 source wiring resistance 31 to 34 n-channel current bypass transistor 41 sense amplifier 51 delay circuit CL1 to CL4 column selection BL1 to BL4 bit line WL1-WL2 word line

Claims (1)

[Claims] 1. A semiconductor memory device in which a bit line constituting a memory cell is connected to a first power supply through at least one current bypass transistor, and a gate of the semiconductor transistor is connected to a second power supply. 2. A semiconductor memory device according to claim 1, wherein the structure of the transistor is formed by connecting memory transistors in series.