JP2000040374A - Data output circuit and semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accelerate data output and to reduce noise by outputting output data held in a latch circuit with an output pin and outputting middle potential with the output pin only when the output data are changed. SOLUTION: When data of '1' is outputted from a sense amplifier circuit 25, the output data '1' from the sense amplifier circuit 25 and the data '1' beforehand held in a latch circuit 53 are inputted to an XNOR circuit 60, and the output of the XNOR circuit 60 becomes '1', and a switch 65 is turned on. When the data '1' of the sense amplifier circuit 25 and the latch circuit 53 are inputted to an XOR circuit 61, the output of the XOR circuit 61 becomes '0', and the switches 64, 65 are turned on, and the middle potential is outputted to an output pin 27 by resistors 62, 63. The output becomes the middle potential while the data output is delayed, and the time of the output data '1' and '0' are reduced. Further, the output potential difference is reduced to about half, and sizes of output buffers 55, 56 are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output circuit, and more particularly to an improvement in a data output circuit used in a semiconductor memory device.

[0002]

2. Description of the Related Art FIG. 1 shows a conventional data output circuit. The data output circuit includes an output stage control switch circuit 1 and an output stage control switch circuit 2 connected to a sense amplifier circuit 8, a latch circuit 3 and a latch circuit 4 connected thereto, and an output buffer connected thereto. 5 and an output buffer 6 and an output pin 7 connected thereto.
Here, the output stage control switch circuit 1 and the output stage control switch circuit 2 are clocked CMOS inverter circuits. The output buffer 5 is an NMOS transistor, and the output buffer 6 is a PMOS transistor. Output data from the sense amplifier circuit 8 is held in the latch circuits 3 and 4 via the output stage control switch circuit 1 and the output stage control switch circuit 2. Here, the output stage control switch circuit 1 and the output stage control switch circuit 2
Is for selecting output data from the sense amplifier circuit 8 according to the gate control signal generated by the gate control signal generation circuit 9.

Here, for example, it is assumed that data of "1" is output from the sense amplifier circuit 8. The output stage control switch circuit 1 and the output stage control switch circuit 2
Since this is a MOS inverter circuit, the gate control signal is 0
When the level becomes the level, the data of “0” is held in the latch circuits 3 and 4. Then, the output buffer 5
Is OFF, and the output buffer 6 is ON. Therefore, the reference voltage Vcc is output to the output pin 7, and the output data becomes "1". If the data of “0” is output from the sense amplifier circuit 8, the result opposite to the above, that is, the data “0” is output to the output pin 7.

[0004]

In order to increase the data output speed in the above-mentioned conventional technique, it is necessary to increase the buffer size of the output buffer 5 and the output buffer 6. Therefore, when the output data is inverted from “1” to “0” or from “0” to “1”, a large current flows through the output buffers 5 and 6. As a result, the fluctuation of the voltage with respect to the device, that is, the noise increases. Then, depending on the magnitude of the noise, there is a disadvantage that the device malfunctions.

Further, according to the above-mentioned conventional technique, for example, output data from the sense amplifier circuit 8 passes through the output stage control switch circuit 1 and the output stage control switch circuit 2. Further, the data is held in the latch circuits 3 and 4, and reaches the output pin 7 through the output buffers 5 and 6. Here, the output data from the sense amplifier circuit 8 passes through circuits such as the output stage control switch circuits 1 and 2 and the output buffers 5 and 6 before being output to the output pin 7, so that it takes time. Occurs. Furthermore, actually, some buffers (not shown) are often connected between the sense amplifier circuit 8 and the output stage control switch circuit 1 and the output stage control switch circuit 2.
For this reason, it is difficult to speed up data output.
The present invention has been made in view of the above-mentioned drawbacks, and aims to speed up data output and reduce noise.

[0006]

According to the present invention, there is provided a latch circuit for holding output data, an output pin for outputting the data held in the latch circuit, and an intermediate potential only when the output data changes. And a circuit for outputting to the output pin.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings (FIGS. 2 to 4). First, FIG. 2 is a block diagram of a part of a read system in a multi-bit SRAM according to the first embodiment of the present invention. 21 is a memory cell, 22 is a memory cell array, 23 is a row decoder, 24 is a column decoder, 25 is a sense amplifier circuit, 26 is a data output circuit,
27 is an output pin. The row decoder 23 selects a predetermined word line 67 according to a row address. The column decoder 24 selects each column in the memory cell array 22. The sense amplifier circuit 25 is a circuit that senses and amplifies the transmitted data, and is connected to the bit line 68. In this read system, data of a bit selectively read from a bit line of the memory cell array 22 is sense-amplified by a sense amplifier circuit 25 and is output to an output pin 27 via a data output circuit 26. Here, the first embodiment of the present invention relates to the data output circuit 26.

Hereinafter, a portion of the data output circuit 26 will be described with reference to FIG. This data output circuit 26
Includes an output stage control switch circuit 51 and an output stage control switch circuit 52 connected to the sense amplifier circuit 25, a latch circuit 53 and a latch circuit 54 connected thereto,
The output buffer 55 and the output buffer 56 connected thereto, the output pin 27 connected thereto, the XOR circuit 60 and the XNOR circuit 61 which are comparison circuits, the resistor 6
2 and a resistor 63, and a switch 64 and a switch 65. Here, the output stage control switch circuit 51 and the output stage control switch circuit 52 are clocked CMOS inverter circuits. The output buffer 55 is NMO
The output buffer 56 is an S transistor, and the output buffer 56 is a PMOS transistor. Further, the switch 64 is a PMOS transistor, and the switch 65 is an NMOS transistor. The XNOR circuit 60 and the XOR circuit 61 have two inputs. One input is data held by the latch circuits 53 and 54, and the other input is output data from the sense amplifier circuit 25. The output data from the sense amplifier circuit 25 is output to the output stage control switch circuit 5.
1 and are held by the latch circuits 53 and 54 via the output stage control switch circuit 52. At this time, the output stage control switch circuit 51 and the output stage control switch circuit 5
Reference numeral 2 is for selecting output data from the sense amplifier circuit 25 according to a gate control signal generated from the gate control signal generation circuit 66.

Here, for example, it is assumed that data "0" is output to the output pin 27. In this case, the output buffer 55 is ON and the output buffer 56 is OFF. Then, the data “1” is held in the latch circuits 53 and 54. In this state, consider a case where the data of “1” is output from the sense amplifier circuit 25 and a case where the data of “0” is output.

First, consider the case where data of "1" is output from the sense amplifier circuit 25. The output data “1” from the sense amplifier circuit 25 and the data “1” already held in the latch circuit 53 are input to the XNOR circuit 60. Therefore, XNOR
The output of the circuit 60 becomes "1". Therefore, the switch 65
Becomes ON. The output data “1” from the sense amplifier circuit 25 and the data “1” already held in the latch circuit 54 are input to the XOR circuit 61. Then, the output of the XOR circuit 61 becomes “0”. For this reason,
The switch 64 turns ON. That is, both the switch 64 and the switch 65 are turned ON. As a result, an intermediate potential generated by the resistors 62 and 63 is output to the output pin 27. Here, the resistor 62 and the resistor 63 output the output data “1” to the output pin 27.
Are determined such that an intermediate potential between the potential corresponding to the output data and the potential corresponding to the output data “0” is output.

On the other hand, since the output stage control switch circuit 51 and the output stage control switch circuit 52 are clocked CMOS inverter circuits, when the gate control signal becomes 0 level, the latch circuit 53 and the latch circuit 54 are set to "0". Data is retained. For this reason, the output buffer 55
F, the output buffer 56 is turned ON. As a result, data "1" is output to the output pin. here,
A circuit that causes a delay in the output of the data until the output data is output from the sense amplifier circuit 25 to the output pin 27, for example, the output stage control switch circuits 51 and 52
Or through one or more buffers not shown. For this reason, it takes some time until this data "1" is output to the output pin 27. As a result, data “1” is output to the output pin 27 after the intermediate potential is output as described above.

Next, consider the case where data of "0" is output from the sense amplifier circuit 25. In this case, X
The output data “0” from the sense amplifier circuit 25 and the data “1” already held in the latch circuit 53 are input to the NOR circuit 60. Therefore, XN
The output of the OR circuit 60 becomes “0”. Therefore, the switch 65 is turned off. The output data “0” from the sense amplifier circuit 25 and the data “1” already held in the latch circuit 54 are input to the XOR circuit 61. Then, the output of the XOR circuit 61 becomes “1”. Therefore, the switch 64 is turned off. That is, both the switch 64 and the switch 65 are turned off.

Since the output stage control switch circuit 51 and the output stage control switch circuit 52 are clocked CMOS inverter circuits, when the gate control signal (not shown) goes to the 0 level, the latch circuit 53 and the latch circuit 54 receive " 1 "is retained. Therefore, the output buffer 55 is turned on and the output buffer 56 is turned off. As a result, data "0" is output to the output pin. Thus, the data “0” remains output to the output pin 27.

As described above, when the data output to the output pin 27 changes, the output data changes once it reaches the intermediate potential. For this reason, the size of the output buffer 55 and the output buffer 56 can be reduced. Therefore, it is possible to suppress a large current from flowing through the output buffer 55 and the output buffer 56 when the output data is inverted from “1” to “0” or from “0” to “1”. This makes it possible to reduce noise. On the other hand, when the data output to the output pin 27 does not change, the output data remains unchanged. That is, only when the output data changes, the output data can be temporarily set to the intermediate potential.

Here, a temporal comparison between the data output according to the conventional technique and the data output according to the first embodiment will be described with reference to FIG. 4, a indicates output data from the sense amplifier circuit 25, b indicates a data output according to the conventional technique, and c indicates a data output according to the first embodiment of the present invention. First, data "1"
Is output. Then, at time T1,
It is assumed that the output data from the sense amplifier circuit 25 has changed from “1” to “0”. Then, according to the conventional technique (see FIG. 1), the time when the output buffer 5 and the output buffer 6 start operating after passing through the output stage control switch circuit 1 and the output stage control switch circuit 2 and a buffer (not shown) is determined. Let it be T2. Further, according to the conventional technique, the time when the output data of the output pin 7 becomes “0” is defined as T4. At this time, in the first embodiment of the present invention, the switches 64 and 65 are turned on by the outputs of the XNOR circuit 60 and the XOR circuit 61 a little after the time T1, and
The intermediate potential generated by the resistors 62 and 63 is output to the output pin 27. Then, at time T2, the output buffer 55 and the output buffer 56 start operating. At this time, unlike the conventional technique, the potential changes from an intermediate potential to a potential corresponding to data “0” instead of a potential corresponding to data “1”. Therefore, the output data becomes “0” at time T3. That is, in the conventional technique, while the data output is delayed (from time T1 to time T2), according to the first embodiment of the present invention, the output potential temporarily drops to the intermediate potential. According to the conventional technique, the output is at the intermediate potential while the data output is delayed. Therefore, according to the first embodiment of the present invention, the data is output only for the time difference between time T4 and time T3. It is possible to increase the output speed. Also, compared to conventional technology,
The drop of the output potential becomes about half, and the output buffer 55
In addition, the size of the output buffer 56 can be reduced. Therefore, noise can be reduced.

When data "1" is output to the output pin 27 and the output data from the sense amplifier circuit 25 becomes "0", the above "0" and "1" are inverted. Then, you can think in the same way.

The XOR circuit 61 and the XNOR circuit 6
0 is not limited to this, but may be any value as long as the data held in the latch circuits 53 and 54 can be compared with the data from the sense amplifier circuit 25.

As described above, according to the first embodiment of the present invention, it is possible to reduce the size of the output buffer 55 and the output buffer 56. Then, noise can be reduced. On the other hand, only when the output data changes, the output can be temporarily set to the intermediate potential. Further, the speed of data output can be increased.

Next, a second embodiment of the present invention will be described with reference to the drawings (FIGS. 2, 5, and 4). First, FIG. 2 is a block diagram of a part of a read system in a multi-bit SRAM according to the first embodiment of the present invention. 21 is a memory cell, 22 is a memory cell array, 23 is a row decoder, 24 is a column decoder, 25 is a sense amplifier circuit, 26 is a data output circuit, and 27 is an output pin. The row decoder 23 selects a memory cell so as to read data of a plurality of memory cells from the memory cell array 22 according to a row address through a word line 67 commonly connected to the memory cell 21. The column decoder 24 selects each column in the memory cell array 22. The sense amplifier circuit 25 is a circuit that senses and amplifies the transmitted data. The column decoder 24 and the sense amplifier circuit 25 are each connected to a bit line 68. In this reading system, the memory cell array 22
The bit data selectively read from the bit line is sense-amplified by the sense amplifier circuit 25, and the data is output to the output pin 27 via the data output circuit 26. Here, the second embodiment of the present invention relates to the data output circuit 26.

Hereinafter, the portion of the data output circuit 26 in FIG. 2 will be described with reference to FIG. The data output circuit 26 includes an output stage control switch circuit 51 and an output stage control switch circuit 52 connected to the sense amplifier circuit 25, a latch circuit 53 and a latch circuit 54 connected thereto, and an output circuit connected thereto. Buffer 55 and output buffer 56, and output pin 27 connected to them.
, An XOR circuit 61, an internal step-down circuit 66, and a switch 64. Here, the output stage control switch circuit 51 and the output stage control switch circuit 52 are
This is a MOS inverter circuit. The output buffer 55
Is an NMOS transistor, and the output buffer 56 is P
It is a MOS transistor. Further, the switch 64 is set to P
It is a MOS transistor. The XOR circuit 61
One input is data held by the latch circuit 54, and the other input is output data from the sense amplifier circuit 25. Output data from the sense amplifier circuit 25 is supplied to the latch circuits 53 and 5 through the output stage control switch circuit 51 and the output stage control switch circuit 52.
4 is held. At this time, the output stage control switch circuit 5
The 1 and output stage control switch circuit 52 is for selecting output data from the sense amplifier circuit according to the gate control signal generated from the gate control signal generation circuit 66.

Here, it is assumed that data “0” is output to the output pin 27, for example. In this case, the one connected to one of the inputs of the XOR circuit 61 of the latch circuit 53 and the latch circuit 54 holds data “1”. In this state, the sense amplifier circuit 25
Let us consider a case where data of “1” is output from the data and a case where data of “0” is output.

First, consider the case where data of "1" is output from the sense amplifier circuit 25. In this case, X
The output data “1” from the sense amplifier circuit 25 and the data “1” already held in the latch circuit 54 are input to the OR circuit 61. Then, the output of the XOR circuit 60 becomes “0”. Therefore, the switch 64 is turned on. As a result, the intermediate potential generated by the internal step-down circuit 66 is output to the output pin 27.

On the other hand, since the output stage control switch circuit 51 and the output stage control switch circuit 52 are clocked CMOS inverter circuits, when the gate control signal becomes 0 level, the latch circuit 53 and the latch circuit 54 are set to "0". Data is retained. For this reason, the output buffer 55
F, the output buffer 56 is turned ON. As a result, the reference voltage, that is, data “1” is output to the output pin. Here, the output data is the sense amplifier circuit 25
From the output pin 27 to the output pin 27, the signal passes through a circuit that causes a delay in data output, for example, the output stage control switch circuits 51 and 52 and one or more buffers (not shown). For this reason, it takes some time until this data "1" is output to the output pin 27. As a result, data “1” is output to the output pin 27 after the intermediate potential is output as described above.

Next, consider the case where data of "0" is output from sense amplifier circuit 25. In this case, X
The output data “0” from the sense amplifier circuit 25 and the data “1” already held in the latch circuit 54 are input to the OR circuit 61. Then, the output of the XOR circuit 61 becomes “1”. Therefore, the switch 64 is turned off.

Since the output stage control switch circuit 51 and the output stage control switch circuit 52 are clocked CMOS inverter circuits, when the gate control signal becomes 0 level, the latch circuit 53 and the latch circuit 54 are set to "1". Data is retained. For this reason, the output buffer 55
N, the output buffer 56 is turned off. As a result, data "0" is output to the output pin. Thus, the data “0” remains output to the output pin 27.

The temporal comparison between the data output according to the prior art and the data output according to the second embodiment of the present invention is the same as that shown in FIG. Also, XOR
The circuit 61 is not limited to this, and any circuit may be used as long as the data held in the latch circuit 54 and the data from the sense amplifier circuit 25 can be compared.

As described above, when the data output to the output pin 27 changes, the output data changes once it reaches the intermediate potential. For this reason, in the prior art, the output is at the intermediate potential while the data output is delayed, so according to the second embodiment of the present invention, only the time difference between time T4 and time T3 is obtained. It is possible to speed up data output (see FIG. 4). In addition, the size of the output buffer 55 and the output buffer 56 can be reduced as compared with the related art.
Therefore, the output data changes from “1” to “0” or “0”.
It is possible to suppress a large current from flowing through the output buffer 55 and the output buffer 56 when inverting from “1” to “1”. Then, noise can be reduced. On the other hand, when the data output to the output pin 27 does not change, the output data remains unchanged. That is, only when the output data changes, the output data can be temporarily set to the intermediate potential. Also, in the first embodiment of the present invention, the resistance 62
Although the intermediate potential varies due to the use of the resistor 63 and the resistor 63, an accurate intermediate potential can be created by using the internal step-down circuit in the second embodiment.

[0028]

According to the present invention, it is possible to speed up data output and reduce noise.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a conventional data output circuit.

FIG. 2 is a block diagram showing a read system of the SRAM according to the first embodiment and the second embodiment of the present invention;

FIG. 3 is a data output circuit diagram according to the first embodiment of the present invention.

FIG. 4 is a temporal comparison diagram between a data output according to a conventional technique and a data output according to the first embodiment.

FIG. 5 is a data output circuit diagram according to a second embodiment of the present invention.

[Explanation of symbols]

 1 ··· Output stage control switch circuit 2 ··· Output stage control switch circuit 3 ··· Latch circuit 4 ··· Latch circuit 5 ··· Output buffer 6 ··· Output buffer 7 · ... Output pin 8 ... Sense amplifier circuit 9 ... Gate control signal 21 ... Memory cell 22 ... Memory cell array 23 ... Row decoder 24 ... Column decoder 25 ····· Sense amplifier circuit 26 ··· Data output circuit 27 ··· Output pin 51 ··· Output stage control switch circuit 52 ··· Output stage control switch circuit 53 ··· Latch circuit 54 ····· Latch circuit 55 ···· Output buffer 56 ···· Output buffer 60 ···· XNOR circuit 61 ···· XOR circuit 62 ··· Resistance 63 ··· Resistance 64 ···・ Switch 5 ... Switch 66 ... gate control signal 67 ... word lines 68 ... bit lines

Claims (6)

[Claims] A latch circuit for holding output data; an output pin for outputting data held in the latch circuit; and a potential corresponding to data "1" only when the output data changes. A circuit for outputting an intermediate potential to a potential corresponding to data “0” to an output pin. 2. A latch circuit for holding output data, an output pin for outputting data held in the latch circuit, and a potential corresponding to data "1" only when the output data changes. A data output circuit for outputting an intermediate potential to a potential corresponding to data "0" to an output pin. 3. A latch circuit for holding output data, an output pin for outputting data held in the latch circuit, and a potential corresponding to data "1" only when the output data changes. A data output circuit comprising: an internal step-down circuit that outputs an intermediate potential to a potential corresponding to data “0” to an output pin. 4. A memory cell array in which a plurality of memory cells are arranged in a matrix, a word line commonly connected to memory cells in a same row in the memory cell array, and a memory cell in a same column in the memory cell array. A plurality of bit lines connected in common, a column decoder respectively connected to the bit lines, a sense amplifier circuit respectively connected to the bit lines, and a latch for holding output data from the sense amplifier circuit A circuit; an output pin for outputting data held in the latch circuit; and an intermediate potential between a potential corresponding to data “1” and a potential corresponding to data “0” only when the output data changes. And a circuit for outputting a signal to an output pin. 5. A memory cell array in which a plurality of memory cells are arranged in a matrix, a word line commonly connected to memory cells in a same row in the memory cell array, and a memory cell in a same column in the memory cell array. A plurality of bit lines connected in common; a column decoder respectively connected to the bit lines; a sense amplifier circuit respectively connected to the bit lines; and a latch circuit for holding data from the sense amplifier circuit An output pin for outputting data held in the latch circuit; and an intermediate potential between a potential corresponding to data “1” and a potential corresponding to data “0” only when the output data changes. A semiconductor memory device comprising: an output load circuit that outputs to an output pin. 6. A memory cell array in which a plurality of memory cells are arranged in a matrix, a word line commonly connected to memory cells in a same row in the memory cell array, and a memory cell in a same column in the memory cell array. A plurality of bit lines connected in common; a column decoder respectively connected to the bit lines; a sense amplifier circuit respectively connected to the bit lines; and a latch circuit for holding data from the sense amplifier circuit An output pin for outputting data held in the latch circuit; and an intermediate potential between a potential corresponding to data “1” and a potential corresponding to data “0” only when the output data changes. A semiconductor memory device comprising: an internal step-down circuit that outputs to an output pin.