JP3774756B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a high-speed, highly integrated semiconductor device that is composed of fine elements and operates at a low voltage suitable for a battery-operable semiconductor integrated circuit.

  Improvement of the degree of integration of a semiconductor integrated circuit (LSI = Large Scale Integration) has been promoted by miniaturization of a MOS transistor which is a constituent element thereof. When a so-called deep submicron LSI having an element size of 0.5 microns or less is used, an increase in power consumed by the LSI becomes a problem as the withstand voltage of the element decreases. For such a problem, it is considered that an effective means is to reduce the operating power supply voltage as the element is miniaturized. Since the current power supply voltage of LSI is 5V, the technology of mounting a voltage conversion circuit for stepping down the external power supply voltage on the LSI chip as means for configuring the LSI with fine elements is called IEE.・ E Journal of Solid State Circuits, Vol. 21, No. 5, 605-611 (1986) (IEEE Jounal of Solid-State Circuits, vol.21, No5, pp.605-611 , October 1986). In this case, the values of the external power supply voltage and the internal power supply voltage are 5 V and 3.5 V, respectively. As described above, the problem of power consumption is becoming apparent in a dynamic RAM (DRAM = Dynamic Random Access Memory) having the highest integration density among LSIs. In line with this trend, there is a movement to lower the external voltage of the LSI itself. For example, in a 64 megabit DRAM using a 0.3 micron processing technique, the external power supply voltage is expected to be lowered to about 3.3V. As the degree of integration increases, the external power supply voltage may further decrease.

  In recent years, with the widespread use of portable electronic devices, there is an increasing demand for low-voltage and low-power consumption LSIs that can perform battery operation and hold information in the battery. For such applications, an LSI that operates at a minimum of 1 to 1.5 V is required. In particular, in the case of a dynamic memory, the degree of integration has already reached the megabit level, and there is a movement to use the semiconductor memory also in the field of a mass storage device, which could conventionally only use a magnetic disk device. . For that purpose, it is necessary to back up with a battery so that data is not lost even if the power is turned off. This backup period usually needs to be guaranteed for weeks to years. For this reason, it is necessary to reduce the current consumption of the memory as much as possible. In order to reduce the power consumption, it is effective to reduce the operating voltage. However, if this is set to around 1.5 V, a single backup battery is sufficient as a backup power source, so the cost is low and the occupied space is also small.

  In CMOS (Complementary MOS) LSIs composed of only inverters and various digital logic circuits, such as processors, even if the power supply voltage is reduced to about 1.5V, the MOS transistor constant and threshold voltage can be selected appropriately. It is possible to operate with a power supply voltage as low as about 1.5 V without causing a significant performance degradation. However, in addition to the external power supply voltage (VCC or VSS), an intermediate voltage or a voltage exceeding those ranges is generated on the LSI, and in an LSI using it for operation, the power supply voltage drop is decisive. The performance was reduced. A typical example of such an LSI is a DRAM. Therefore, when an information device that operates at a low voltage is constituted by a plurality of types of LSIs such as a processor and a memory, as represented by DARM, a voltage other than the power supply voltage is generated and used for the operation. The low voltage operation of LSI is essential.

  When a DRAM is operated at a low voltage, the following three problems that have been conventionally used cause problems.

(1) A circuit for reading a minute signal read from a memory.

(2) A circuit for generating a high voltage for driving a word line necessary for making a MOS transistor constituting a memory cell sufficiently conductive and transmitting a signal without loss.

(3) A circuit that generates an intermediate voltage (VCC / 2) serving as a reference voltage when detecting a read signal from the plate electrode of the memory cell storage capacitor and the memory cell.

These conventional examples will be described in the following order.

(1) is as follows. As LSI is highly integrated and scaled up, the parasitic capacitance of the signal wiring increases, and thus the problem that the operation speed decreases is becoming apparent. In the case of a dynamic memory, the speed at which a minute signal read from each memory cell on the data line is amplified by the sense amplifier, and the input / output control line (common I / O) for reading information from the selected data line Line) occupies a large proportion of the operation speed of the entire memory, and a technology for increasing the speed is indispensable for improving the performance of the memory. Conventional input / output control circuits include, for example, IEE, Journal of Solid State Circuits, ESC 22 (1987), pages 663 to 667 (IEEE, Journal of Solid- State Circuits, Vol.SC-22, No5, October, 1987, pp 663-667), two MIS (Metal
Insulator Semiconductor (FET) type field effect transistors (FETs) are generally used, and a selection signal is applied to their gate electrodes to control the connection between the data line pair and the common I / O line pair.

  A conventional example of (2) is shown in FIG. This shows a circuit related to a DRAM memory cell array (MA) and a word driver (WD). FIG. 21 shows the waveform of each part. This circuit is disclosed in, for example, IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. sc-21, NO. 3, JUNE 1986, pp. 381-387.

  A conventional example of (3) is as follows. The DRAM system that precharges the data line to the VCC / 2 voltage has become the mainstream of DRAMs of 1 megabit or more together with the CMOS circuit due to features such as high speed, low power consumption, and noise resistance. An example of a conventional intermediate voltage generating circuit for generating the VCC / 2 voltage is described in IEEJ Journal of Solid State Circuits, Vol. 21, No. 5, pp. 643-648. (1986) (IEEE Journal of Solid-State Circuits, vol. 21, No. 5, pp. 643-648, Octorber 1986).

IEE, Journal of Solid State Circuits, SC 22 (1987), pages 663 to 667 (IEEE, Journal of Solid-State Circuits, Vol. SC-22, No. 5) , October, 1987, pp 663-667) IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. sc-21, NO. 3, JUNE 1986, pp. 381-387 I. E. E. Journal of Solid State Circuits, Vol. 21, No. 5, pp. 643-648 (1986) (IEEE Journal of Solid-State Circuits, vol.21, No. 5, pp.643-648, Octorber 1986)

The problems to be solved by the invention disclosed in this specification with respect to the above conventional example are as follows.

  First, the conventional example (1) is as follows. An example of the conventional method is shown in FIGS. 7 (a) and 7 (c). Since this method can be composed of a minimum number of transistors, it is effective in reducing the area of the entire memory, but has the following drawbacks. (A) If the I / O control MIS-FETs (T50, T51) are turned on before the signal voltage of the data lines (D0, D0￣) is sufficiently amplified, the operation of the sense amplifier SA0 is inhibited. Causes malfunction.

(B) For the above reason, it is necessary to put a time delay (timing margin) from when the sense amplifier is operated to when the selection signal Y01 is input and when the MIS-FET is turned on. FIG. 7 (c)).

(C) In order to prevent such a malfunction, there is a design restriction on the ratio between the channel conductance of the MIS-FET (conductivity between drain and source) and the channel conductance of the MIS-FET constituting the sense amplifier. To do. In general, it is necessary to make the former smaller than the latter, and it is difficult to increase the driving capability of the common I / O lines (IO0, IO0￣). Therefore, in addition to (b), the operation speed further decreases.

(D) As the degree of integration of the memory increases, the internal power supply voltage tends to decrease in order to cope with a reduction in power consumption and a decrease in the breakdown voltage of the element. Therefore, the driving capability of the MIS-FET is further reduced, and the operation speed is further reduced.

(E) It is difficult to write or read in parallel between one common I / O line and a plurality of data lines connected to the common I / O line mainly due to the reason of (c) above. Limited in terms of test function.

  For these reasons, the conventional input / output circuit method cannot provide a circuit method suitable for a highly integrated memory that operates at high speed even at a low voltage.

Next, the conventional example of (2) is as follows. As shown in FIG. 20, the word driver is composed of transistors QD and QT. Here, when the X decoder output N1 becomes a high level (VL), the gate N2 of the QD is charged through the QT and the QD is turned on. At this time, the voltage of N2 is VL-VT. Next, when the word line drive signal φX (amplitude is VL + VT or more) generated by the peripheral circuit FX becomes a high level, a current flows from the drain to the source of the QD, and the word line W is set to a high level. At this time, since the potential difference between the gate of QT and N1 is 0 and N2 is Vt, QT is cut off. Therefore, when φX rises, the voltage of N2 rises with φX due to coupling by the capacitance between the gate and source of QD. If the voltage between the gate and source of QD is equal to or higher than VT when φX reaches the maximum value, the voltage of the word line becomes equal to φX. On the other hand, when φX becomes lower than VT in the middle of the rise, the capacitance between the gate and source of QD becomes 0, so the rise of N2 stops at that point, and VL−VT + α as shown in FIG. (VL-2VT) / (1-α). The voltage of the word line is (V _DL -2V _T ) / (1-α). Here, α is the ratio of the gate capacitance of the QD to the total capacitance of the node N2.

  Here, consider a case where VL drops to 1.1 V due to battery consumption. If α = 0.9 and VT = 0.5 (V), the voltage of N2 is 1.5 V from the above equation. Therefore, the voltage of the word line only rises to 1.0V. Usually, since the threshold voltage of the switch transistor QS of the memory cell is higher than that of the peripheral circuit and becomes 0.5 V or more, the amount of charge stored in the memory cell is less than half of the maximum value (CS × 1.1) ( CS × 0.5), and soft error resistance and S / N of the sense amplifier are significantly reduced. That is, the stored data is easily destroyed.

  As described above, when trying to operate a battery with a DRAM using conventional technology, if the electromotive force of the battery decreases to nearly twice the threshold voltage VT of the MOS transistor, the word driver malfunctions, There is a problem that the write voltage is lowered and data is easily destroyed, and there is a problem that needs to be solved.

  Regarding (3), the following two problems occur in the conventional intermediate voltage generation circuit due to the low voltage and high integration. (A) As the power supply voltage decreases, the voltage setting accuracy decreases and the signal-to-noise (S / N) ratio deteriorates.

(B) Since the device operates in the source follower mode, the response speed is determined by the drive capability and load capacitance value of the transistor. For this reason, increase in load capacitance due to high integration and further reduction in voltage The response speed becomes slow due to a decrease in the drive capability of the element.

  FIG. 30 shows a conventional example of an intermediate voltage generating circuit for DRAM. Hereinafter, the above problem will be described with reference to FIG. In FIG. 30, TN5 and TN6 are N-channel MIS type FETs, TP5 and TP6 are P-channel MIS type FETs, R1 and R2 are resistors, and CL is a load capacitance. The circuit of FIG. 30 is a kind of complementary push-pull circuit, and TN6 and TP6 constitute a voltage dividing circuit that divides the power supply voltage VCC (VSS is a ground potential) into an intermediate voltage of HVC, and a bias voltage is applied to these gates. TN5 and TP5 for providing the above constitute a bias circuit. In the VCC / 2 precharge type DRAM, the load capacity is almost equal to the total data line capacity, 5 to 10 nF (nano-farad) for 4 megabit DRAM, 20 to 40 nF for 16 megabit DRAM, and 80 to 160 nF for 64 megabit DRAM. It is a value of the degree. In this circuit, the output is stabilized so as to have a constant voltage by always passing a minute current through each FET. If the current is very small, the voltage difference between the terminal 20 and the terminal 22, that is, V (20) −V (22) is substantially equal to the threshold voltage VTN of the FET TN5, and the voltage difference between the terminal 22 and the terminal 21, that is, V (22 ) -V (21) is substantially equal to the absolute value VTP of the threshold voltage of the FETTP5. Further, the gate width to gate length ratio W / L of the FETs TN6 and TP6 is selected to be several to several tens of times the W / L of TN5 and TP5, respectively. Therefore, the bias current of TN6 is several times to several tens of times the bias current of TN5.

First, the first problem will be described. Assuming that there is no difference in device characteristics (for example, threshold voltage, channel conductance per unit gate width, etc.) between the FET pairs TN5 and TN6 and TP5 and TP6, the output HVC has a terminal 22 A voltage equal to that of is obtained. The output voltage is
V (HVC) = R2 / (R1 + R2) × VCC−R2 / (R1 + R2) × VTN + R1 / (R1 + R2) × VTP
It is expressed. Here, VSS is assumed to be at the ground potential. Under standard conditions, the values of VTN and VTP are almost equal, and R1 = R2
V (HVC) = VCC / 2−VTN / 2 + VTP / 2
That is, when the difference between the values of VTN and VTP is negligible compared to the value of VCC, V (HVC) ≈VCC / 2
It becomes. In general, the variation in threshold voltage of an element does not decrease even with high integration and is considered to be constant. Therefore, as VCC decreases, the setting accuracy of V (HVC) decreases. For example, assuming that VTN and VTP each vary ± 0.1V with respect to the standard value, when the power supply voltage is 5V (HVC is 2.5V), the variation of the intermediate voltage is approximately ± 4%. When the power supply voltage is 1.5 V (HVC is 0.75 V), the fluctuation of the intermediate voltage reaches about ± 13%, which hinders stable operation of the memory.

Next, the second problem will be described. When charging / discharging the load, the output MISFET operates in the saturation region, so that its drain current ID is ID = β / 2 × (VGS−VT) ^2.
It is expressed. Here, VGS is a gate-source voltage, VT is a gate threshold voltage of MISFET, and β is a constant determined by the structure and dimensions of the element. Now, in the conventional circuit, the time tr required to raise the voltage of the load (load capacity = CL) from 0 V to 90% of the intermediate voltage VCC / 2 is tr = 18CL / β × 1 / (VCC / 2)
It is expressed. Assume that the number of memory cells connected to one data line is 256, and the capacitance value per data line is 0.5 pF. Since these values are almost constant as the memory becomes highly integrated, the value of the load capacity increases four times for each generation. For example, CL≈8.2 nF for a 4 Mbit DRAM, CL≈33 nF for 16 Mbit, and CL≈131 nF for 64 Mbit. On the other hand, when the power supply voltage is decreased from generation to generation, such as 5V → 3.3V → 1.5V, when β of MISFET is constant at 10 mA / V ² , the rise time tr is 5.9 μs → 36 μs → 314 μs. Each time it will increase by about 10 times. In order to keep the response speed constant, it is necessary to increase the β of MISFET 10 times for each generation. However, since there is a side effect of increasing the layout area and the steady current, the rise time is actually increased. It is impossible to keep tr constant.

The outline of the present invention will be briefly described as follows.

Arranged at the intersection of the first data line pair, the second data line pair, the first word line intersecting the first and second data line pairs, and one of the first word line and the first data line pair. A first memory cell including a first memory cell, a second memory cell disposed at an intersection of the first word line and one of the plurality of second data line pairs, and a third data line pair. A second memory array including: a second word line intersecting the third data line pair; and a second memory cell disposed at one intersection of the second word line and the third data line pair; A first circuit coupled to a first data line pair via a first MISFET pair; a first circuit coupled to the second data line pair via a second MISFET pair; and a third circuit coupled to the third data line pair via a third MISFET pair. A second circuit, and a Y decoder, wherein the first circuit Is arranged between the Y decoder and the first memory array, and operates so that the potentials of one and the other of the first MISFET pair become equal via the first MISFET pair, A first sense amplifier that amplifies a signal appearing on the first data line pair, and the second circuit is disposed between the first memory array and the second memory array, and is connected to the second MISFET pair. The second data line pair operates so that the potentials of one and the other of the second data line pair become equal, and the second data line pair operates so that the potentials of the one and the other of the third data line pair become equal via the third MISFET pair. Amplifies a signal appearing on the second data line pair via a precharge circuit and the second MISFET pair or a signal appearing on the third data line pair via the third MISFET pair And a second sense amplifier, No other memory array is arranged between the Y decoder and the first memory array.

The first circuit further includes a first signal line pair that couples the first MISFET pair and the first precharge circuit, and the first precharge circuit is coupled between the first signal line pair. And a second signal line pair coupled between the second MISFET pair and the third MISFET pair, and the second precharge circuit includes: And a fifth MISFET having a source / drain coupled between the second signal line pair.

The first precharge circuit includes a sixth MISFET having a source / drain coupled between one of the first signal line pairs and a precharge potential, the other of the first signal line pair and the precharge potential. And a seventh MISFET having a source / drain coupled between the second signal line pair and a source / drain coupled between one of the second signal line pair and the precharge potential. And an eighth MISFET having a source / drain coupled between the other of the second signal line pair and the precharge potential.

From another point of view, the first data line pair, the second data line pair, the first word line intersecting the first and second data line pairs, the first word line, and the first data line A first memory including a first memory cell disposed at an intersection with one of the data line pairs, and a second memory cell disposed at an intersection between the first word line and one of the plurality of second data line pairs. An array; a third data line pair; a second word line intersecting the third data line pair; and a second memory cell disposed at one intersection of the second word line and the third data line pair. A first circuit coupled to the first data line pair via a first MISFET pair and not coupled to the other data line pair; and a second MISFET pair coupled to the second data line pair. And coupled to the third data line pair via a third MISFET pair. A first circuit coupled to the first MISFET pair. The first memory array is disposed between the first circuit and the second circuit, and the first circuit is coupled to the first MISFET pair. A signal line pair; a first sense amplifier coupled between the first signal line pair; and a first precharge circuit coupled between the first signal line pair. The second circuit includes: A second signal line pair coupled between the second MISFET pair and the third MISFET pair; a second sense amplifier coupled between the second signal line pair; and the second signal line pair. A second precharge circuit coupled thereto.

With the above configuration, an optimum input / output circuit configuration can be obtained without greatly increasing the chip area as compared with the prior art.

  The present invention will be specifically described below with reference to examples. In the following description, an example in which the present invention is applied to a dynamic memory (DRAM) will be described. However, the present invention can be similarly applied to, for example, a static memory (SRAM) and a read-only memory (ROM). . In addition to a memory using a MIS type FET element, a memory using a bipolar element, a so-called BiCMOS type memory in which a bipolar element and a MIS-FET are combined, and a semiconductor material other than silicon are used. The same applies to the memory.

  1 to 6 show an embodiment of the memory circuit of the present invention. 1 to 6, MA is a memory cell array in which a plurality of memory cells each having one MIS-FET and one storage capacitor are two-dimensionally arranged, and CKT0 and CKT1 are memory cell signals or read lines. Or an input / output control circuit for exchanging information with the outside of the memory through the write line, a data line pair for transmitting signals between the D0 and D0 デ ー タ, D1 and D1￣ memory cells and the input / output control circuit, WD is a word line driving circuit for designating a row address in the memory cell array and supplying a driving signal to one word line, W0 to Wm are word lines, and YD is a column address in the memory cell array. Y (column) decoder, Y01 represents a column selection signal line. In the input / output control circuit, SA0 and SA1 are detection circuits (sense amplifiers) for detecting minute signal voltages on the data lines, and CSN0 and CSP0, and CSN1 and CSP1 drive the detection circuits SA0 and SA1, respectively. A signal line, CD0 or CD1 is a drive signal generation circuit for the detection circuit, and PR0 and PR1 are precharge circuits for short-circuiting the data line pair and setting a voltage convenient for the operation of the sense amplifier in a non-operating state, RG0 or RG1 is a read gate for reading the signal (voltage difference) appearing on the data line pair to the outside of the memory array, T1 to T4 are N-channel MIS-FETs constituting the read gate, WG0 or WG1 is an external Write gates for driving data lines according to information, T5 to T8 are N constituting one write gate Channels MIS-FET, RO0, RO0￣, RO1, RO1￣ are read lines, WI0, WI0￣, WI1, WI1￣ are write lines, RCS0, RCS0￣, RCS1, RCS1￣ are read control lines, WR0, WR0. ￣, WR1, WR1￣ respectively indicate write control lines. SWR0 and SWR1 are switch circuits for connecting the read lines to the common read lines CRO and CRO￣, and SWW0 and SWW1 are switch circuits for connecting the write lines and the common write lines CWI and CWI￣, SEL0 and SEL1 are signals for selecting one of the left and right switches. AMP is a sense amplifier for detecting and amplifying a signal appearing on CRO￣ and CRO, DOB is an output buffer, and DIB is an input buffer. In this embodiment, the input / output control circuits CKT0 and CKT1 are alternately arranged on the left and right of the memory cell array for each data line pair, and the I / O lines in the input / output control circuit are read lines (RO lines). And writing lines (WI lines). These specific configurations and effects will be described below.

  FIG. 2 shows a plan layout diagram of the read gate and write gate circuits. In general, as the integration of the memory increases, it becomes difficult to lay out the input / output control circuit Ci with a data line pitch. However, by arranging the input / output control circuits alternately on the left and right sides of the memory cell array as in this embodiment, the layout pitch of the input / output control circuits can be double the data line pair pitch, that is, 2 dy, so that the chip area is greatly increased. Layout is possible without making it happen. In highly integrated memories, for example, IEE Journal of Solid State Circuits, 23 (1988), pages 1113 to 1119 (IEEE, Journal of Solid-State Circuits, vol. 23, No. 5, October 1988, pp 1113 to 1119), there is a problem that the signal-to-noise ratio is remarkably lowered due to capacitive coupling between adjacent data lines. It is known that the capacitive coupling noise in the memory cell array portion can be reduced by a method such as crossing the data lines in the middle of the memory cell array. However, in the input / output control circuit unit, the coupling capacitance between adjacent data lines depends on the location. The noise was not sufficiently reduced because of the non-uniformity. In this embodiment, by providing a shield wiring between the data line pairs of the input / output control circuit, the line-to-line capacitive coupling noise can be significantly reduced as compared with the conventional case. This will be described below. In the layout of the input / output control circuit section as shown in FIG. 2, another signal wiring formed simultaneously with the data line is arranged between the data line pair. Here, for example, the read lines RO and RO￣ and the read control lines RCS and RCS￣ that are wired perpendicularly to the data lines in the read gate RGi portion are wiring materials formed simultaneously with the data lines through the through holes. Connected and arranged parallel to the data lines. By doing so, it is possible to reduce the parasitic capacitance between the data line and the adjacent data line, to minimize the noise accompanying the reading operation, and to achieve a stable operation.

  Next, specific configurations of the read switch SWR0, the write switch SWW0, and the sense amplifier circuit AMO will be described.

  FIG. 3A shows a configuration example of the read switch SWRi (i = 0, 1). This circuit selectively connects one of the plurality of read lines ROi and ROi￣ to the common read lines CRO and CRO￣ and controls the voltage of the read control lines RCSi and RCSi￣ of the selected memory block. Thus, a signal is taken out to the readout line. In the figure, T10 to T17 are N-channel MISFETs, INV100 is an inverter, and NAND1 is a two-input inverting AND circuit that outputs a low level only when the inputs are both at a high level. When the memory block is selected and the selection signal SELi is at a high level, and the memory is in a read state and the write signal WE is at a high level, the MISFETs T10 to T13 are turned on and T14 to T17 are turned off. Therefore, the read lines ROi and ROi￣ are connected to the common read lines CRO and CRO￣, respectively, and the read control lines RCSi and RCSi are grounded. Thus, for example, when the column selection signal Y01 becomes high in FIG. 1, T3 and T4 are turned on, and the read control lines RCS0 and RCS0 are read from the read lines RO0 and RO0￣ according to the voltage difference between the data line pair D0 and D0￣. A signal is obtained as a difference between currents flowing through the ridges. Here, the read control lines RCS0 and RCS0 are not necessarily separated when only the read operation is considered. However, the separation is indispensable when performing a parallel test as will be described later.

  When the memory block is deselected and the selection signal SELi is at a low level, or when the memory is in a write state and the write signal WE￣ is at a low level, the MISFETs T10 to T13 are nonconductive and the T14 to T17 are conductive. Therefore, the read lines ROi and ROi￣ and the read control lines RCSi and RCSi￣ are connected to the same voltage (in this case, the intermediate voltage HVL). Thus, for example, even if the column selection signal Y01 becomes high in FIG. 1 and T3 and T4 are turned on, no current flows from the read lines ROi and ROi￣ to the read control lines RCSi and RCSi￣. As described in FIG. 10, it is convenient when a column address of a plurality of memory blocks (including a selected block and a non-selected block) is selected by one column selection signal line.

  FIG. 3B is a configuration example of the write switch SWWi (i = 0, 1). This circuit selectively connects one of the plurality of write lines WIi, WIi￣ to the common write line CWI, CWI￣, and sets the write control line Wri of the selected memory block to the high level to perform writing. To do. In the figure, T20, T23 to T26 are N-channel MISFETs, T21 and T22 are P-channel MISFETs, INV101 to INV103 are inverters, and NAND2 is a 2-input inverting AND circuit. When the memory block is selected and the selection signal SELi is at a high level, and the memory is in a write state and the write signal WE is at a high level, the MISFETs T20 to T23 are turned on and T24 to T26 are turned off. Therefore, the write lines WIi and WIi￣ are connected to the common write lines CWI and CWI￣, respectively, and a high level is output to the write control line WRi. Thus, for example, in FIG. 1, when the column selection signal Y01 becomes high level, T5 and T6 become conductive, the data line pair D0, D0￣ is connected to the write lines WI0, WI0￣, and the write information on the write line is the data line. Is written to.

  When the memory block is deselected and the selection signal SELi is at a low level, or when the memory is in a read state and the write signal WE is at a low level, the MISFETs T20 to T23 are nonconductive and the T24 to T26 are conductive. Therefore, the write lines WIi and WIi￣ are connected to the same voltage (here, the intermediate voltage HVL), and the write control line WRi is at a low level. Thus, for example, even if the column selection signal Y01 becomes high in FIG. 1 and T5 and T6 are conducted, the data line and the write line are not conducted. For example, as shown in FIG. This is convenient when the column address of a plurality of memory blocks (including selected blocks and non-selected blocks) is selected by a signal line.

  Next, FIG. 4 shows a configuration of a sense amplifier circuit for amplifying signals read out to the common read lines CRO and CRO￣. In the figure, amp1 is a first sense amplifier circuit that inputs common readout lines CRO and CRO￣ and outputs d1 and d1, and amp2 is a second sense amplifier that receives d1 and d1￣ and outputs d2 and d2￣. A sense amplifier circuit, amp3 is a third sense amplifier circuit with d2 and d2￣ as inputs and d3 and d3￣ as outputs, and T42 and T43 are MISFETs for initializing the third sense amplifier circuit before operation. . The first sense amplifier circuit amp1 is composed of two current-voltage conversion circuits having the same configuration. The current-voltage conversion circuit includes a differential amplifier circuit DA1, a P-channel MISFET T30, and an N-channel MISFET T31. The second sense amplifier circuit amp2 includes two differential amplifier circuits DA3 and DA4 having the same configuration. The third sense amplifier circuit amp3 includes two inverting OR circuits MOR1 and NOR2, and two inverters INV105 and INV106.

  Next, the operation of the present embodiment will be described using the operation waveforms of FIGS. Here, an example in which information read out to the data lines D0 and D0 読 出 し is read or information from the outside is written into D0 and D0￣ will be described, but the same operation is performed for all the memory arrays. Obviously, this can be done selectively for memory cells. Although the case where the operating voltage is 1.5 V has been described here, the present invention is not limited to this, and the present invention can be similarly applied and the same effect can be obtained even when operated at other voltages.

  First, the reading operation will be described with reference to FIG. The control signal PC of the precharge circuit part PR0 falls at time t0, and the precharge operation to the data line is completed. Subsequently, the selected word line W0 rises at t1, and a signal is read from the memory cell to the data lines D0 and D0￣. Next, at t3, the sense amplifier drive signal CSP is changed from the intermediate potential to the high level, the CSN is changed from the intermediate potential to the low level, and the sense amplifier SA0 is driven. As a result, the signal read out to the data line is amplified to high and low by the sense amplifier. In this embodiment, the data line is connected to the gates of the transistors T1 and T2 in the read gate RG0, and is connected to the read lines RO0 and RO0 through the transistors T3 and T4. The read control lines RCS0 and RCS0￣ of the selected input / output circuit CKT0 are driven low at t1. Since the data line and the readout line are separated by this configuration, the information on the data line can be obtained even if the column selection signal line Y01 is input at t3 in the middle of amplification before the data line is determined to be high or low level. There is no destruction. Therefore, since the information on the data line can be transmitted to the read line without destroying it, the read operation can be speeded up. The reason why the speed can be increased compared to the conventional case and the effect will be described in detail later. Here, the signal voltage of the readout line and the common readout line, that is, the voltage difference between RO0 and RO0￣ and CRO and CRO￣ is about 20 mV, and the output signal amplitude of the first sense amplifier circuit (voltage difference between d1 and d1￣) Is about 200 mV, and the output signal amplitude (voltage difference between d2 and d2￣) of the second sense amplifier circuit is about 1 to 1.5V. That is, the voltage amplification factor of the first sense amplifier circuit is about 10, and the voltage amplification factor of the second sense amplifier circuit is about 5-7. The voltage amplification factor of the third sense amplifier circuit is about 1-2. However, the third sense amplifier circuit has a function of storing output information, that is, a so-called latch function. That is, by amplifying an input signal and setting both inputs to low, an output corresponding to the previous input is held until the next input is input. As a result, it is not necessary to keep all the first to third amplifier circuits in an operating state, and after output, the first and / or the second amplifier circuit is made non-operating to reduce power consumption. can do.

  This figure also shows an example of a so-called static column operation in which after reading one piece of information, the column address is switched to read other pieces of information. That is, information is read by raising Y23 after the column selection signal Y01. According to the present embodiment, as will be described later, by using the input of the sense amplifier circuit as a current, the voltage amplitude of the readout line and the common readout line is reduced to 20 mV, which is 1/10 of the conventional one. As a result, the time required for charging and discharging the parasitic capacitances of the readout line and the common readout line can be reduced to about 1/10, and the delay from the address switching to the output of information can be extremely reduced.

  Next, an example in which a write operation is performed following a read operation will be described with reference to FIG. In this figure, the first read operation is the same as in FIG. When WE becomes high at t4, the column selection signal line Y01 remains High, the control signal line RCS0 of RG0 becomes HVL (0.75 V), and the control signal line WR0 of the write gate WG0 becomes “High”. At the same time, when write data is applied to the write input / output lines WI0 and WI0￣, data is written to the data lines D0 and D0￣ through the transistors T5, T7, T6, and T8 in the write gate WG0.

  As shown in the above example, as one means for changing the transfer impedance between the I / O line and the data line in the write operation and the read operation, the read operation margin is separated by separating the read line and the write line. Since the write operation margin can be set individually, the operation can be speeded up and stabilized even in the low voltage operation.

  Next, the effect of the sense amplifier circuit used in this embodiment will be described with reference to FIGS. FIG. 7A schematically shows the configuration of a conventional sense amplifier circuit, and FIG. 7B schematically shows the configuration of the sense amplifier circuit according to the present invention. FIG. 7C schematically shows operation waveforms of the conventional sense amplifier circuit and the sense amplifier circuit according to the present invention. In the conventional circuit, a minute signal read from the memory cell MC to the data lines (D0, D0￣) is amplified by the sense amplifier SA0, and then the MISFETs T50, T51￣ controlled by the column selection signal Y01 are turned on. Then, it was transmitted to the read lines (IO0, IO0￣). The conventional circuit has two problems that hinder speeding up. One is that the MISFET needs to be turned on after being sufficiently amplified by the sense amplifier. Otherwise, there is a capacitance difference of several tens of times between the data line (CD about 0.3 pF) and the readout line (CR about 8 pF), so a large charge flows from the readout line, and the information that has already been amplified is destroyed. It is because it ends up. The other is a sense amplifier having a small driving capability, and it is necessary to amplify a large parasitic capacitance read line to a large voltage of 200 mV. This is because of the signal detection sensitivity of the second sense amplifier circuit at the next stage.

  Therefore, in the present invention, the NMOS transistors T1 and T2 that receive the signal of the data line at the gate are provided, and the sense amplifier and the read line are separated. As a result, the MISFETs T3 and T4 controlled by the column selection signal can be turned on without waiting for the data line to be sufficiently amplified. Therefore, the voltage information on the data line is converted into current information and read at high speed. You can start. Furthermore, a current sense circuit achieved by a P-channel MISFET and an amplifier circuit is provided so as to be suitable for low voltage operation, so that a voltage output proportional to the current input can be obtained. By using a current input, the voltage amplitude of the signal line can be reduced by about an order of magnitude (200 mV → 20 mV) compared to the conventional case, and the time required for charging and discharging the parasitic capacitance CR is greatly shortened and speeded up. Is done.

  FIG. 8 compares the operating speeds of the conventional sense amplifier circuit and the sense amplifier circuit according to the present invention based on the computer simulation results. Here, the sense time is a delay time from when the signals CSN and CSP for starting the sense amplifier are turned on until a signal voltage of 200 mV is obtained on the I / O line (conventional case), or the first time The delay time is defined until the output of the sense amplifier circuit is 200 mV (in the case of the present invention). With the circuit of the present invention, the speed is increased by 20 ns at 1.5 V compared with the prior art, indicating that the present invention operates at a low voltage and at a high speed.

  As described above, in this embodiment, the input / output control circuits are alternately arranged on the left and right sides of the memory cell array, and the reading and writing input / output lines are separated, so that the operation can be performed even in the low voltage operation. Speeding up and stabilization can be achieved. Further, the first sense amplifier circuit for detecting the signal on the read line is constituted by a current-voltage conversion circuit, and the MISFET for driving the read line and the MISFET for converting the voltage on the data line into the current on the read line are complementary. With this configuration, it is possible to provide a sense amplifier circuit that operates at a high speed even with a low power supply voltage of about 1 to 2V.

FIG. 9 shows an embodiment for further stabilizing the operation. As described above, in the input / output control circuit section, the parasitic capacitance between the data lines can be reduced. Here, the operation is further stabilized by balancing the parasitic capacitance between the data lines in the memory cell array section. That is, the data lines are crossed at the center of the memory cell array for each pair of lines. The parasitic capacitances between D1, D1￣ and data line D0￣ are Cc01 _L and Cc01 _R , respectively. However, since Cc01L and Cc01R match, the parasitic capacitance between D1, D1￣ and data line D0￣ can be made equal. Similarly, since the parasitic capacitance between D1 and D1￣ and the data line D2 can be made equal, the parasitic capacitance with the adjacent data line can be balanced between the paired data lines. Therefore, the reading operation can be further stabilized in the memory cell array.

FIG. 10 shows an embodiment in the case where a plurality of memory cell arrays exist. Here, the reading operation will be described. The input / output control circuit CKTij is shared by the left and right memory cell arrays, switch transistors indicated by T60 to T63 are connected between CKTij and each memory cell array, and SHRij, which is a memory cell array selection signal, is connected to their gates. Is entered. SWRi is a switch connected to a read line RO and a common read line CRO shared by a plurality of RO lines, and a memory cell array selection signal SHRij is also input to this switch. SHRij is set to High in advance. For example, when the memory cell array MA2 is selected, only SHR1 _R and SHR3 _L are set to Low. Here, if the column selection signal Y01 is selected, the signals read to the data lines D1, D1￣ and D0, D0￣ are read to the RO12, RO12￣, RO23, RO23￣ through the input / output control circuits CKT12, CKT23. It will be. These are further read out to the common I / P lines CRO0, CRO0Ｐ, CRO1, CRO1￣ through the switches SWR1 and SWR2. As described above, even when there are a plurality of memory cell arrays, it is possible to arrange the input / output control circuits alternately on the left and right sides of the memory cell array and share them with the left and right memory cell arrays without greatly increasing the chip area. Improvement of the characteristics described above can be realized.

  FIG. 11 shows an embodiment of a parallel test using the present invention. The parallel test is performed by simultaneously selecting a plurality of column selection signals (multiple selection). That is, during the parallel test, the column selection signal is selected in multiple by the test signal TEST. Thereby, in the read operation, the read signal of the data line is simultaneously read on the read line according to the multiplicity. If all the information of the data lines read out at the same time is coincident, one of the read lines RO and RO￣ has a “High” voltage level and the other has a “Low” voltage level according to the read information. . If even one piece of erroneous information is read, both RO and RO￣ are at the “Low” voltage level. On the other hand, in the write operation, data is written to the data line connected to the write gate selected from the input / output line for writing. Here, in the present invention, a parallel test can be performed without providing a new test I / O line even in the case of a parallel test, and information is transmitted from the data line to the AMP as in the normal test. In addition, since the signal line for reading and the signal line for writing are separated, the operation margin can be set individually for the reading operation and the writing operation as described above, and there are no restrictions on increasing the multiplicity. Loss, enabling highly parallel read / write. In the figure, the driving signal RCS of the reading gate RG is a paired line, and the RCS connected to the reading lines RO and RO￣ is separated in the reading operation. This is an effective means for discriminating one misread when the multiplicity is increased. When the multiplicity is increased, it is necessary to increase the current flowing from the RO to the RCS. On the other hand, the current flowing from RCS to GND is saturated at a certain level due to the wiring resistance of the readout line. In other words, the RCS potential rises. Therefore, if the RCS is not separated, the signal current of the I / O line on the side that has been erroneously read decreases as the multiplicity increases, making detection difficult. By separating RCS, the potential of the RCS on the side misread is not increased, and only the current flowing from RO to RCS needs to be detected, so detection with higher accuracy can be performed. As described above, the present invention enables a highly parallel test, so that the test time can be greatly shortened.

  FIG. 12 shows an example of a specific circuit for determining the multiplicity. Usually, Y0 to Yn-1 are inputted to the column decoder YD. Yn-1 divides the column direction into two, Yn-2 further divides each into two, and so on. Y0 repeats “0” (Low) and “1” (High) for each column selection signal. Here, the test signal TEST is set to High, and the OR gate output signals of Yn−1￣, Yn−1 and TEST are AYn−1 and AYn−1 ′, which are replaced with Yn−1￣ and Yn−1. By inputting to the decoder, both AYn-1 and AYn-1 'can be set high regardless of Yn-1 high and low, and two column selection signals can be selected, so that the multiplicity can be set to two.

FIG. 13 shows an embodiment in which the multiplicity is four. The multiplicity can be set to 4 by inputting the NAND gate outputs of Yn-1 and Yn-2 to the NAND gate together with the TEST, changing their outputs from AYn-20 to 3, and inputting them to the column decoder. As described above, based on the embodiment shown in FIGS. 12 and 13, multiple column decoders can be selected during the parallel test, and one column selection signal can be selected by setting the test signal TEST to low during the normal test. . FIG. 14 shows an embodiment of a sense amplifier circuit for realizing a parallel test. A method for outputting the test result during the parallel test will be described with reference to FIG. In a normal read operation, the outputs after current-voltage conversion are input as they are to the inverting and non-inverting inputs of the two differential amplifier circuits DA4 and DA5 constituting the amp2T, and these outputs are input to the amp3. During parallel test to the non-inverting inputs of the two differential amplifier circuit DA4, DA5 inputs the V _RT as the reference voltage. In the parallel test, if even one erroneous data is included in the multiple selected data lines, current flows through both RO and RO. Therefore, the current-voltage conversion outputs d1 and d1￣ of the first sense amplifier circuit amp1 are both at a low level. On the other hand, the reference voltage _VRT is set to a voltage between the high level and the low level of the current-voltage conversion output. In this way, when even one piece of erroneous information is included, a high level is output to the outputs of the two differential amplifier circuits DA4 and DA5. That is, when both d2 and d2 are high, it can be determined that the information read in parallel includes erroneous information. At the time of the parallel test, these outputs are taken into the determination circuit TEST by setting TESTＴＥ to Low. TEJ outputs high or low to ERR according to the output voltage of d2 and d2￣. That is, if all the parallel test results are correct, ERR outputs Low, and if one is wrong, it outputs High. In this way, discrimination of parallel test results with increased multiplicity can also be performed using the input / output circuit system and sense amplifier circuit according to the present invention.

FIG. 15 shows an embodiment of a reference voltage _VRT generation circuit used for the parallel test. In the same figure, the current-voltage conversion circuit described above is used, and _VRT is generated by setting the parallel test signal TEST to High during the parallel test. In this circuit, a reference current corresponding to about half of the signal current is applied to the input of the current-voltage conversion circuit. If this the signal current flows in both RO lines, the converted voltage is smaller than V _RT. If the result of the parallel test is correct, the voltage after one conversion becomes larger than _VRT . Therefore, the test result can be determined by comparing the converted voltage with the VRT.

  FIG. 16 shows a specific example of the write switch SWW. WE is a write signal. This embodiment is based on the case where there are a plurality of memory cell arrays based on FIG. 10, and it is assumed that the memory cell array on the right side of SWW operates (SELR is High and SELL is Low). TEST is Low during parallel test. During the reading operation, WE is Low, and WI and WI are set to the same potential by the circuit WST. When the write operation is started, WE becomes High. Since all signals input to the GR are high during the reading operation, WER is low and one WEL is high. Therefore, the write control signal WR becomes High, and data is written from CWI, CWI to WI, WI￣ through N-channel MISFETs T77, T78 and P-channel MISFETs T75, T76.

FIG. 17 shows an embodiment in which the voltage level of the power supply line on the high voltage side of the sense amplifier for detecting and amplifying the signal read from the memory cell to the data line can be arbitrarily set. The write voltage level when writing “1” to the memory cell is the voltage level of the power line on the high voltage side of the sense amplifier. Therefore, it is sufficient that the voltage level of the power supply line on the high voltage side can be arbitrarily set. Here provided two power supply wiring of the high voltage side, used for normal write one of the power lines as V _DL. The other power supply wiring V _DM can be arbitrarily set from the outside of the chip, for example. Thus, if the signals MT0 and MT1 are set to Low, the sense amplifier drive signal CSP can be set to V _DL , and conversely if the signals MT0 and MT1 are set to High, the sense amplifier drive signal CSP can be set to V _DM . According to the present embodiment, only the voltage level of information “1” can be set arbitrarily. Furthermore, the voltage level of the information “1” can be set by changing every other pair. Therefore, as in the case of testing the coupling noise between the data lines, it is possible to write a marginal voltage at which information is inverted every other pair, which is effective when a margin test is desired. In addition, the test time such as the information retention characteristic of the memory cell can be shortened.

  18 and 19 show an embodiment of a word driving circuit according to the present invention. The feature of this embodiment is that a static word driver composed of QD1, QD2, QP, and QT is used in place of the conventional dynamic word driver. In addition, a voltage conversion circuit VCHG that always generates a voltage higher than the data line voltage VL by VT of the switch transistor QS of the memory cell is provided as the power source. The operation of this embodiment will be described below.

  First, when the X decoder XD is selected by the address signal Ai, its output N1 becomes Low level. Then, the charge at the node N2 is pulled out through the transistor QT, and N2 also goes to the low level. Then, the transistor QD1 is turned on and the word line W is raised to the level of VCH. Since the level of VCH is equal to or higher than VL + VT (QS), the maximum voltage VL is written in the memory cell CS.

  Next, in the precharge cycle, φ￣P first goes low, thereby turning on QP and setting node N2 to VCH. Then, since QD1 is turned off and QD2 is turned on, the word line W becomes a low level and electric charge is held in the memory cell.

  As described above, in this embodiment, the gate voltage of the drive transistor operates at a low level, so that it operates stably as a word driver even when the power supply voltage is lowered.

  FIG. 22 shows a specific example of the word line voltage conversion circuit VCHG of FIG. FIG. 23 shows the internal waveform and input timing when the circuit is activated. The feature of this embodiment is that the charge pump circuit feeds back to the output voltage precharge transistor (QB in FIG. 22) in order to obtain a fast rise and a high output voltage even with a low power supply voltage. The operation will be described below.

  First, consider a case where the input pulses φ and φ￣ are High and Low, respectively. At this time, the voltage of the node B is VL-VT because it is charged from VL through QC. On the other hand, the node A has a value determined by the electric charge stored in the capacitors CA and CD and the amplitude of φ. In this embodiment, this voltage is assumed to be VL. Next, when the voltages of φ and φ￣ are switched, the node B is boosted by CB and becomes VL−VT + αVL. Where α is the ratio of the total capacity of CB and Node B. At this time, the voltage of the node A becomes a voltage VL−2VT + αVL that is lower than the voltage of B by the VT of QA.

  Next, when the voltages φ and φ￣ are switched again, the node A is boosted again. If it is higher than VL by δ at this time, the voltage at node B is precharged to VL-VT by QC, so QB is turned on and the voltage at node B is further increased by δ. Therefore, the node B is further boosted in the next cycle, and the voltage at the node A is further increased. While repeating the above, the voltage at the node A rises and finally reciprocates between VL and 2VDL.

  When this output is connected to a rectifier circuit indicated by 2, that is, a diode-connected MOS transistor QD, and a smoothing capacitor CD is further inserted to the output, a boosted DC voltage VCH is obtained. This output voltage is 2VL-VT in a no-load state.

  Here, the circuit connecting QA and CA is divided into two. If one of the output points of each circuit, that is, one of the connection points of QA and CA is connected to the rectifier circuit 2 and the other is connected to the gate of QB, QB Since the gate is separated from the load circuit, the gate voltage becomes so high that no current flows through the load circuit, and the voltage at node A can be raised even faster.

  The feature of this circuit is that, as described above, the output voltage is fed back to the precharge circuit so that the precharge voltage can be increased and a high output voltage can be obtained even with a low power supply voltage. For example, when VL = 0.8 (V) and VT = 0.5 (V), when there is no feedback, that is, when there is no QB, the voltage of the node B is 1.1 V at the maximum (when α = 1, 2 VL -VT), and as a result, node A is 1.4V (3VL-2VT) and VCH is 0.9V (3VL-3VT). On the other hand, when there is QB, 1.6V (2VL), 1.6V (2VL), and 1.1V (2VL-VT) are all higher than the former.

  FIG. 28 shows the result of comparison of the boosting rates with and without the feedback transistor QB (in the present invention) and without (conventional method) by computer simulation. Here, the solid line indicates that the threshold voltage of the transistor is standard, and the broken line indicates that the threshold voltage is low. From this figure, it can be seen that in all of the conventional methods, the power supply voltage drops sharply at 1 to 1.5 V, whereas in the present invention, it is constant up to 0.8 V and operates stably even at a low power supply voltage. . Here, it is assumed that the rectifier circuit has no voltage effect due to the threshold voltage of the transistor.

  The embodiment shown in FIGS. 24 and 25 is a circuit for obtaining a higher output voltage. The feature of the present embodiment is that the gate voltage is synchronized with the output voltage of the charge pump circuit in order to reduce the voltage drop in the rectifying transistor, and when the output is at the high level (2 VL), it is higher by VT or higher than that. The level (VL) means VL.

  In FIG. 24, CP and QD are the above-described charge pump circuit and rectifier circuit. Further, Q1 to Q19 and C1 to C4 are added elements, Q1 is a rectifying transistor, Q3 to Q10, C1 to C3 are circuits for controlling the gate voltage of Q1, Q11 to Q13, Q15 to Q18, and C4 are gate boosters. The capacitor C3 charging circuit, Q19, is a precharge transistor for speeding up the rise of VCH. PA and PA￣ are control signals for the charge pump circuit, and PB and PB￣ are control signals for the gate voltage control circuit. The operation will be described below.

  1 is that the voltage at the node A is boosted and reciprocates between VL and βVL (β≈2) when PA and PA are alternately switched to High and Low by the charge pump described above. At this time, as shown in FIG. 25, PA and PA￣ are set such that the High periods do not overlap each other. In FIG. 22, when φ￣ corresponding to PA￣ is not fully reduced to 0V and the voltage at node B is still higher than VL + VT, φ corresponding to PA rises and the voltage at rising node A rises. Then, since QA is in an ON state, the charge stored in CA leaks to the power source side through QA.

  Next, in the rectifier circuit, when PA and PB are Low, and PA￣ and PB￣ are High, the gate of Q4 is boosted to VL + VT or more by C1, so the voltage of the gate G of Q1 is equal to VL. . At this time, since node A is VL, there is no back flow from VCH to node A. The gate of Q11 becomes 3VL-VT because C4 is precharged to VCH (2VL) -VT by Q13 and Q18 and then boosted by PA￣ (VL). Therefore, if VL ≧ 2VT, the voltage is boosted to VCH (2VL) + VT or more, and the node C becomes VCH. At this time, the gate-source voltage of Q10 is VCH-VL and exceeds VT, so it is turned on and the gate voltage of Q9 becomes equal to node C. Therefore, Q9 is turned off and no current flows from node C to node G.

  Next, when PA and PB are High, PA￣ and PB￣ are Low, Node A is 2VL, and Node C is VL + VCH. On the other hand, since the gate of Q7 is boosted to VL + VT or more by C3, its source becomes VL. That is, since the gate of Q9 becomes VL, the voltage between the gate and the source becomes VCH, Q9 is turned on, and the gate of Q1 becomes VL + γVCH (γ≈1). Therefore, 2VL is output as it is without dropping by VT as in the embodiment of FIG.

  In this embodiment, PB is set to the low level before PA. However, when the gate voltage of Q1 is still higher than VL + VT, PA becomes low and the voltage at node A becomes VL. This is to prevent the charge from flowing back to the node A. The reason why the minimum potential of the gate control circuit is set to VL like the sources of Q4 and Q7 is to reduce the potential difference between the electrodes of the transistor. As a result, the potential difference between the electrodes becomes 2 VL or less, and the same fine transistor as other parts can be used.

  The above is the feature of the embodiment shown in FIG. 24. In FIG. 24, the same effect can be obtained by removing Q7 and Q10 and connecting the gate of Q9 to the gate of Q4. For example, when PB is VL and PB￣ is 0, the gate of node C is VCH + VL, Q4, Q9 is VL, so Q4 is off, Q9 is on, and node G is VCH + VL. On the other hand, when PB is 0 and PB￣ is VL, node C is VCH (2VL), and the gates of Q4 and Q9 are 2VL. Therefore, Q4 is on, Q9 is off, and node G is VL.

  26 and 27 are circuits for generating the timing of FIG. In FIG. 26, inverters I5 to I8, resistor R2, capacitor C2, NAND gate NA2, and NOR gate NO1 are circuits for preventing the overlap of PA and PA￣, and I2, I3, R1, and C1 are delays of the fall of PA and PB. Circuits for determining time, I9 to I13, NA3 are circuits for creating a delay at the fall of PA and PB. I14 to I25 are buffer inverters. This may be any number of stages as long as the odd number of stages is the same, and may be adjusted according to the magnitude of the load. FIG. 27 is a circuit example for generating the input pulse OSC of the circuit. This circuit is generally called a ring oscillator. The feature of this circuit is that the time constants of R and C are made sufficiently larger than the delay time of the inverter in order to suppress the fluctuation of the oscillation frequency due to the power supply voltage. For this reason, even if the ratio of the VT of the transistor to the power supply voltage is 1 to 3 or less and the delay time of the inverter has a large power supply voltage dependency, the oscillation frequency becomes stable.

In addition to the measures described above, the operation at a lower voltage is further stabilized by lowering the VT of the transistors of the embodiments of FIGS. This is because the driving capability of the transistor increases due to the low VT. Although the subthreshold current increases as the VT is lowered, the number of elements of the voltage conversion circuit is about several tens at most, which is almost negligible when viewed from the whole chip. On the other hand, the driving capability of the word driver and the memory cell also increases due to the low VT. However, since the former uses 10 ³ to 10 ⁴ of the M-bit class DRAM, the leakage current flowing in the transistor off state cannot be ignored. In the latter case, the problem is that the charge retention time is shortened and the refresh interval must be shortened. This leads to the largest increase in power consumption. Therefore, it is best to set VT at a low voltage conversion circuit, word driver at a standard, and memory cell higher than a standard.

  As described above, according to this embodiment, the gate voltage of the rectifying transistor can be made higher than the drain voltage by the threshold voltage VT or more, and the backflow of charges can be prevented. The value can be increased to 2 VL. Further, by using an oscillation circuit and timing generation circuit using RC delay, the oscillation frequency and the delay time between timings are stabilized against fluctuations in the power supply voltage, so that the voltage conversion efficiency can always be in the best state. Further, by providing three types of transistor VTs, the voltage conversion circuit is low, the word driver is standard, and the memory cells are higher than standard, stabilization at low voltage, high speed, and low power consumption can be achieved. Therefore, it is possible to realize a semiconductor integrated circuit that operates stably even when the power supply voltage is an electromotive force of one battery.

Next, an embodiment in which the present invention is applied to an intermediate voltage generating circuit will be described. In the following description of the embodiment, VCC is used as a symbol representing the higher power supply voltage, but it is not necessary to be different from the VL used so far, and it can be replaced by VL as it is. Further, although HVC is used as a symbol representing the intermediate voltage, it does not have to be different from the HVL used so far and can be replaced by HVL as it is. FIG. 29 is a configuration example of a voltage follower circuit according to the present invention. This circuit outputs a voltage substantially equal to the voltage applied to the input and drives a large load capacity. In FIG. 1A, reference numeral 1 denotes a first complementary push-pull circuit, which is composed of an N-channel MOS transistor TN2, a P-channel MOS transistor TP2, and bias voltage sources VN1 and VP1. Reference numeral 2 denotes a current mirror type push-pull amplifier circuit, which is composed of an N channel MOS transistor pair TN1 and TN3 and a P channel MOS transistor pair TP1 and TP3 forming a current mirror circuit. Reference numeral 3 denotes a second complementary push-pull circuit, which includes an N-channel MOS transistor TN4, a P-channel MOS transistor TP4, and bias power supplies VN2 and VP2.

The constant setting of various transistors and voltage sources in this circuit and the operation in the steady state will be described. The values of voltage sources VN1 and VP1 are selected to be approximately equal to the gate threshold voltages of transistors TN2 and TP2, respectively. This prevents both transistors TN2 and TP2 from being cut off simultaneously under any operating condition. For this reason, it is possible to prevent the output impedance from becoming high and the potential not being determined or the output voltage from fluctuating depending on the load condition. By making the value of the voltage source approximately equal to the gate threshold voltage of the transistor, the current flowing through the two transistors in a steady state is suppressed to a low value, and the standby power of the integrated circuit is reduced while being high. The load drive capability is obtained. An operation under such a bias condition is generally referred to as a class AB operation. Assuming that the current values flowing in TN2 and TP2 are IC1 and ID1, respectively, these currents are supplied to TP3 by a current mirror circuit composed of a P-channel MOS transistor pair TP1 and TP3 and an N-channel MOS transistor pair TN1 and TN3, respectively. Is converted into a current ID2 flowing through TN3 and a current ID2 flowing through TN3. The current ratio of IC1 and IC2 is substantially equal to the β ratio of transistors TP1 and TP3, and the current ratio (mirror ratio) of ID1 and ID2 is substantially equal to the β ratio of transistors TN1 and TN3. That is,
M _p = IC2 / IC1 = β _TP3 / β _TP1
M _N = ID2 / ID1 = β _TN3 / β _TN1
It is. By setting this ratio to a value of 1 or more, it is possible to amplify the current and increase the drive capability of the next stage load (terminals 6 and 7). In the present invention, this ratio is selected to be about 1 to 10. Similar to the first push-pull circuit, the values of the voltage sources VN2 and VP2 are set to be approximately equal to the gate threshold voltages of the transistors TN4 and TP4, respectively. As a result, the second push-pull circuit also performs class AB operation.

  Now, what happens when the first push-pull circuit deviates from a steady state, that is, a state where IC1 = ID1 is established. The current value when the output voltage is forcibly changed from the steady state by the voltage δV is expressed as follows.

IC1−ID1 = − (√ (2β _N I) + √ (2β _P I)) × δV + (βN−βP)
/ 2 × δV ²
Here, β _N and β _P represent β of the transistors TN2 and TP2, respectively, and I represents a current flowing through the first push-pull circuit in a steady state (ie, I = IC1 = ID1).

For the sake of simplicity, assuming that the characteristics of TN2 and TP2 are almost the same, and β _N and β _P are equal (β = β _N = β _P ), the above equation is IC1−ID1≈−2√ (2βI ) × δV
It becomes. If the mirror ratios of the two current mirror circuits are equal (M = M _N = M _P ),
IC2-ID2≈−2 × M × √ (2βI) × δV
It becomes.

For example, if M = 5, β = 1 mA / V ² , and I = 0.2 μA, IC2−ID2 = 20 μA when the output voltage decreases by 0.1 V (δV = −0.1 V).

  That is, even when the output voltage is as small as 0.1 V, a sufficiently large drive current of 20 μA can be obtained with respect to the steady current of 1 μA (0.2 μA × 5) of IC2 and ID2. Therefore, the terminal 6 can be driven to the minimum VSS, and the terminal 7 can be driven to the maximum VCC to the limit of the power supply voltage range even with a slight change in the output voltage. In the driving direction, the terminal 7 is driven to VCC when the output voltage decreases, and the terminal 6 is driven to VSS when the output voltage increases. As a result, when there is an error in the output voltage, the second push-pull circuit is driven with a signal obtained by amplifying the error, and the operation is performed so as to eliminate the error in the output voltage. Therefore, it is possible to provide a much higher driving capability than in the case where the driving is simply performed by the source follower circuit as in the conventional example. Even if the steady-state bias current is suppressed to a sufficiently low value, a high driving current can be obtained by amplifying the error. Further, as can be easily understood from the above equation, this circuit operates symmetrically with respect to the direction of error, so that the same driving ability can be obtained for charging and discharging of the output.

  Next, the accuracy of the circuit as a voltage follower will be described. In this circuit, an error in the output voltage is detected by the first push-pull circuit, and the second push-pull circuit is driven by a signal obtained by amplifying the error. Therefore, the output voltage accuracy (input / output voltage difference) is determined by the voltage accuracy (input / output voltage difference) of the first push-pull circuit. In the first push-pull circuit, when a steady state, that is, a condition that satisfies IC1 = ID1, is obtained, a relationship between the input voltage V (IN) and the output voltage V (OUT) is obtained, and the following equation is obtained.

V (OUT) −V (IN) = β × (VN1−VTN) − (VP1−VTP) / (
β _R +1)
Where β _R = √ (β _TN2 / β _TP2 )
VTN and VTP are the absolute values of the gate threshold voltages of the N-channel and P-channel MOS transistors, respectively. As is apparent from this equation, VN1 and VP1 have characteristics that change in accordance with changes in VTN and VTP, respectively, and by appropriately selecting β of the transistor, N channel transistors and P Even if the element characteristics of the channel transistor change independently, the voltage difference between the output and the input can be made zero. As described in the next embodiment, the voltage source as described above can be easily configured by connecting the gate and drain of each channel conductivity type MOS transistor and allowing a predetermined current to flow therethrough. In general, even if there are variations in characteristics between elements of different conductivity types, transistors of the same conductivity type go through the same manufacturing process, so that the difference in characteristics between elements can be suppressed to a sufficiently small value. In particular, with respect to variations in processing shape, the difference in characteristics between the element pairs can be further reduced by designing the gate width and gate length to be sufficiently larger than the processing accuracy. For example, taking the gate threshold voltage as an example, the difference between pairs of elements of the same conductivity type can be easily reduced to about 20 to 30 mV, but the difference between elements of different conductivity types is Usually, the variation is about 200 mV at maximum, which is about one digit larger. As described above, the voltage accuracy (input / output voltage difference) of the first push-pull circuit is suppressed to about 20 to 30 mV, which is determined by the threshold voltage difference between the transistor pair, and is about one digit lower than that of the conventional method.

  Next, a transient operation will be described with reference to FIG. Consider a case where the input voltage V (IN) falls from time t0 to t1 and rises from time t4 to t5. Since the output does not immediately follow immediately after the input voltage drops, the transistor TN2 is cut off from time t1 to time t2, and the value of the current IC1 becomes almost zero. On the other hand, ID1 increases, and the voltage V (6) at the terminal 6 is pulled down to approximately VSS (0V). This increases the driving capability of the transistor TP4 and discharges the output OUT at high speed. After the time t2, when the difference between the output voltage and the input voltage becomes small, the transistor TN2 starts to conduct, and finally IC1 = ID1 at time t2 when there is no voltage difference between the input and output, and a steady state is obtained. When the input voltage rises, the voltage at the terminal 7 rises to VCC in contrast with this, and the output is charged at high speed.

  As described above, according to the present invention, even if there is a variation in the manufacturing process, there is little error between input and output voltages, and in a transient state, a voltage follower that can charge and discharge a large-capacity load at high speed. Can be provided. In addition to the application as a voltage follower, this circuit can be used as a high-performance current detection circuit by inputting a signal current to the output terminal OUT and taking out the output from the terminal 6 or 7.

  Next, an embodiment in which the above-described circuit is applied to an intermediate voltage (VCC / 2) generation circuit of a dynamic memory will be described with reference to FIGS. FIG. 31 shows a configuration example of an intermediate voltage generating circuit according to the present invention. In the figure, 30 is a reference voltage generating circuit, 31 is a first complementary push-pull circuit, 32 is a current mirror type amplifier circuit, and 33 is a second complementary push-pull circuit. The reference voltage generation circuit generates an intermediate voltage at the terminal 34 by dividing the power supply voltage in half by two resistors R3 and R4 having equal resistance values. By using the same type of elements for the resistors R3 and R4, a fairly accurate value can be obtained for the intermediate voltage. It is obvious that the element for obtaining the intermediate voltage is not limited to the resistor, and a similar circuit can be configured even if, for example, a MOS transistor or the like is used. The first push-pull circuit is basically the same as the push-pull circuit 1 shown in FIG. Here, a resistor R5 and an N-channel MOS transistor TN10 are used instead of the voltage source VN1, and a resistor R6 and a P-channel MOS transistor TP10 are used instead of the voltage source VP1, respectively. By doing so, as described in the previous embodiment, the voltage at the terminal 35 is always automatically set higher than the input terminal 34 by a value substantially equal to the gate threshold voltage of the N-channel MOS transistor. Can do. Note that the resistance value is selected so that the current flowing through R5 and R6 becomes a small value that is a fraction to one-tenth of the current flowing through R3 and R4. This is because the characteristics of the N-channel transistor and the P-channel transistor vary independently, and the voltage at the terminal 34 is affected even if the current value flowing into (or out of) the push-pull circuit into the reference voltage generation circuit fluctuates. This is to prevent fluctuations. The current mirror type amplifier circuit 32 has the same configuration as the current mirror type amplifier circuit 2 shown in FIG. The second push-pull circuit is basically the same as the push-pull circuit 3 shown in FIG. Here, an N-channel MOS transistor TN14 is used instead of the voltage source VN2, and a P-channel MOS transistor TP14 is used instead of the voltage source VP2. By doing so, as in the case of the first push-pull circuit, the value of the bias current flowing through the push-pull circuit is prevented from fluctuating with respect to the change in the threshold voltage of the transistor. With the circuit configuration as described above, an accurate intermediate voltage can be obtained for the output HVC, and the load capacitance CL can be charged and discharged at high speed.

  FIG. 32 (a) and FIG. 32 (b) show results obtained by computer analysis of the performance comparison between the present circuit system shown in FIG. 31 and the conventional circuit system shown in FIG. In FIG. 32A, the horizontal axis represents the difference between the absolute values of the gate threshold voltages of the N-channel transistor and the P-channel transistor, and the vertical axis represents the value of the intermediate voltage. From this result, in the conventional circuit, when the threshold voltage difference fluctuates by ± 0.2 V, the output voltage fluctuates by about ± 100 mV (about ± 13% with respect to 0.75 V), whereas the present invention In this circuit, the output voltage fluctuation is about ± 8 mV (about ± 1% with respect to 0.75 V), which can be reduced by one digit or more as compared with the conventional circuit. FIG. 32B is a plot of the rise time of the output voltage after the power is turned on against the power supply voltage. The rise time is defined as the time when the output voltage reaches 90% of the steady value. Further, the value of the load capacity is assumed to be the total capacity of the bit line precharge power source and the plate electrode of the 64 Mbit DRAM. As can be seen from the analysis result, according to the circuit of the present invention, it is possible to start up the load in about one digit shorter time than the conventional circuit.

FIG. 33 (a) is a circuit diagram showing another embodiment of the present invention. In the figure, 40 is a complementary push-pull type voltage follower circuit, and 41 is a tri-state buffer. The voltage follower circuit is basically the same as the push-pull circuit 1 of FIG. Here, the tristate buffer operates so as to supplement the drive capability of the push-pull circuit. The tristate buffer includes a P-channel transistor TP21 and an N-channel transistor TN21 for driving a load, two differential amplifier circuits (comparators) AMP1 and AMP2 for driving these transistors, and two voltages for setting an offset amount. It consists of sources VOSL and VOSH. The operation of this circuit depends on which of the following three voltage conditions applies:

(1) V (OUT)> V (IN) + VOSH
(2) V (IN) + VOSH> V (OUT)> V (IN) -VOSL
(3) V (IN) −VOSL> V (OUT)
Under the voltage condition (1), the voltage at the output OUT is higher than the voltage at the terminal 43, and the voltage at the terminal 45 is at a high voltage level (VCC). The voltage at the terminal 44 is also at a high voltage level (VCC). Therefore, the N-channel transistor TN21 becomes conductive, the P-channel transistor TP21 becomes cut off, and the load is discharged. Under the voltage condition (2), the voltage at the output OUT is lower than the voltage at the terminal 43 and the voltage at the terminal 45 is at a lower voltage level (VSS). Further, the voltage at the terminal 44 maintains a high voltage level (VCC). Therefore, the two transistors TN21 and TP21 are both cut off, and the output is in a high impedance state. Under the voltage condition (3), the voltage at the output OUT is lower than the voltage at the terminal 42, and the voltage at the terminal 44 is at a lower voltage level (VSS). Further, the voltage at the terminal 45 maintains a low voltage level (VSS). Therefore, the N-channel transistor TN21 is cut off and the P-channel transistor TP21 is turned on to charge the load. In this way, there are three states in which discharge occurs when the output voltage increases beyond a certain range centered on the input voltage, charging occurs when the output voltage decreases beyond a certain range, and neither charging nor discharging occurs within the certain range ( A driving circuit having a tristate can be realized. The operation at the time of transition of this circuit is shown in FIG. Consider a case where the input voltage V (IN) drops at time t0 and rises at time t2. At the time of falling, the voltage at the terminal 45 becomes VCC from time t0 until time t1 when the output voltage becomes equal to “(voltage in steady state) + VOSH”, the transistor TN21 is turned on, and the load is discharged. At the time of rising, the voltage at the terminal 44 becomes VSS from time t2 until time t3 when the output voltage becomes equal to “(voltage in steady state) −VOSL”, the transistor TP21 is turned on, and the load is charged. .

  In this way, by combining a push-pull circuit with a tristate buffer, when the voltage error between input and output becomes larger than a certain level, the transistor with high drive capability is made conductive to increase the response speed during transients. be able to. The convergence of the two voltage sources VOSL and VOSH for setting the offset amount can be made faster by setting the values as small as possible. However, in order to avoid malfunction, a differential amplifier circuit (comparator) AMP1 is used. And a value sufficiently larger than the input offset voltage of AMP2. When a circuit is constituted by MOS transistors, this value is desirably 50 mV or more. Note that the circuit configuration of the tri-state buffer is not limited to the example shown here, and any other scheme may be used as long as the same function is realized.

Next, an embodiment in which a voltage follower using a tristate buffer is applied to an intermediate voltage (VCC / 2) generation circuit of a dynamic memory will be described with reference to FIGS. FIG. 34 shows a configuration example of the intermediate voltage generating circuit according to the present invention. 34, reference numeral 50 denotes a reference voltage generation circuit, 51 denotes the voltage follower circuit described in FIG. 29, and 52 denotes a tri-state buffer. This increases the restoring capability when the voltage error between the input and output becomes large by adding a tristate buffer to the intermediate voltage generating circuit shown in FIG. The configuration and operation of the tristate buffer will be described below. The feature of this embodiment is that the first push-pull circuit is used as it is, the error voltage is detected using the difference in the mirror ratio of the current mirror circuit, and the tristate buffer is activated. In FIG. 34, TP36 and TP37 are P-channel MOS transistors, TN36 and TN37 are N-channel MOS transistors INV1 and INV2, inverters TP38 are P-channel MOS transistors configured to drive a load by the output of the inverter INV1, and TN38 is an inverter INV2. N-channel MOS transistors configured to drive a load with the output of are shown. TP32 and TP36, and TP32 and TN37 each constitute a current mirror circuit. Now, the current flowing through the transistor TN31 is IC1, the current flowing through the transistor TP31 is ID1, the current flowing through the transistor TN36 is ID2, and the current flowing through the transistor TP36 is IC2. The relationship between the output voltage error δV and IC1 and ID1 is as described above.
IC1-ID1≈−2√ (2βI) × δV
And can be approximated. The mirror ratio of the current mirror circuit
M _P1 = IC2 / IC1 = β _TP36 / β _TP32
M _N1 = ID2 / ID1 = β _TN36 / β _TP32
Then, it becomes like the following formula.
IC2 / M _P1 −ID2 / M _N1 ≈−2√ (2βI) × δV
Upon application of the offset voltage Vos now output, and the IC 2 = ID2, placing the current value at that time and I _2, the offset voltage Vos is _{Vos ≒ I 2 / (2 ×} α) × (M P1 -M _N1 ) / (M _N1 × M _P1 )
It is expressed. here,
α = √ (2βI ₁ )
Further, β is β of the transistor constituting the first push-pull circuit, and I ₁ is a current flowing through the first push-pull circuit in a steady state. For example, I ₁ = 0.2 μA
, I ₂ = 1 μA, β = 1 mA / V ² , M _N1 = 1, M _P1 = 0.2, the offset voltage Vos is −100 mV. That is, when the output voltage is lowered by 100 mV or more from the steady value, the input voltage of the inverter INV1 is changed from the low level to the high level, the output voltage is changed from the high level to the low level, and the driving P-channel MOS transistor TP38 is made conductive. Charge the load. Similarly, by appropriately selecting the constants of the transistors TP37 and TN37, the N-channel MOS transistor TN38 can be turned on and the load can be discharged when there is a predetermined positive offset.

  As described above, by adopting the circuit configuration as shown in the present embodiment, the same function as shown in FIG. 33 can be realized. Further, in this circuit system, the offset amount is determined by the mirror ratio of the current mirror circuit. Therefore, the offset amount can be set with high accuracy if consideration is given to reducing the difference in characteristics of the transistor pair. Further, since it is not necessary to provide a high-precision differential amplifier separately, high power consumption can be achieved and high performance can be realized with a simple configuration.

  FIG. 35 shows the result of calculating the performance comparison between this circuit system and the conventional circuit system shown in FIG. 30 by computer analysis. FIG. 35 is a plot of the rise time of the output voltage after power-on with respect to the power-supply voltage. The rise time is defined as the time when the output voltage reaches 90% of the steady value. Further, the value of the load capacity is assumed to be the total capacity of the bit line precharge power source and the plate electrode of the 64 Mbit DRAM. As can be seen from the analysis result, according to the circuit of the present invention, the rise time can be further shortened by about a half digit as compared with the embodiment shown in FIG. Compared with the conventional circuit, the load can be started up in a time that is about one and a half digits shorter. As described above, by combining a push-pull circuit with a tristate buffer, a voltage follower circuit capable of following the input at higher speed can be provided. Since the voltage setting accuracy is determined by the push-pull circuit, the voltage error between the available powers can be made extremely small as in the case of the previous embodiment.

  In the above embodiments, the circuit configuration for driving a large-capacity load in an integrated circuit (LSI) at high speed has been described. However, when driving at higher speed, the transient current during charging and discharging becomes a big problem. For example, the load capacity of an intermediate voltage generation circuit of a DRAM of about 64 Mbit is about 115 nF, and the current value reaches 23 mA when driven with an amplitude of 1 V for 5 μs. This is a size comparable to the current consumption value of DARM, and driving at a higher speed causes influence on main circuit characteristics, for example, generation of noise in the power supply line and reduction in reliability of the drive signal wiring. It is not preferable because of danger. In general, in an ultra-highly integrated LSI, particularly a memory, the entire LSI is often composed of a plurality of blocks of the same type, and during operation, only a part of these blocks is activated. In such an LSI, it is effective to apply the embodiments described below.

  36 and 37 show an embodiment in which the present invention is applied to an intermediate voltage supply system of a dynamic memory (DRAM). In FIG. 36, MB0, MB1 to MBi are i + 1 memory blocks, 60 to 62 are word line selection circuits, 68 to 70 are intermediate voltage lead lines from each memory block, and 76 and 77 are two sets of intermediate voltages. Generating circuits 74 and 75 are signal lines for supplying intermediate voltages HVC1 and HVC2 to each memory block from two sets of intermediate voltage generating circuits, and 71 to 73 are for supplying one of the two signal lines to the memory block. This is a switch provided for each block. The memory block MB0 is a memory cell array MA0 in which memory cells are two-dimensionally arranged, and input / output control for amplifying a signal read from the memory cell and outputting it to the outside or writing an external signal to the memory cell. The circuit block MC0, the input / output circuit 67, and the like are included. DL0, DL0￣, DLj￣ are data lines for transmitting signals to the memory cells, 63 is a plate electrode forming a counter electrode of the storage capacitor, and 64 is a precharge voltage arranged to make the data line an intermediate voltage when not selected. Supply line, PC is a precharge signal line, SA0 to SAj are sense amplifiers for detecting and amplifying signals read from the memory cells, and 65 and 66 are common input / outputs for transmitting signals between the input / output circuit 67 and each data line. Line pairs IO0 to IOj are IO gates for controlling connection between the data line pair selected by the addressing signal and the common input / output line pair.

  Now, suppose that only one block MB0 is selected from the i + 1 memory blocks and enters the operating state. At this time, one word line in MA0 is selected by the word line selection circuit 60 and transits to a high level. At the same time, the switch 71 is controlled, and the intermediate voltage lead line 68 is connected to the signal line 75 for supplying the intermediate voltage. On the other hand, the lead lines 69 and 70 from the memory blocks MB1 to MBi in the non-selected state are connected to a signal line 74 for supplying an intermediate voltage. In this way, the load of i memory blocks is connected to the intermediate voltage generation circuit 76, whereas the load of one memory block is connected to the intermediate voltage generation circuit 77. For example, when i = 15, the load capacity driven by the intermediate voltage generation circuit 77 is 1/15 of the load capacity driven by the intermediate voltage generation circuit 76. Therefore, even if the same circuit is used for 76 and 77, the intermediate voltage of the selected block MB0 operates 15 times faster than the intermediate voltage of the non-selected block. From the viewpoint of circuit performance, the response speed of the non-selected memory block is not related to the performance of the memory, so that the performance of the entire memory can be improved with almost no increase in transient current. FIG. 37 shows the time change of the intermediate voltage when the power supply voltage fluctuates during the memory operation. In other words, it is assumed that the voltage VCC decreases between the times t0 and t2. It is assumed that the memory block MB0 is selected between time t0 and t1 and after time t3, and the memory block MB1 is selected between time t1 and t3. Between time t0 and t1, since the block MB1 is not selected, the intermediate voltage V (69) responds slowly, whereas the block MB0 is selected, so the intermediate voltage V (68) is Following high speed. When the block MB1 is selected and the block MB0 is switched to non-selection at time t1, this time, V (69) quickly changes toward the voltage to be set. As described above, according to this embodiment, a large-capacity load such as an intermediate voltage of a dynamic memory can be driven substantially at a high speed with almost no increase in transient current. In this example, the example in which the present invention is applied to the intermediate voltage of the dynamic memory has been described. However, the scope of application is not limited to this, and it is composed of the same type of blocks, and some of them are active during operation. It can be applied to generalized integrated circuits.

  As mentioned above, although the details of the present invention were explained by each example, the application range of the present invention is not limited to these. For example, although the case where an LSI is constituted by a CMOS transistor has been mainly described here, an LSI using a bipolar transistor, an LSI using a junction FET, a BiCMOS type LSI combining a CMOS transistor and a bipolar transistor, and silicon Other materials, for example, an LSI in which an element is formed on a substrate such as gallium arsenide, can be applied as it is.

  In the present embodiment, the current mirror circuit is used as the current amplifier circuit, but other current amplifier circuits may be used.

The figure which shows the 1st Example of this invention. The figure which shows the 1st Example of this invention. The figure which shows the 1st Example of this invention. The figure which shows the 1st Example of this invention. The figure which shows the 1st Example of this invention. The figure which shows the 1st Example of this invention. The figure which shows the effect of this invention. The figure which shows the effect of this invention. The figure which shows the Example which further heightened the effect by using FIGS. The figure which shows the Example when a some memory cell array exists. The figure which shows the Example of a parallel test. The figure which shows the Example of a parallel test. The figure which shows the Example of a parallel test. The figure which shows the Example of a parallel test. The figure which shows the Example of a parallel test. The figure which shows the Example of a parallel test. The figure which shows the Example for writing arbitrary write-in voltages to a memory cell. Examples of the present invention. Timing chart. It is a prior art example and its timing chart. It is a prior art example and its timing chart. Examples of the present invention. Timing chart. Examples of the present invention. Timing chart. Examples of the present invention. Examples of the present invention. The figure which shows the effect of the Example of FIG. (A) is an embodiment for explaining the basic concept of the present invention. (B) is a diagram for explaining the operation during the transition. A conventional example of an intermediate voltage generating circuit for DRAM. A specific embodiment in which the present invention is applied to an intermediate voltage generation circuit of a DRAM. The figure explaining the effect of this invention. (A) is an embodiment for explaining another basic concept of the present invention. FIG. 6B is a diagram for explaining the operation. A specific embodiment applied to an intermediate voltage generation circuit of a DRAM. The figure explaining the effect. The figure explaining the specific Example which applied the other basic concept of this invention to the intermediate voltage drive system of DRAM. It is a figure explaining the intermediate voltage change of the Example of the figure (a) when a power supply voltage fluctuates during memory operation.

Explanation of symbols

MA ... Memory cell array, CKT ... Input / output control circuit, RG0, RG1 ... Read gate, WG0, WG1 ... Write gate, SA0, SA1 ... Sense amplifier, SWR0, SWR1 ... Read switch, SWW0, SWW1 ... Write switch, RO, RO￣ ... read line, WI, WI￣ ... write I / O line, dy ... data line pitch, WD ... word driver, XD ... X decoder, VLG ... voltage conversion circuit for memory array, VCHG ... for word line Voltage conversion circuit, W ... word line, φ 、 P ... precharge signal, FX ... word line drive pulse generation circuit, φX ... word line drive pulse, CP ... charge pump circuit, RECT ... rectifier circuit, VL ... data line voltage or Internal (for array) power supply voltage, VCH ... Word line voltage conversion circuit output voltage, φ, φ￣, PA, PA￣ PB, PB￣ ... Word line voltage conversion circuit boost pulse, OSC ... Ring oscillator output pulse, C, C1, C2, C3, C4, CA, CB, CD ... Capacitor, R, R1, R2 ... Resistance, QD1, QP, Q9, Q10 ... P channel MOS transistors, QT, QD2, QS, QD, QA, QB, QC, QP, Q1, Q8, Q11, Q19 ... N channel MOS transistors, I1, I25, I30, I33 ... inverters, NA1, NA2 ... NAND circuit, NO1 ... NOR circuit, VEXT ... external power supply voltage, 1, 31, 40 ... first complementary push-pull circuit, 2, 32 ... current mirror type push-pull amplifier circuit, 3, 33 ... first Two complementary push-pull circuits, 30, 50... Reference voltage generation circuit, 41, 52. Buffer, AMP1, AMP2 ... Differential amplifier circuit, MB0 to MBi ... Memory block, 60-62 ... Word line selection circuit, 71-73 ... Switch, 76, 77 ... Intermediate voltage generation circuit (drive circuit), MA0 ... Memory cell array, MC0... Signal amplification and input / output control circuit group, SA0 to SAj... Detection amplifier circuit (sense amplifier), IO0 to IOj.

Claims (12)

Arranged at the intersection of the first data line pair, the second data line pair, the first word line intersecting the first and second data line pairs, and one of the first word line and the first data line pair. A first memory array, and a first memory array including a second memory cell disposed at an intersection of the first word line and one of the plurality of second data line pairs;
A second data line including a third data line pair, a second word line intersecting the third data line pair, and a second memory cell disposed at one intersection of the second word line and the third data line pair. Two memory arrays;
A first circuit coupled to the first data line pair via a first MISFET pair;
A second circuit coupled to the second data line pair via a second MISFET pair and to the third data line pair via a third MISFET pair;
Y decoder,
The first circuit is disposed between the Y decoder and the first memory array , connected to the first MISFET pair, connected to the first signal line pair, and to the first MISFET. A first precharge circuit that operates so that the potentials of one and the other of the first data line pair are equal to each other via the pair; and is connected to the first signal line pair and appears on the first data line pair A first sense amplifier for amplifying the received signal,
The second circuit is disposed between the first memory array and the second memory array, and is connected between the first MISFET pair and the second MISFET pair, and the second signal line. The second data line pair is connected to a pair and operates so that the potential of one of the second data line pair is equal to the other via the second MISFET pair, and one of the third data line pair is A second precharge circuit that operates to have the same potential, and a signal that appears on the second data line pair via the second MISFET pair or the third MISFET pair that is connected to the second signal line pair. and a second sense amplifier for amplifying a signal appearing at the third data line pair, and
2. A semiconductor device according to claim 1, wherein no other memory array is arranged between the Y decoder and the first memory array. In claim 1,
Before first precharge circuit SL has a first 4MISFET having a source-drain coupled between the first signal line pair,
Before Stories second precharge circuit to a semiconductor device and having a first 5MISFET having a source-drain coupled between said second signal line pairs. In claim 2,
The first precharge circuit includes a sixth MISFET having a source / drain coupled between one of the first signal line pairs and a precharge potential, and the other of the first signal line pair and the precharge potential. A seventh MISFET having a source and a drain coupled to each other,
The second precharge circuit includes an eighth MISFET having a source / drain coupled between one of the second signal line pairs and the precharge potential, and the other of the second signal line pair and the precharge potential. And a ninth MISFET having a source / drain coupled therebetween. In claim 1,
Before Symbol first precharge circuit includes a first 6MISFET having a source-drain coupled between one and the precharge potential of the first signal line pair, the other with the precharge potential of the first signal line pair And a seventh MISFET having a source and a drain coupled therebetween,
The second precharge circuit includes an eighth MISFET having a source / drain coupled between one of the second signal line pairs and the precharge potential, and the other of the second signal line pair and the precharge potential. And a ninth MISFET having a source / drain coupled therebetween. In any one of Claims 1-4,
The first precharge circuit is inactivated when the first memory array is selected;
The semiconductor device according to claim 1, wherein the second precharge circuit is inactivated when one of the first memory array and the second memory array is activated. In any one of Claim 1 to 5,
The first memory array includes a fourth data line pair, a fifth data line pair, a fourth memory cell disposed at an intersection of the first word line and the fourth data line pair, A fifth memory cell disposed at one intersection of one word line and the fifth data line pair;
The fourth data line pair is coupled via a third circuit and a tenth MISFET pair,
The fifth data line pair is coupled via a fourth circuit and an eleventh MISFET pair,
The second memory array further includes a sixth data line pair, and a sixth memory cell disposed at an intersection of the second word line and one of the sixth data line pair,
The sixth data line pair is coupled to the fourth circuit through a twelfth MISFET pair,
The third circuit is disposed between the Y decoder and the first memory array,
The fourth circuit is disposed between the first memory array and the second memory array,
The first, second, fourth and fifth data line pairs are arranged adjacently in order. Arranged at the intersection of the first data line pair, the second data line pair, the first word line intersecting the first and second data line pairs, and one of the first word line and the first data line pair. A first memory array, and a first memory array including a second memory cell disposed at an intersection of the first word line and one of the plurality of second data line pairs;
A third data line pair; a second word line intersecting the third data line pair; and a second memory cell disposed at one intersection of the second word line and the third data line pair. Two memory arrays;
A first circuit coupled to the first data line pair via a first MISFET pair and not coupled to the other data line pair;
A second circuit coupled to the second data line pair via a second MISFET pair and coupled to the third data line pair via a third MISFET pair;
The first memory array is disposed between the first circuit and the second circuit,
The first circuit is coupled between a first signal line pair coupled to the first MISFET pair, a first sense amplifier coupled between the first signal line pair, and the first signal line pair. A first precharge circuit,
The second circuit includes a second signal line pair coupled between the second MISFET pair and the third MISFET pair, a second sense amplifier coupled between the second signal line pair, and the second signal. And a second precharge circuit coupled between the pair of lines. In claim 7,
The first precharge circuit includes a fourth MISFET having a source / drain coupled between the first signal line pair,
The second precharge circuit has a fifth MISFET having a source / drain coupled between the second signal line pair. In claim 7 or 8,
The first precharge circuit includes a sixth MISFET having a source / drain coupled between one of the first signal line pairs and a precharge potential, and the other of the first signal line pair and the precharge potential. A seventh MISFET coupled between,
The second precharge circuit includes an eighth MISFET having a source / drain coupled between one of the second signal line pairs and the precharge potential, the other of the second signal line pair, and the precharge potential. And a ninth MISFET having a source and a drain coupled to each other. In claim 7,
The precharge potential output from the second precharge circuit is supplied to the second data line pair via the second MISFET pair,
The semiconductor device according to claim 1, wherein the precharge potential output from the second precharge circuit is supplied to the third data line pair via the third MISFET pair. In any one of Claims 7 to 10,
The first memory array includes a fourth data line pair, a fifth data line pair, a fourth memory cell disposed at an intersection of the first word line and the fourth data line pair, A fifth memory cell disposed at one intersection of one word line and the fifth data line pair;
The fourth data line pair is coupled via a third circuit and a tenth MISFET pair,
The fifth data line pair is coupled via a fourth circuit and an eleventh MISFET pair,
The second memory array further includes a sixth data line pair, and a sixth memory cell disposed at an intersection of the second word line and one of the sixth data line pair,
The sixth data line pair is coupled to the fourth circuit through a twelfth MISFET pair,
The third circuit is disposed between the Y decoder and the first memory array,
The fourth circuit is disposed between the first memory array and the second memory array,
The first, second, fourth and fifth data line pairs are arranged adjacently in order. In any one of Claims 1-11,
The semiconductor device is a dynamic memory.