KR100262437B1 - Semiconductor device operating with low supply voltage - Google Patents

Abstract

PURPOSE: A semiconductor device operated at a low supply voltage is provided to operate stably a driving transistor for word line as a word driver though a supply voltage is reduced. CONSTITUTION: In the circuit, the transfer impedance between a common I/O line and a data line is changed depending on whether information is to be read or written. A current/voltage converter includes a MISFET different in conduction type to a select MISFET. Thus, the speed of reading information is increased. An intermediate voltage generator having high driving capability is provided. Thus, the circuit has sufficient driving capability for an LSI having large load capacitance. A voltage converter converts a data line supply voltage or word line supply voltage to a higher voltage. Therefore, stabilized signal transmission is ensured.

Description

Semiconductor device operating at low power supply voltage {SEMICONDUCTOR DEVICE OPERATING WITH LOW SUPPLY VOLTAGE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a highly integrated semiconductor device capable of battery operation, high speed, and low voltage operation.

The degree of integration of LSI (Large Scale Integration) is improved by miniaturizing the MOS transistor as its component. In the LSI having a so-called deep sub-micron dimension of 0.5 micron or less, the problem is that the power consumption of the LSI is increased and the breakdown voltage of the device is a problem. In order to cope with such a problem, it is considered that an effective means is to lower the operating power supply voltage of the device as the device becomes finer. Since 5V is mainly used as the power supply voltage of the current LSI, a technology for mounting a voltage drop conversion circuit for converting an external power supply voltage to an internal power supply voltage on an LSI chip as a means of configuring the LSI with a minute device is IEEE, Journal of Solid- State Circuits, Vol. 21, No. 5, pp. 605-610, issued October 1986. In this case, the external and internal power supply voltages are 5V and 3.5V, respectively. As such, power consumption is a problem in the LSI, particularly in the highest density DRAM. According to this tendency, there is a movement to lower the external power supply voltage of the LSI. For example, in a 64-Mbit DRAM using a 0.3 micron processing technology, the external power supply voltage will drop to about 3V. In addition, as the degree of integration of the LSI is improved, the external power supply voltage may be further lowered.

Background Art In recent years, as portable electronic devices are widely used, demands for low voltage-low power consumption LSIs capable of storing information by batteries and batteries are increasing. For these applications, the minimum voltage is 1 to 1. LSI operating at 5V is required. In particular, in the case of dynamic memory, its density has already reached the megabit level. In addition, there is a movement to use dynamic memory in the field of mass storage device, which has conventionally used only a magnetic disk device. It is necessary to back up the dynamic memory by the battery so that data is not lost even if the power is cut off. In general, backup periods require weeks to years. Therefore, it is necessary to minimize the power consumption of the memory. In order to achieve low power, it is effective to reduce the operating voltage. When the operating voltage is reduced to about 1.5V, one battery is sufficient for the backup power supply. In addition, it is inexpensive and the area of power is reduced.

CMOS (complementary MOS) LSI consisting only of inverters and various digital logic circuits In processors, for example, if the dimensions of the MOS transistors and the gate threshold voltage are properly selected, even if the power supply voltage is lowered to about 1.5V, a significant performance degradation will occur. There is nothing to do. However, in the LSI using the external power supply voltage and its intermediate voltage for operation, there is an obvious performance degradation. One typical LSI is DRAM.

In the case where the DRAM is operated at a low voltage, a conventional problem mainly occurs in the following three parts in terms of high speed operation and stable operation.

That is, [1] an input / output (I / O) control circuit that leads a minute signal in a memory cell, [2] a circuit that generates a high voltage necessary for driving a word line to transmit a signal, and [3] an intermediate voltage. There are three kinds of generating circuits.

Description will be made sequentially according to these prior art circuits. In [1], the parasitic capacitance on the signal wiring also increases as the LSI becomes more integrated and larger. Therefore, the operating speed of the LSI decreases. In the case of dynamic memory, the speed of amplifying a small signal from each memory cell to the data line using a sense amplifier, and an input / output signal line (common I / O) for reading information from the selected data line Line) occupies a large proportion of the operating speed of the entire memory, and a technique for speeding up these is indispensable for improving the performance of the memory. As a conventional input / output control circuit, for example, IEEE, Journal of Solid-State Circuits, Vol. SC-22, No. 5, pp. It is described in 663-667 (issued October 1987). Among them, a method of controlling the connection of a pair of common I / O lines and a pair of data lines by applying a selection signal to the gate electrodes of two MISFETs (Metal Insulator Semiconductor Field Effect Transistors) is described. However, this method has a problem that the propagation delay of a signal becomes large under low voltage.

Regarding [2], Fig. 9 shows a conventional example thereof. This shows a circuit related to the memory cell array MA and the word driver WD of the DRAM. 10 shows waveforms of several circuit elements. This circuit is described, for example, in IEEE, Journal of Solid-State Circuits, Vol. SC-21, No. 3, pp. 381-389 (June 1986). According to this method, when the low power supply voltage is used, no high voltage is applied to the word line.

[3], for example, IEEE, Journal of Solid-State Circuits, Vol. 21, No. 5, pp. 643-647 (issued October 1986). However, the technique described here has a problem that the driving capability is greatly lowered when a low power supply voltage is used.

As a prior application for a low voltage operation semiconductor device related to a semiconductor memory device according to the present invention, US application No. 366, 869.

The problem to be solved by the present invention with respect to the prior art is as follows.

First, the problem to be solved with respect to the prior art of [1] is as follows. 2A and 2C show a conventional scheme. The detailed description of FIGS. 2A and 2C will be described later. According to this method, since the I / O control circuit can be configured with the minimum number of transistors required, it is effective to reduce the total area of the memory. However, the memory has the following problems.

[a] data line (D ₀ , If the I / O control MISFETs (T ₅₀ , T ₅₁ ) are in a conductive state before the voltage difference between the circuits is sufficiently established, the operation of the sense amplifier SA ₀ is inhibited and causes a malfunction.

[b] For the reason described above, it is necessary to set a time delay (timing margin) until the MISFET is brought into a conduction state by applying the selection signal Y ₁ after the sense amplifier is operated. Therefore, the operation speed is lowered (Fig. 2C).

[3] In order to prevent such a malfunction, a design constraint occurs in the ratio between the channel conductance (or drain-source conductivity) of the MISFET and the channel conductance of the MISFET constituting the sense amplifier. In general, it is necessary to make the former smaller than the latter. At this time, common I / O line (IO ₀ , It is difficult to take large driving capacity. Therefore, the operation speed is further lowered.

[d] It is difficult to read or write data in parallel between one common I / O line pair and several data lines connected to this common I / O line pair mainly for the reason of [c] above. Therefore, the parallel test method cannot be applied to the conventional method by selecting multiple I / O gates.

For these reasons, it was not possible to provide a circuit system suitable for a highly integrated memory which operates at high speed even at low voltage and has a high speed parallel test capability.

9 and 10 show a conventional example of the above [2]. As shown in FIG. 10, the voltage at the node N ₂ becomes V _L -V _T + α (V _L -2V _T ) / (1-α). The voltage of the word line is (V _L -2V _T ) / (1-α), where V _L is the power supply voltage, V _T is the threshold of the transistor, and α is the gate capacitance of Q _D and the total capacitance of node N ₂ . Ratio (ie, the sum of the gate capacitance of Q _D and the parasitic capacitance of node N ₂ ).

Here, assume that V _L is 1.1V. α = 0. 9, V _T = 0. If a 5V, the voltage of the above formula are: 1. N ₂ is at 5V. Therefore, the voltage of the word line rises only to 1.0V. In general, the threshold value of the switching transistor Q _S of the memory cell is 0.5 V or more higher than the threshold value of the peripheral circuit, so that the amount of charge stored in the memory cell is less than 1/2 of the maximum value (C _S x1.1) (C _S ). 0.5). Therefore, the resistance to soft errors and the S / N ratio of the sense amplifier are greatly reduced. As a result, destruction of stored data is likely to occur.

As described above, when the DRAM is operated by the battery using the prior art, the word driver causes an operation failure when the electromotive force of the battery drops to a value almost twice that of the threshold voltage V _T of the MOS transistor. Therefore, the write voltage to the memory cell is lowered, and data destruction is more likely to occur. Therefore, it was necessary to solve this problem.

Regarding [3], its conventional example is shown in FIG. In the conventional method, an intermediate voltage was generated using one stage of the complementary push-pull circuit. However, the load capacity is increased by the high integration of the LSI. Therefore, the driving capability is insufficient and the response speed is lowered. In addition, since the voltage setting accuracy is lowered and the S / N ratio is lowered, the V _T fluctuation is not constant when the operating voltage is lowered.

In the present invention, an input / output (I / O) control circuit for reading / writing data from data lines is alternately arranged on the left and right sides of the memory array. In addition, a circuit configuration is used in which the transfer impedance between the common I / O line and the data line is changed depending on whether information is read or written. In addition, as a sense circuit for detecting a signal of the lead (RO) line, a current voltage converting means using a drive MISFET of a complementary conductivity type with an I / O gate is provided. Therefore, the input / output control circuit is arranged at twice the pitch of the data line. Compared with the related art, the input / output circuit can be configured without increasing the chip area. In addition, since the operating margin of the input / output circuit is greatly improved, the input / output circuit can be operated at high speed even at a low voltage.

The circuit method including the complementary push-pull circuit and the current mirror amplification circuit is composed of field effect transistors capable of lowering the gate threshold voltage. In addition, the output can be fed back so that the variation in the driving capability of the intermediate voltage generating circuit can be reduced to the low power supply voltage. Since the intermediate voltage generation circuit has a high driving capability, the load capacity can be charged and discharged at high speed.

By using the output of the voltage converting means of the present invention as a power source of the word driver, it is possible to apply a voltage equal to or more than the threshold voltage of the switching transistor of the memory cell array as the word line voltage than the data line voltage. Therefore, the memory operation becomes stable even when the power supply voltage drops to about 1V.

SUMMARY OF THE INVENTION An object of the present invention is to provide an input / output control circuit method of an ultra-high density memory that operates at high speed even at low voltage.

Another object of the present invention is to provide an input / output control circuit method of an ultra-high density memory that operates stably even at low voltage.

It is another object of the present invention to provide a means for generating a sufficiently high word line voltage to prevent data destruction.

Still another object of the present invention is to provide an intermediate voltage generating means having a small output voltage variation even under a large load capacity.

1A to 1G show a first embodiment of the present invention;

2A to 2E are views for explaining the effect of the present invention;

3 is a view showing an embodiment to improve the effect of the first embodiment of Figures 1a to 1g,

4 is a diagram illustrating an embodiment in which a plurality of memory arrays are provided;

5A to 5F show an embodiment of a parallel test;

6 is a view showing an embodiment of writing an arbitrary write voltage to a memory cell;

7 is a view showing an embodiment of the present invention,

8 is a timing diagram showing the operation of the embodiment;

9 shows a prior art and a timing diagram thereof;

10 shows a prior art and a timing diagram thereof;

11 is a view showing an embodiment of the present invention,

12 is a timing chart showing the operation of the embodiment;

13 illustrates an embodiment of the present invention;

14 illustrates an embodiment of the present invention;

15 is a view showing an embodiment of the present invention;

16 illustrates an embodiment of the present invention;

17 is a timing chart showing the operation of the embodiment;

18 illustrates an embodiment of the present invention;

19 illustrates an embodiment of the present invention;

20 is a view for explaining the effect of the embodiment of FIG.

21A is a diagram showing an embodiment for explaining the basic concept of an intermediate voltage generating circuit of the present invention;

21B is a diagram for explaining the transient operation of the generation circuit of FIG. 21A;

Fig. 22 shows a conventional intermediate voltage generation circuit for DRAM;

23A is a diagram showing a specific embodiment of a DRAM using the intermediate voltage generation circuit of the present invention;

23B and 23C are views for explaining the effect of the intermediate voltage generation circuit of the present invention;

24A is a diagram showing an embodiment for explaining another basic concept of an intermediate voltage generation circuit according to the present invention;

24B is a view for explaining the operation of the intermediate voltage generation circuit of FIG. 24A;

25A is a diagram showing an embodiment of an intermediate voltage generation circuit of a DRAM;

25B is a diagram for explaining the effect of the embodiment of FIG. 25A;

FIG. 26A is a diagram showing an embodiment of an intermediate voltage generating means of a DRAM to which another basic concept of the present invention is applied;

Fig. 26B is a view showing a change in the intermediate voltage of the embodiment of Fig. 26A which occurs when the power supply voltage is changed during the memory operation.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

Best Mode for Carrying Out the Invention Embodiments of the present invention will be described below with reference to the drawings.

In the following description, an example in which the present invention is applied to a dynamic memory (DRAM) will be described. However, the present invention can be similarly applied to static memory (SRAM) and read only memory (ROM). Further, the present invention can be similarly applied to a memory using a bipolar element, a Bi CMOS type memory in which a bipolar element and a MISFET are combined, and a memory using a semiconductor material other than silicon.

Fig. 1A shows one embodiment of the memory circuit of the present invention. In FIG. 1A, the MA is a two-dimensional memory cell array of each memory cell consisting of one MISFET and one storage capacitor, CKT ₀ , CKT ₁ detects a memory cell signal and externally transmits information via a read / write line. Input and output control circuit, D ₀ and , D ₁ and Is a data line pair for transmitting a signal between the memory cell and the input / output control circuit, WD is a word line driver specifying a row address in the memory cell array to apply a drive signal to the word line, W _{0 to} W _m are word lines, and YD Is a Y (column) decoder designating a column address in the memory cell array, and Y ₁ represents a column select signal line, respectively. In the input / output control circuit, SA ₀ , SA ₁ are sense amplifiers for detecting the small signal voltage of the data line, CSN ₀ and CSP ₀ , CSN ₁ and CSP ₁ are the drive signal lines of sense amplifiers SA ₀ , SA ₁ , CD ₀ , CD ₁ is a drive signal generation circuit of a corresponding sense amplifier, PR ₀ , PR ₁ is a precharge circuit for shorting a pair of data lines corresponding to non-operation and setting a voltage suitable for operation of the sense amplifier, and RG0, RG1 are corresponding Lead gates that lead to the signal (voltage difference) appearing on the data line pair outside the memory array, T _{1 to} T ₄ are N-channel MISFETs constituting the lead gate, and WG ₀ and WG ₁ are corresponding data lines according to external information. The driving light gates, T _{5 to} T ₈ are N-channel MISFETs constituting the light gate, RO ₀ , , RO ₁ , Silver lead wire, WI ₀ , , WI ₁ , Is a light wire, RCS ₀ , , RCS ₁ , Is the lead control line, WR ₀ , , WR ₁ , Is light control line, SWR ₀ , SWR ₁ is common lead line CRO, SWW ₀ and SWW ₁ are common light wires CW1, SEL ₀ , SEL ₁ is a signal for selecting any one of the left and right switches, and AMP is CRO, A sense amplifier for detecting and amplifying a signal appearing on the screen, DOB represents an output buffer, and DIB represents an input buffer. In this embodiment, the input / output control circuits CKT ₀ and CKT ₁ are alternately arranged on the left and right of the memory cell array with respect to the corresponding data line pairs. The I / O line of the input / output control circuit is separated into a lead (RO) line and a light (WI) line. The specific structure and effect of these elements are described next.

FIG. 1B is a diagram illustrating an arrangement of a lead gate and a light gate. In general, as the memory density increases, it becomes more difficult to arrange the input / output control circuit Ci at the data line pitch. However, by alternately arranging the input / output control circuits on the left and right sides of the memory cell array as in this embodiment, the arrangement pitch of the input / output control circuit is twice or 2 dy the pitch of the data line pairs. Therefore, the arrangement of the input / output circuit can be achieved without increasing the chip area. Highly integrated memories are described, for example, in IEEE, Journal of Solid-State Circuits, Vol. 23, No. 5, pp. As described in 1113-1119 (issued in October 1988), there is a problem that the signal-to-noise ratio greatly decreases due to capacitive coupling between adjacent data lines. It is known that the capacitively coupled noise generated in the memory cell array is reduced by crossing the data lines with each other in the memory cell array. However, since the capacitive coupling between adjacent data lines in the input / output control circuit changes from place to place, the noise cannot be sufficiently reduced. In this embodiment, a shielding conductor (described later) is provided between the data line pairs of the input / output control circuit to significantly reduce the capacitive coupling noise between the data lines as compared with the conventional memory. In the arrangement of the input / output control circuit shown in Fig. 1B, a signal line is disposed between the signal line formed with the data line pair and the data line pair. In the present embodiment, for example, lead wires RO ₀ , which are arranged to intersect the data lines of lead gates RG i. And lead control line RCS ₀ , Is connected to the conductor formed with the data line via a through hole so that is parallel to the data line. By doing in this way, parasitic capacitance between adjacent data lines is reduced and coupling noise is suppressed to the minimum, and stable operation can be expected.

Next, the specific structures of the reed switch SWR ₀ , the light switch SWW ₀ and the sense amplifier AMP will be described.

1C shows several lead wire pairs ROi, One of the common lead line CRO, Is a diagram showing the structure of the reed switch SWRi (i = 0, 1) selectively connected to the. At the same time, the lead control line RCSi of the selected memory block, The voltage is controlled to lead the signal to the lead wire. In Fig. 1C, T _{10 to} T ₁₇ are N-channel MISFETs, INV ₁₀₀ is an inverter, and NAND ₁ is a two-input NAND gate that outputs a low level (low level) only when all of its inputs are high. The memory block is selected so that the selection signal Seli is high and the memory signal is in the read state. When is high, MISFETs T _{10 to} T ₁₃ are in a conductive state, and T ₁₄ to T ₁₇ are in a non-conductive state. Therefore, the lead wire ROi, Common lead line CRO, Respectively connected to the lead control line RCSi, Is grounded. By this, for example, when the column select signal Y ₁ in Fig. 1A becomes high, T ₃ and T ₄ become conductive and data line pairs D ₀ and Depending on the voltage difference between the lead wires RO ₀ , Lead control line RCS at ₀ , A signal is obtained, which is the difference between the currents flowing in. Lead control line RCS ₀ , When is separated, a parallel test for investigating defects in the memory cells can be executed as described later.

The memory block is unselected and the write signal is selected when the select signal Seli is low or the memory is written. When a low level, MISFET T ₁₀ ~T ₁₃ is whole, the non-T ₁₄ ~T ₁₇ is in conduction. Therefore, the lead wire ROi, And lead control line RCSi, Is changed to the same voltage level (in this case, the intermediate voltage level HVL). As a result, for example, in Fig. 1A, even if the column select signal Y ₁ becomes high level (high level) and T ₃ and T ₄ become conductive, lead wires ROi, Lead control wire RCSi, No current flows through the This is advantageous in the case of selecting column addresses in several memory blocks (including selected and non-selected blocks) by using one column select signal line as described, for example, in FIG.

1D is a diagram showing the structure of the light switch SWWi (i = 0, 1). This circuit is a pair of light wires Wii, One of the common light lines CWI, Selectively connect to At the same time, the write control line WRi of the memory block selected for the write purpose is set high. In FIG. 1D, T ₂₀ , T _{23 to} T ₂₆ are N-channel MISFETs, T ₂₁ and T ₂₂ are P-channel MISFETs, INV _{101 to} INV ₁₀₃ are inverters, and NAND ₂ represents two-input NAND gates, respectively. The memory block is selected so that the select signal Seli is high level and the write signal is written when the memory is written. When a high-level, T ₂₀ ~T MISFET ₂₃ is a T-conductive ₂₄ ~T ₂₆ is whole, non. Thus, the light wire Wii, Is the common light line CWI, The high level is output to the light control line WRi. Thus, for example, when the column select signal Y ₁ becomes high in FIG. 1A, T ₅ and T ₆ become conductive. Data line pair D ₀ , Is the wire pair WI ₀ , The write information on the write line is written to the data line.

When the memory block is unselected and the selection signal Seli is low level or the memory is in the read state and the write signal WE is low level, the MISFETs T ₂₀ to T ₂₃ become non-conducting and T ₂₄ to T ₂₆ become conductive. Thus, the light wire Wii, Is connected to the same voltage level (in this case, the intermediate voltage level HVL). At the same time, the write control line WRi goes low. As a result, for example, in Fig. 1A, even if the column select signal Y ₁ becomes high and T ₅ and T ₆ become conductive, the data line and the write line are not conductive. This is advantageous in the case of selecting column addresses of several memory blocks (including selected and non-selected blocks) using one column select signal line as described, for example, in FIG.

1E is a common lead line CRO, Fig. 1 shows the structure of a sense amplifier for amplifying the signal read in. In Fig. 1E, amp1 represents a common lead line CRO, Type d1, The first sense amplifier outputs a, amp2 is d1, Enter d2. The second sense amplifier outputs a, amp3 is d2, Enter d3. Refers to each of the third sense amplifier to the output, T _42, T ₄₃ is a MISFET for initializing the third sense amplifier prior to its operation. The first sense amplifier amp1 includes two current voltage conversion circuits of the same configuration, and the two current voltage conversion circuits are composed of a differential amplifier circuit DA1, a P-channel MISFET T ₃₀ , and an N-channel MISFET T ₃₁ . The second sense amplifier amp2 includes two differential amplifier circuits DA3 and DA4 of the same structure. The third sense amplifier amp3 includes two NOR gates NOR1 and NOR2 and two inverters INV ₁₀₅ and INV ₁₀₆ .

The operation of this embodiment will be described with reference to the operation waveforms of FIGS. 1F and 1G. Where data line D ₀ , Read information read in D0, and get information from D ₀ , An example in the case of writing to the above will be described. However, it is apparent that the same operation can be selectively executed for all memory cells in the memory array. Here, it is assumed that the operating voltage is 1.5V. However, the present invention is not limited to this, but can also be applied to other cases where other operating voltages are used to obtain the same effect.

First, the read operation will be described with reference to FIG. 1F. The control signal PC of the precharge circuit PR ₀ falls at time t ₀ , and the precharge operation (preliminary charging operation) to the data line ends. Subsequently, the selected word line W0 rises at time t ₁ and the data line d ₀ , in the memory cell. Leads to a signal. Next, at t ₃ , the sense amplifier drive signal CSP is changed from its intermediate voltage level to a high level, and the CSN is driven from its intermediate level to a low level to drive the sense amplifier SA ₀ . As a result, the signal read on the data line is amplified to a high level or low level by the sense amplifier. In this embodiment, and the data line connected to the gate of the transistor T _1, T ₂ RG0 in the gate through the transistor T _3, T ₄ lead RO _0, You are connected to. Lead control line RCS ₀ , of input / output circuit CKT ₀ selected in t ₁ Is driven low. This structure separates the data lines from the lead wires. Therefore, even if the column select signal line Y ₁ is input to the input / output circuit at t ₃ during the amplification before the data line is set to the high and low levels, the information on the data line is not destroyed. Therefore, the information of the data line can be transferred to the lead line without destroying the information of the data line. Thus, the read speed is increased. The reason and effect of speeding up the read speed compared with the prior art are explained in full detail below. Signal voltage RO ₀ , of lead wire and common lead wire , CRO, The voltage difference between them is about 20 mA, and the amplitude (d1) of the output signal of the first sense amplifier Voltage difference) is about 200 Hz, and the amplitude d2 of the output signal of the second sense amplifier Voltage difference) is about 1 to 1. 5V. That is, the voltage amplification ratio of the first sense amplifier is about 10, the voltage amplification ratio of the second sense amplifier is about 5-7, and the voltage amplification ratio of the third sense amplifier is about 1-2. The third sense amplifier has a function of storing output information, a so-called data latch function. That is, after the input signal is amplified, it is turned low to maintain the output corresponding to the input until the next input is received. This eliminates the need to keep all of the first to third amplifiers in an operating state all the time. After the signals are output from the first to third amplifiers, the power consumption can be reduced by making the first or second amplifiers or both amplifiers inactive.

Fig. 1F shows a so-called static column operation in which one information is read and then another information is read by selecting a corresponding column, i.e., the signal Y ₂₃ is raised after the column selection signal Y ₁ and the information is shown. Leads. According to the present embodiment, as will be described later, the voltage amplitude of the lead wire and the common lead wire is reduced to 20 mV, which is 1/10 of the voltage amplitude of the conventional lead wire and the common lead wire by supplying a current input to the sense amplifier. As a result, the time required for charging and discharging the parasitic capacitance of the lead wire and the common lead wire can be reduced to about 1/10 as compared with the prior art. In addition, the delay from selecting a new address to outputting information can be greatly shortened.

Following the read operation, an example of the write operation will be described according to Fig. 1G in which the first read operation is the same as in Fig. 1F. When WE goes high at t ₄ , the control signal line RCS ₀ of RG0 becomes HVL (0.75V) and becomes high by the column select signal line Y ₁ in which the control signal line WR ₀ of the write gate WG ₀ remains high. . At this time, the data to be written is the write I / O line WI ₀ , When applied to the data line DO through transistors T ₅ , T ₇ and T ₆ , T ₈ in write gate WG ₀ , The data is written to.

As described in the above example, the lead wire is separated from the light wire as one means of changing the transfer impedance between the I / O line and the data line in the write operation and the read operation. This makes it possible to individually set the read and write operation margins. As a result, speed and stabilization can be achieved even in a low voltage operation.

The effect of the sense amplifier used in this embodiment will be described with reference to FIG. Figure 2a shows a conventional sense amplifier, Figure 2b schematically shows the structure of a sense amplifier according to the present invention. 2C schematically illustrates operation waveforms of the sense amplifiers of the related art and the present invention. In the conventional sense amplifier, the data line D ₀ , ) A small signal read on the sense amplifier is a MISFET T _50, T ₅₁ is amplified by the SA ₀ controlled by the column select signals Y ₁ is turned on (ON), and the lead wire (IO _0, ) Conventional amplifiers have two problems that hinder their speed. One is that after the signal has been sufficiently amplified by the sense amplifier, it is necessary to turn on the MISFET. Otherwise, since there is a capacitance difference of several tens of times between the data line and the lead line, a large amount of charge flows from the lead line (approximately 8 ms of CR) to the data line (approximately 0.3 ms of CD). Thus, the amplified and started information is destroyed. On the other hand, it is necessary to amplify the lead wire having a large parasitic capacity to a large voltage such as 200 kW using a small sense amplifier. This is because a sufficient signal voltage is required by the second sense amplifier of the next stage.

To this end, in the present invention, the sense amplifier is separated from the lead line by providing a lead gate composed of the NMOS transistors T ₁ and T ₂ that receive the data line signal at its gate. In addition, these transistors are provided with a current sense circuit comprising a P-channel MISFET amplifier of complementary conduction type. In other words, by using the current as the input of the sense amplifier, the amplitude of the voltage of the signal line is reduced to obtain a voltage output proportional to the current input. By separating the sense amplifiers from the lead wires, the MISFETs T ₃ and T ₄ controlled by the column select signals can be turned on without waiting for the data lines to be sufficiently amplified. This converts the voltage information of the data line into current information in order to read at high speed. By using the current input type sense amplifier, the voltage amplitude of the signal line is suppressed by one digit (from 200 kHz to 20 kHz) compared with the prior art. As a result, the time required for charging and discharging the parasitic capacitance CR can be greatly shortened and the speed can be increased.

In the present invention, since the MISFET of the lead gate and the MISFET of the current sense circuit are complementary conductive types, this structure can provide a current sense circuit operating at the lowest voltage. The effect of this structure is described next. 2D shows various structures of the current sense circuit. In Fig. 2D, ISC _{1 to} ISC ₃ are current sense circuits, and RO ₀ is a common lead wire. The N-channel MISFET connected below RO ₀ simply shows the series connection of the lead gate and the select gate for convenience. In any case, to match the conditions, the RO line must be half of the supply voltage V _L. Biased to

In FIG. 2D, (i) is a common ground. A bipolar transistor and a resistor constitute the current sense circuit ISC ₁ . This circuit is described, for example, in ESSCIRC Digest of Technical Papers, pp. 184-187, published in September 1989.

(ii) is of the same type. The current sense circuit ISC ₂ is composed of a drive MOS transistor of the same conductivity type as the lead gate and a differential amplifier circuit. This circuit scheme is described, for example, in IEEE, Journal of Solid-State Circuits, Vol. 23, No. 5, pp. 1113-1119, issued October 1988.

(iii) is a complementary conductive type consisting of a drive MOS transistor of a complementary conductivity type and a differential amplifier circuit with a lead gate. In this case, the difference between the voltage on the RO line and the reference voltage is amplified to control the gate voltage of the MISFET for negative feedback. As a result, the amplitude of the voltage on the RO line is reduced. If the signal current is IS, the voltage amplification ratio of the differential amplifier circuit is A, the mutual conductance of the MISFET is Gm, and the sense output is ΔV, the amplitude of the input voltage is ΔV / A, and the sense output is ΔV = Is /. It becomes Gm. Therefore, if Gm is appropriately selected (it can be freely set according to the size of the MISFET) according to the value of the signal current, the amplitude of the input voltage is 20 Hz or 1 / compared with the prior art in which A = 10 and ΔV = 200 Hz. It can be reduced to 10.

The minimum operating voltages of these sense circuits are compared below. For the sake of simplicity, the following assumptions are made. The threshold voltages of all the MOS transistors are the same, the absolute value of this threshold voltage is V _T , the signal amplitude (dynamic range) of the sense output is ΔV, and the bias voltage of the lead signal line (RO line) is to be.

The operating conditions in the base grounding type of (i)

V _L V _L / 2 + VCE + △ V

Is given by

Therefore, the minimum operating voltage

V _L 2 (VCE + △ V)

Is given by

Where VCE is the voltage difference between the collector and the emitter. In order to avoid saturation operation of the bipolar transistor, it is necessary to set VCE to a certain value (for example, 0.7 V or more). ΔV is the signal amplitude of the sense output. In consideration of the margin of operation, the amplitude is preferably secured to more than 0.4V. Therefore, the minimum operating voltage is 2. 2V.

The operating conditions in the same type of (ii)

V _L V _L / 2 + V _T + △ V

Is given by

Therefore, the minimum operating voltage

V _L 2 (V _T + △ V)

Is given by

If the threshold voltage V _T is 0.5V, the minimum operating voltage is 1.8V.

A problem with the conventionally proposed schemes (i) and (ii) is that the RO line is connected to the emitter of the bipolar transistor or the source of the MISFET. Therefore, the voltage difference between the base-emitter or the threshold voltage needs to be assigned to a value between the power supply voltage V _L and the bias voltage V _L / 2 of the RO line. On the other hand, in the present invention, as described in (iii), the driving element and the lead gate are each composed of complementary conductive PMOS transistors. The drains of these transistors are connected to the RO line so that there is no restriction on the voltage. The operating condition and minimum operating voltage of the current sense circuit in the complementary conductive type

V _L V _T + △ V

Is given by

If the threshold voltage V _T is 0.5V, the minimum operating voltage is 0.9V. As a result, the complementary conductive current sense circuit of (iii) is most suitable for low voltage operation.

Figure 2e is a diagram showing the comparison of the operating speed of the conventional and the sense amplifier of the present invention according to the results of the computer simulation. The sense time is defined by the delay time after applying the signals CSN and CSP to start the sense amplifier until a signal voltage of 200 Hz is obtained on the I / O line (in the case of a conventional voltage sense amplifier). Or the delay time from the application of the signals CSN and CSP to the first sense amplifier until an output of 200 Hz is obtained (in the case of a voltage sense amplifier). All voltage sense types operate at high speeds. However, the minimum operating voltages of the base ground type and the same type are 2.5V and 1.9V, respectively, and these amplifiers do not operate at 1.5V. This is in good agreement with the above-described analysis results. On the other hand, in the complementary conductive type sense circuit, the minimum operating voltage is 1.25V and operates at a high speed up to the lowest voltage. The lower limit of the operating voltage is not determined by the operation of the sense circuit itself, but by the lower limit of the operating voltage of the sense amplifier that amplifies the data line signal. In other words, the sense circuit itself is operable at a voltage of 1.25V or less. Compared with the conventional voltage sense type, the present invention speeds up to 20 mA at 1.5V.

As described above, in this embodiment, the input / output control circuits are alternately arranged on the left and right sides of the memory cell array, and the read and write input / output lines are separated from each other so that stable operation can be achieved even at high speed and low voltage operation of the DRAM. The first sense amplifier for detecting the signal of the lead wire is constituted by a current voltage converting circuit, and the MISFET for the lead wire driving and the MISFET for converting the voltage of the data line into the current through the lead wire are used. There is provided a sense amplifier system that operates at high speed even at low power supply voltages such as 1 to 2 V.

3 is a diagram illustrating an embodiment for more stable operation. As described above, the parasitic capacitance between the data lines is reduced in the input / output control circuit. In this embodiment, a more stable operation is achieved by balancing the parasitic capacitance between the data lines in a part of the memory cell array. For this purpose, the data lines are arranged in pairs at the center of the memory cell array. D ₁ and the data line Between and And Parasitic doses between are C _C 1 _L and C _C 1 _R, respectively. C _C 1 _L and C _C 1 _R coincide, so D ₁ and Between and And The parasitic capacity in between is the same. Similarly, between D ₁ and data line D2 and The parasitic capacitance between and data line D2 is also the same. Therefore, the parasitic capacitance between each pair of data lines and other adjacent data lines is also the same, so that the read operation can be further stabilized even in the memory cell array.

4 is a diagram illustrating an embodiment including a plurality of memory cell arrays. Here, the read operation will be described. The input / output control circuit CKTij is shared by the memory cell arrays arranged on the left and right of the input / output control circuit. The switching transistors T ₆₀ and T ₆₁ are arranged between the memory cells array adjacent to CKTij and the switching transistors T ₆₂ and T ₆₃ are arranged between the other memory cell arrays adjacent to CKTij. The switching transistor SHRij, which is a memory cell array selection signal, is input to its gate. SWRi is a switch for connecting the common lead wire CRO shared by the lead wire RO and a plurality of RO wires including the lead wire RO. The memory cell array selection signal SHRij is input. SHRij is set to high in advance. For this reason, for example, when memory cell array MA ₂ is selected, only SHR _1R and SHR _{3L go} low. It is assumed here that the column select signal Y ₁ is selected. Data line D ₁ , And D ₀ , The signal read to RO ₁₂ , through the input / output control circuit CKT ₁₂ , CKT ₂₃ . , RO ₂₃ , Leads to. These signals are also passed through the switches SWR ₁ and SWR ₂ to the common I / O line CRO ₀ , , CRO ₁ , Leads to. As described above, even if a plurality of memory cell arrays exist, the input / output control circuits are alternately arranged on the left and right sides of the memory cell array, so that sharing by adjacent memory cell arrays does not significantly increase the chip area. Therefore, the improvement to the above-mentioned characteristic can be realized.

FIG. 5A illustrates an embodiment of the present invention for examining defects in memory cells in parallel. Parallel testing is performed by selecting several column selection signals simultaneously. That is, in the parallel test, several column selection signals are selected by the test signal TEST. As a result, at the time of the read, the read signal from the data line is simultaneously read to the lead line according to the multiplicity. If the information of the data lines read at the same time is identical, lead wires RO, One of them goes high and the other goes low. If at least one misleading is lead, RO and All low. In the write operation, data is written to the data line connected to the light gate selected by the write input / output line. A feature of the present invention is that it is not necessary to prepare a new test I / O line even in parallel test. Therefore, data is transferred from the data line to the AMP as in the normal test. Further, since the read signal line is separated from the write signal line, the separation operation margin can be set for each of the read and write operations as described above. Thus, there is no limit to the increase in multiplicity, and a high degree of parallel read / write operation is achieved. In Fig. 5A, there is a pair of drive signal lines RCS with respect to the lead gate RG. The RCS lines connected to are separated from each other. This is a valid means for determining one order operation even when the multiplicity is increased. When multiplicity is increased, it is necessary to increase the current flowing from RO to RCS. On the other hand, the current flowing from the RCS to GND is saturated to an arbitrary value by the wiring resistance of the lead wire, thereby increasing the voltage level of the RCS. Therefore, if the RCS is not separated, the signal current of the I / O line on the side where the duck was on is lowered as the degree of multiplicity increases, making it difficult to detect. Since the voltage level of the RCS on the side where the order was removed does not rise by separation of the RCS, only the current flowing from the RO to the RCS needs to be detected, so that high precision detection can be performed.

As described above, the present invention can achieve a high degree of parallel testing, thereby greatly reducing the test time.

5B is a diagram illustrating an embodiment of a specific circuit for determining multiplicity. In other words, Y _{0 to} Y _n-1 are input to the column decoder YD. Y _n-1 is divided into two in the column direction, and Y _n-2 is divided into four. Y ₀ repeats the transition state from '0' (low) to '1' (high) in response to each column selection signal. Here, the test signal TEST is set high and Y _n-1 , And OR gate output signals according to TEST and AY _n-1 and AY _n-1 ′. These signals are represented by Y _n-1 , Instead, by inputting to the column decoder, the signals AY _n-1 , AY _n-1 , 'are all high regardless of whether Y _n-1 is high or low. Therefore, since two column selection signals can be selected, the multiplicity can be set to two.

5C is a diagram illustrating an embodiment in which multiplicity is four. The NAND gate outputs for Y _n-1 and Y _n-2 are input to the corresponding NAND gate with TEST, and their outputs AY _{n-20 to} AY _n-23 are input to the column decoder when the multiplicity is four. . 5B and 5C, the multiplicity of the column decoder can be selected during parallel testing. In the normal test, one column select signal is selected by setting the test signal TEST low.

5D is a diagram showing an embodiment of a sense amplifier for implementing parallel test. A method of outputting the result of the parallel test will be described with reference to FIG. 5D. In the normal read operation, the output obtained by the current voltage conversion is input to the inverting and non-inverting terminals of the two differential amplifier circuits DA4 and DA5 constituting amp2T. The output of amp2T is input to amp3. In parallel testing, V _{RT is} applied as the reference voltage to the noninverting inputs of the two differential amplifier circuits DA4 and DA5. In a parallel test, if at least one of the false information is on a multiselected data line, RO and In both current flows. Accordingly, the current voltage conversion output d1 of the first sense amplifier amp1, Goes low. The reference voltage V _RT is preset to a voltage between the high and low levels of the current voltage conversion output. In this case, when at least one misinformation is included, the outputs of the two amplifiers DA4 and DA5 go high. On the other hand, voltage level d2, If is high, it can be determined that the information read in parallel includes false information. In parallel test, to input the outputs from DA4 and DA5 to the judgment circuit TEJ. To low. If the results of the parallel test are all correct, ERR outputs low. If at least one of the results is incorrect, ERR outputs high. By doing in this way, the result of the parallel test which increased the multiplicity can also be discriminated using the input / output circuit system and the sense amplifier which concerns on this invention.

FIG. 5E is a diagram showing an embodiment of a reference voltage V _RT generating circuit used for parallel testing. 5E also uses the above-described current voltage conversion circuit. In the parallel test, _VRT is generated by setting the parallel test signal TEST high. In this circuit, the reference current corresponding to 1/2 of the signal current is applied to the input of the current voltage converting circuit. As a result, when the signal current flows through the RO lines on both sides, the voltage after conversion becomes smaller than V _RT . If the result of the parallel test is correct, the voltage after one conversion is larger than V _RT . Therefore, the test result can be discriminated by comparing the voltage after conversion with V _RT .

5F illustrates a specific embodiment of the light switch SWW. Here, WE is a write signal. This embodiment is a case where there are several memory cell arrays shown in FIG. Assume that the memory cell array on the right side of the SWW is operating (SELR is high and SELL is low). TEST is low for parallel testing. WE goes low during lead operation, WI, Is set to the same voltage level by the circuit WST. When the write operation is started, WE goes high. The signals input to GR are all high during the read operation. Thus, WER goes low and WEL goes high. For this reason, the write control signal WR goes high. In addition, CWI, via N-channel MISFETs T ₇₇ , T ₇₈ and P-channel MISFETs T ₇₅ , T ₇₆ In WI, The data is written to.

FIG. 6 shows an embodiment in which the voltage level of the power supply voltage line on the high voltage side of the sense amplifier for detecting and amplifying a signal read from the memory cell to the data line can be set to an arbitrary level. The write voltage level used when '1' is written in the memory cell is the voltage level of the power supply voltage line on the high voltage side of the sense amplifier. Therefore, it is necessary to set the voltage level of the power supply voltage line on the high voltage side to an arbitrary level. In this case, two kinds of power supply voltages are provided on the high voltage side, and one power supply voltage line is used as V _DL for normal light purposes. The power supply line V _DM is arranged to be set to an arbitrary value outside the chip. As a result, when the signals MT0 and MT1 go low, the drive signal CSP of the sense amplifier becomes V _DL . On the contrary, when the signals MT0 and MT1 go high, the drive signal CSP of the sense amplifier becomes V _DM . According to this embodiment, only the voltage level of the information '1' can be set to an arbitrary value. Further, the voltage level of the information '1' can be changed and set every other pair. Therefore, every pair of threshold voltages at which information is inverted can be written as in the case of testing the coupling noise between data lines. This is also valid for margin testing. It is also effective in reducing the time required for testing the information retention characteristics of the memory cells.

9 and 10 show a conventional word driver.

As shown in Fig. 9, the word driver WD is composed of transistors Q _D and Q _T. Output N ₁ of the X decoder XD is when a high (V _L), the gate of the N ₂ Q _D is charged via the Q _T is in a state where Q _D on. At this time, the voltage of N ₂ is V _L -V _T. The word line driving signal Φ _X (having an amplitude equal to or greater than V _L + V _T ) generated by the peripheral circuit FX becomes high, and the word line W is made high by flowing current from the drain of Q _D to its source. . At this time, the voltage difference between the gate and the Q _T N ₁ is 0 in the voltage between the gate and the Q _T N ₂ so as V _t, Q _T is in the off state. Thus, as Φ _X rises, the voltage of N ₂ rises with Φ _X by coupling by the gate-source capacitance of Q _D. When the gate-source voltage difference of Q _D is greater than or equal to V _T when Φ _X reaches its maximum value, the voltage of the word line becomes equal to Φ _X. When trying to Φ _X increases in Q _D gate - when the voltage difference between the source in the same manner as V _T less than or V _T, the gate of Q _D - source capacitance is to the time that the voltage increase of the N ₂ Stop 0 , As shown in FIG. It becomes The word line voltage becomes (V _L -2V _T ) / (1-α). Is the ratio of the gate capacitance of Q _D to the total capacitance of node N ₂ .

7 and 8 show one embodiment of a word driver (word driver circuit) according to the present invention. This embodiment is characterized by using a static word driver consisting of Q _D1 , Q _D2 , Q _P and Q _T instead of the conventional dynamic word driver. In addition, the voltage conversion circuit VCHG is provided as a power supply for generating a high voltage of V _T or the data line voltage V _L of the switching transistor Q _S of the memory cell. The operation in this embodiment will be described next. First, when X decoder XD is selected by the address signal Ai, the output N ₁ of the X decoder XD goes low. Then, through the transistor Q _T is drawn out of the electric charge of the node N ₂ is also a low N _2. As a result, the transistor Q _D1 is turned on, the word line W is raised to the V _CH level, and information is written to the memory cell CS.

Next, in the precharge cycle, Becomes low level, Qp is turned on, and node N _{2 is set} to V _CH . As a result, since Q _D1 is turned off and Q _D2 is turned on, the word line W is turned low to hold charge in the memory cell.

As described above, in this embodiment, the voltage of the word line can be set to the maximum V _CH voltage output by the word line voltage conversion circuit VCHG. Since the word driver operates when the gate voltage of the driving transistor is at the low level, the word driver operates stably as a word driver even when the power supply voltage is lowered.

FIG. 11 illustrates a specific embodiment of the word line voltage conversion circuit VCHG of FIG. 7. Fig. 12 shows internal waveforms and input timings generated when the circuit is started. This embodiment is characterized in that the feedback and an N-channel MOS transistor (Q _B in Fig. 11) for pre-charging its output voltage in the charge pump circuit CP in order to obtain quick rising and high output voltage in the low power supply voltage.

First, input pulse ψ, Let be the high and low levels, respectively. At this time, since the voltage of the node B is charged by the internal power supply voltage via Q _C , it becomes V _L -V _T. The node A becomes a voltage value determined by the charges stored in the capacitors CA and CD and the amplitude of ψ. In this embodiment, this voltage is assumed to be V _L. Next, ψ and When the voltages of V are replaced with each other, the voltage of the node B is stepped up by the capacitor C _B to become V _L -V _T + αV _L. Where α is the ratio of the total capacitance of C _B and Node B. At this time, the voltage of the node A becomes V _L -2V _T + αV _L which is less than V _T of the N-channel MOS transistor Q _A than the voltage of B.

Next, again ψ, When the voltages of A are replaced with each other, the node A is boosted again. If this is higher than V _L , the voltage of node B is precharged to V _L -V _T by N-channel MOS transistor Q _C , so that N-channel MOS transistor Q _B is turned on to reduce the voltage of node B. It also raises by δ. Thus, in the next cycle, Node B is raised to a higher voltage level, and the voltage at Node A is also raised. By repeating this operation, the voltage of the node A is raised, and finally, the reciprocating between V _L and 2V _L is performed.

This output is connected to the rectifier circuit 2 or the diode-connected MOS transistor Q _D. The smoothed capacitor C _D is connected to the output of Q _D to obtain a boosted direct current (DC) voltage V _CH , which becomes 2V _T -V _T under no load.

The circuit connecting Q _A and C _A is divided into two circuits. One of the connection points of the MOS transistor Q _A and the capacitor C _A is connected to the rectifier circuit 2, and the other is connected to the gate of Q _{B so that} the gate of Q _B is separated from the load circuit. Therefore, the gate voltage is increased by the amount corresponding to the fact that no current flows in the load circuit, so that the voltage of the node A can be raised more quickly. In Fig. 11, Q _A , Q _B and Q _{C to} Q _E are N-channel MOS transistors, respectively.

The characteristic of this circuit is to supply a high output voltage even at a low power supply voltage by increasing the precharge voltage by returning the output voltage to the precharge circuit as described above. For example, V _L = 0. 8 (V), V _T = 0. When 5 (V) is set, the voltage at node B is maximum when there is no feedback or when there is no Q _B. It does not exceed 1V (2V _L -V _T when α = 1). As a result, the voltage at node A is 1.4V (3V _L -2V _T ) and the output voltage _VCH is 0.9V (3V _L -3V _T ). In contrast, when Q _B is present, the voltage at node B, the voltage at node A, and V _CH are respectively 1.6V (2V _L ), 1.6V (2V _L ), and 1.1V (2V _L -V _T ). It becomes higher than the former value. It can be understood that the word line driver of the present invention is superior to the conventional word line driver when the high voltage generation circuit is used as a power source.

20 is a view showing the comparison result of the step-up ratio of the feedback transistor word line voltage converter circuit (present invention) and the non-word line voltage converter having a feedback circuit for the transistor Q _B (prior art) having a Q _B for. In FIG. 20, the solid line shows the case where the threshold voltage of the transistor is standard, and the dotted line shows the case where the threshold voltage of the transistor is low. In Fig. 20, in the prior art, the boosting rate is 1 to 1. It is understood that the voltage is rapidly decreasing at 5V. On the contrary, in the present invention, it can be seen that the word-voltage voltage conversion circuit operates stably even at a low power supply voltage because the boost ratio is constant up to 0.8V. It is assumed here that there is no voltage drop in the rectifier circuit due to the threshold voltage of the transistor.

FIG. 13 illustrates that the output is also drawn from the node B of FIG. 11. The outputs at the nodes A and B output about twice as much V _L by compensating each other on the time axis, so that a more stable output is obtained.

FIG. 14 is a diagram showing a circuit in which the amplifier stages Q _A2 and Q _E2 are provided in the circuit of FIG. 11 and the output is separated from the gate of Q _B. As a result, the gate voltage of Q _B is prevented from being lowered by the output. As a result, this output voltage can be increased twice more at high speed.

In FIG. 15, the amplification stages Q _B2 and Q _C2 and the rectifying transistor Q _D2 are additionally provided in the circuit of FIG. 14 to obtain a high speed rise of the output voltage and a stable output.

16 and 17 show an embodiment having a circuit for generating a high output voltage using the circuit of FIG. Although this embodiment uses the circuit of Fig. 11 for simplicity, it is apparent that higher output voltages can be obtained by using the circuits of Figs.

The characteristic of this embodiment is to synchronize the gate voltage of the rectifying transistor with the output voltage of the charge pump circuit in order to reduce the voltage drop in the rectifying transistor, and when the output is at the high level (2V _L ), the gate voltage is higher than _VT . The gate voltage is set to V _L when the output voltage is high and the output is at a low level (V _L ).

In Fig. 16, CP and Q _D are charge pump circuits and rectifier circuits, Q _{1 to} Q ₁₉ , and C _{1 to} C ₄ are added elements, and Q ₁ is a rectifying transistor, Q _{3 to} Q ₁₀ and C _1. ? C ₃ is a gate voltage control circuit for controlling the gate voltage, Q ₁₁ ? Q ₁₃ , Q ₁₅ ? Q ₁₈ and C ₄ are the charge circuits for the gate boost capacitor C ₃ , and Q ₁₉ is a fast rising of V _CH . Pracharge transistors, PA, The control signal of the charge pump circuit, PB, Denotes a control signal of the gate voltage control circuit.

In operation, the CP represents the charge pump described above. PA, By alternately going high and low, the voltage at node A is stepped up and changed between V _L and βV _L (β # 2). At this time, PA, As shown in FIG. 8, high periods do not overlap each other. This is the above in FIG. Corresponds to Does not fall completely to 0V, if ψ corresponding to PA rises to the voltage at node A when the voltage at node B is still above V _L + V _T , QA is on and accumulates in CA. This is because the charged charge leaks to the power supply side via QA.

In the rectifier circuit, PA, PB is low, When is high, the gate of Q ₄ is stepped up by V ₁ or more than V _L + V _T. Therefore, the voltage of the gate G of Q ₁ becomes equal to V _L. At this time, since node A is at V _L , there is no reverse flow of node A from V _CH . After gate of Q ₁₁ precharges C ₄ to 2V _L -V _T by Q ₁₃ , Q ₁₈ Since it boosts to (V _L ), the gate of Q ₁₁ becomes 3V _L -V _T. Thus, if V _L ≥2V _T is boosted to _{V CH (2V L) + V} T more than the node C is a V _CH. At this time, the gate Q ₁₀ - because the voltage difference between the source V _CH -V greater than V _{T L,} Q ₁₀ is a on-gate voltage of Q ₉ becomes equal to the voltage at the node C. Therefore, Q ₉ is turned off and no current flows from node C to node G.

PA, PB is high, When is low, the voltage at node A becomes 2V _L and the voltage at node C becomes V _L + V _CH . Since the gate of Q ₇ is stepped up by V ₃ or more than V _L + V _T , its source voltage becomes V _L. In other words, the gate voltage of Q ₉ is V _L. Therefore, the gate-source voltage difference of Q ₉ is V _CH . Thus, Q ₉ is turned on and the gate of Q ₁ is V _L + γV _CH (γ # 1). Thus, the 2V _L is output without Like the embodiment of Figure 11-day output drops as V _T.

In this embodiment, the PB is changed to low level before the PA to prevent the charge from being retained at the output to Node A. When PB and PA simultaneously change to the low level, the gate voltage of Q ₁ becomes more than V _L + V _T and the voltage of node A becomes less than V _L. It causes charge to detain from the output to node A. The reason why the lowest potential of the gate control circuit is set to V _L , such as the sources of Q ₄ and Q ₇ , is to reduce the voltage difference between the electrodes of the transistor. As a result, the voltage difference between the transistor electrodes becomes 2 V _L or less, so that the same fine transistor as in the other circuit can be used.

The above is the characteristic of the Example of FIG. However, similar effects are obtained even if Q ₇ and Q ₁₀ are deleted in FIG. 16 and the gate of Q ₉ is connected to the gate of Q ₄ . For example, if PB is V _L , When is 0, the node C becomes V _CH + V _L and the gates of Q ₄ and Q ₉ become V _L. Therefore, Q ₄ turns off, Q ₉ turns on, and the node G turns to V _CH + V _L. PB is 0, Is V _L , the node C becomes V _CH (2V _L ), and the gates of Q ₄ and Q ₉ become 2V _L. Therefore, Q ₄ is on, Q ₉ is off and the node G is V _L.

18 and 19 show a circuit for generating the timing signal used in FIG. In Fig. 18, inverters I _{5 to} I ₈ , resistor R ₂ , capacitor C ₂ , NAND gate NA ₂ and NOR gate NO ₁ are PA, Circuits to prevent overlapping, and I ₂ , I ₃ , R ₁ and C ₁ constitute a circuit for determining the fall delay time of PA and PB, and I _{9 to} I ₁₃ and NA ₃ represent PA and A circuit for generating the fall delay of the PB is configured, and I _{14 to} I ₂₅ are buffer inverters. The number of stages of the buffer inverter may be several stages as long as the even number and the number of stages are the same. The number of stages of the inverter may be adjusted according to the size of the load.

FIG. 19 shows a circuit generally called a ring oscillator for generating an input pulse osc in the circuit of FIG. This circuit is characterized in that the time constants of R and C are selected so as to be sufficiently larger than the delay time of the inverter in order to suppress fluctuations in the oscillation frequency due to variations in the power supply voltage. Therefore, even if any abnormality is V _T ratio of the power supply voltage of the third transistor also the delay time of the inverter highly dependent on the supply voltage frequency of oscillation is stable.

In addition to the above countermeasures, the operation of the memory at low voltage is further stabilized by reducing V _T of the transistors of the embodiments of FIGS. 11 and 16. This is because the driving capability of the transistor increases by the reduction of V _T. As the V _T decreases, the sub-threshold current increases. However, since the voltage conversion circuit includes at most ten elements, the sub-threshold current can be largely ignored, considering the entire chip. Word driver and the drivability of the memory cell transistor is increased by the reduction in V _T. However, since 10 ³ to 10 ⁴ electrons are used in the M-bit class DRAM, the leakage current flowing when the transistor is off cannot be ignored. In the latter case, the time required to hold the electric charges is reduced to shorten the regeneration interval. This increases the power consumption. Therefore, it is most preferable to set V _T low in the voltage conversion circuit, high in the word driver, and high in the memory cell.

20 shows a comparison between the present invention and the prior art. As is apparent from Fig. 20, the boost ratio in the present invention is higher than that in the prior art under low power supply voltage.

As described above, according to this embodiment, the threshold value than the drain voltage of the rectification transistor, the gate voltage of the rectification transistor voltage V _T or higher can be set to a high value. In addition, since the arrest of charge is also prevented, the output voltage is increased to 2V _L which is a logic value of the double voltage generating circuit. By using the oscillation circuit and the timing generator circuit using RC delay, the oscillation frequency and the timing mutual delay time become stable against the power supply voltage fluctuation. Therefore, the voltage conversion efficiency can always be maintained at the best state. Providing a V _T of the transistors 3 type, and the lower V _T the voltage converting circuit, in the word driver in a standard memory cell is higher than the standard. This makes it possible to stabilize and speed up operation at low voltage, increase the operating speed, and reduce the power consumption. Therefore, it is possible to realize a semiconductor integrated circuit which operates stably even in an electromotive force generated by a single battery with a power supply voltage.

Hereinafter, an intermediate voltage generation circuit used in the present invention will be described. In the following description, VCC is used as a symbol representing the higher power supply voltage. However, VCC may be replaced with V _L since it does not need to be different from V _L used so far. HVC is used as a symbol representing the intermediate voltage. However, HVC can be replaced with HVL since it does not need to be different from HVL used so far.

FIG. 21 is a diagram showing the structure of a voltage follower circuit for outputting the same voltage as the voltage applied to the input and driving a large load capacity. Fig. 22 is a diagram showing a conventional structure in which a sufficient current output cannot be provided when the load capacity is increased by high integration of the LSI. It is low in driving capacity and its output voltage fluctuates greatly. Hereinafter, the present invention will be described. In Fig. 21A, (i) shows a first complementary push-pull circuit including an N-channel MOS transistor TN2 and a P-channel MOS transistor TP2 and bias voltage sources VN1 and VP1. (ii) shows a current mirror type push-pull amplifier circuit including a pair of P-channel MOS transistors TP1 and TP3 constituting a current mirror circuit different from the pair of N-channel MOS transistors TN1 and TN3 constituting the current mirror circuit. (iii) shows a second complementary push-pull circuit comprising N-channel MOS transistors TN4 and P-channel MOS transistors TP4 and bias voltage sources VN2 and VP2.

The constant setting and operation in the steady state of various transistors and voltage sources of this circuit will be described below. The values of the power supply voltages VN1 and VP1 are selected to be equal to the gate threshold voltages of the transistors TN2 and TP2, respectively. As a result, it is possible to avoid the transistors TN2 and TP2 being blocked at the same time under any operating conditions. Thus, the output impedance is increased to change the voltage level or the output voltage is prevented from changing by the load condition. The value of the power supply voltage is equal to the gate threshold voltage of the transistor. As a result, the current flowing through the two transistors in the steady state is suppressed to a low value. High load driving capability is achieved while reducing the power consumed when the integrated circuit is in the standby state. The operation of the transistor under such a bias condition is generally referred to as class AB operation.

If the current values flowing through TN2 and TP2 are IC1 and ID1, respectively, these currents are respectively obtained by a current mirror circuit including a pair of P-channel MOS transistors TP1 and TP3 and a pair of N-channel MOS transistors TN1 and TN3, respectively. The current flows through TN3 to IC2 and ID2. The current ratio of IC2 to IC1 is equal to the β ratio of transistors TP3 to TP1, and the current ratio (mirror ratio) of ID2 to ID1 is equal to the β ratio of transistors TN3 to TN1. In other words,

to be. By setting this ratio to a value of 1 (single) or more, the current can be amplified to increase the driving capability of the load (terminals 6 and 7) of the next stage. In this circuit, the ratio is selected to a value of about 1 to 10. The values of the power supply voltages VN2 and VP2 are selected to be equal to the gate threshold voltages of the transistors TN4 and TP4, similarly to the first complementary push-pull circuit. As a result, the class AB operation is performed with the second complementary push-pull circuit.

Hereinafter, what happens when the first complementary push-pull circuit deviates from the normal state, that is, the state where IC1 = ID1 is established. The current value generated when the output voltage is forcibly changed by the voltage δV from the steady state is shown as follows.

Here, β _N and β _P denote β values of the transistors TN 2 and TP 2, respectively, and I denotes a current flowing through the first complementary push-pull circuit in a steady state, that is, I = IC 1 = ID 1.

Hereinafter, for simplicity, it is assumed that the characteristics of TN2 and TP2 are the same or that β _N and β _P are the same (β = β _N = β _P ).

The formula is

Is converted to.

Assuming that the mirror ratios of the two current mirror circuits are the same (M = M _N = M _P ),

It becomes

For example, M = 5, β = 1 μs / V ² _, I = 0. When the output voltage is set to 2 kV, IC2-ID2 = 20 kV when the output voltage decreases to 0.01 V (? V = 0.1 V).

When the output voltage slightly changes to 0.1 V, a drive current of 20 mA is sufficiently large with respect to the steady state current 1 mA (0.2 mA x 5) of IC2 and ID2. Therefore, even if the output voltage changes minutely, the terminal 6 can be driven to the minimum VSS and the terminal 7 to the maximum VCC. That is, the complementary push-pull circuit 3 can be driven to the limit of the power supply voltage range. In the driving direction, the terminal 7 is driven to VCC when the output voltage decreases, and the terminal 6 is driven to VSS when the output voltage rises. As a result, when there is an error in the output voltage, the second complementary push-pull circuit can be driven by the signal with the amplified error, thereby eliminating the error in the output voltage. Thus, the present invention has a high driving capability compared to the prior art driven only by the small follower. Even if the bias current in the steady state is suppressed to a sufficiently low value, a high driving current can be obtained by amplifying the error. As can be easily understood from the above equation, since this circuit operates symmetrically with respect to the direction of error, the same driving capability can be obtained for charging and discharging the output. The precision as a voltage follower circuit of this circuit will be described. This circuit uses a first complementary push-pull circuit to detect an error in the output voltage. The second complementary push-pull circuit is driven by the amplified and detected error signal. Therefore, the accuracy (input / output voltage difference) of the output voltage is determined by the voltage precision (input / output voltage difference) of the first complementary push-pull circuit. In the first complementary push-pull circuit, when a steady state or a condition in which IC1 = ID1 is obtained, the relationship between the input voltage V (IN) and the output voltage V (OUT) is given as follows.

here, And VTN and VTP are absolute values of the gate threshold voltages of the N and P-channel MOS transistors, respectively. As is apparent from the above formula, VN1 and VP1 have characteristics that change with the change of VTN and VTP, respectively. Optionally, the β value of the transistor is appropriately selected. By doing this, even if the device characteristics of the N-channel and P-channel transistors change independently by, for example, a non-uniform manufacturing process, the voltage difference between the output and the input can be zero. The power supply voltage will be described in the following embodiment. The gate and the drain of each channel conductive MOS transistor are connected. The above-described power supply voltage is easily configured by allowing a predetermined current to flow through the MOS transistor. In general, transistors of the same conductivity type go through the same fabrication process. Therefore, even if the element-to-element characteristic of another conductivity type changes, the element-to-element characteristic difference is suppressed to a sufficiently small value. In particular, considering the nonuniform process configuration, the gate width and length are designed to have a sufficiently large value compared to the processing precision. As a result, the characteristic difference between the elements is further reduced. Take the gate threshold voltage as an example. The voltage difference between devices of the same conductivity type can be easily reduced to about 20 to 30 mA or less, so that the difference between the devices of different conductivity types is about 200 mA at most by one order of magnitude compared to the devices of the same conductivity type. It becomes big. As described above, the voltage accuracy (input / output voltage difference) of the first complementary push-pull circuit is suppressed to about 20 to 30 kΩ determined by the threshold voltage difference of the transistor, and these values are lowered by one order of magnitude compared to the prior art. .

The operation of overshowing the voltage follower circuit will be described with reference to FIG. 21B. In the following, it is assumed that the input voltage V (IN) falls across t ₁ at time t ₀ and rises over t ₅ at t ₄ . Since the output does not immediately follow the drop of the input voltage, the transistor TN2 is cut off from time t ₁ to t ₂ and the value of the current IC1 becomes zero. On the contrary, ID1 increases to lower the voltage V6 of the terminal 6 to VSS (0V). As a result, the driving capability of the transistor TP4 is increased to discharge the output OUT at a high speed. When the input / output voltage difference decreases after time t ₂ , the transistor TN ₂ starts to conduct. At time t ₃ when the voltage difference between the input and output finally decreases to 0, IC1 = ID1 is brought to a steady state. When the input voltage rises, the voltage at terminal 7 increases symmetrically with respect to the rise of the input voltage to charge VCC at high speed.

As described above, the intermediate voltage generator circuit makes the error between the input and output voltages small even when the characteristics of the transistor manufacturing process change. In addition, a voltage follower circuit capable of charging and discharging a large capacity load at a high speed is provided in an over-show. In addition to the operation of the voltage follower circuit, this circuit may be used as a high performance current detection circuit by supplying a signal current to the output terminal OUT and extracting the output from the terminal 6 or the terminal 7.

An embodiment in which the above-described circuit is applied to the intermediate voltage (VCC / 2) generation circuit system of the dynamic memory will be described with reference to FIG. Fig. 23A is a diagram showing the configuration of a specific intermediate voltage generation circuit. In Fig. 23A, reference numeral 30 denotes a reference voltage generator circuit, 31 denotes a first complementary push-pull circuit, 32 denotes a current mirror amplifier, and 33 denotes a second complementary push-pull circuit. The reference voltage generating circuit generates an intermediate voltage at the terminal 34 by dividing the power supply voltage by half with two resistors R3 and R4 having the same resistance value. By using the same kind of elements as the resistors R3 and R4, an intermediate voltage with very high accuracy is obtained. The device for obtaining the intermediate voltage is not limited to the resistance. For example, it is clear that the same circuit can be configured using a MOS transistor. The first complementary push pull circuit is basically the same as the push pull circuit 1 of Fig. 21A. In this circuit, the resistor R5 and the N-channel MOS transistor TN10 are used in place of the voltage source VN1, and the resistor R6 and the P-channel MOS transistor TP10 are used in place of the voltage source VP1, respectively. By doing so, as described in the above-described embodiment, the voltage at the terminal 35 is always set automatically to a value as high as the gate threshold voltage of the N-channel MOS transistor at the input terminal 34. Since the resistance values of R5 and R6 are selected so that the current flowing through the resistors R5 and R6 is less than 1/2 and 1/10 of the current flowing through the resistors R3 and R4, the characteristics of the N and P channel transistors change independently. Therefore, the voltage at the terminal 34 is not affected by the change in the current value flowing from the push-pull circuit to the reference voltage generating circuit, so that it does not change. The current mirror amplification circuit 32 has the same configuration as the current mirror amplification circuit 2 of Fig. 21A. The second complementary push-pull circuit is basically the same as the push-pull circuit 3 of Fig. 21A.

In Fig. 23A, an N-channel MOS transistor TN14 is used instead of the voltage source VN2, and a P-channel MOS transistor TP14 is used instead of the voltage source VP2. By doing this, the value of the bias current flowing through the push-pull circuit does not change due to the change in the threshold voltage of the transistor. By taking this structure, a high-precision intermediate voltage is obtained at the output HVC. Further, the load capacity CL can be charged and discharged at high speed.

23B and 23C show results obtained by computer analysis of the performance comparison between the circuit method of the present invention of FIG. 23A and the conventional circuit method of FIG. In Fig. 23B, the horizontal axis represents the difference between the absolute values between the gate threshold voltages of the N and P-channel transistors, and the vertical axis represents the value of the intermediate voltage. As a result, in the conventional circuit, the threshold voltage difference is ± 0. It can be seen that when changing to 2V, the output voltage fluctuates to about ± 100 kV (about ± 13% for 0.7V). In contrast, in the circuit of the present invention, the output voltage changes to about ± 8 kV (about ± 1% for 0.7V), which is reduced by more than one digit compared to the prior art. Fig. 23C is a graph showing the rise time of the output voltage after the power is turned on with respect to the power supply voltage. Rise time is defined as the time at which the output voltage reaches 90% of its normal value after power up. The load capacitance value is assumed to be the sum of the capacity of the power source and the plate electrode for precharging the bit line of the 64M bit DRAM. As can be seen from this analysis result, the use of the intermediate voltage generating circuit is used to raise the load in a period of one digit shorter than the conventional circuit.

24A is a circuit diagram of another intermediate voltage generation circuit. In Fig. 24A, reference numeral 40 denotes a complementary push-pull voltage follower circuit, and 41 denotes a tri-state buffer. The voltage follower circuit is basically the same as the complementary push-pull circuit 1 of Fig. 21A. In Fig. 24A, the tri-state buffer operates to compensate for the drive capability of the push-pull circuit. The tri-state buffer includes load-driven P and N-channel transistors TP21 and TN21, two other differential amplifier circuits (non-crosswise) AMP1 and AMP2 for driving these transistors, and two supply voltages VOLS and VOSH to set the offset amount. do. The operation of this circuit is determined by maintaining the following three voltage conditions.

[1] V (OUT)> V (IN) + VOSH

[2] V (IN) + VOSH> V (OUT)> V (IN) -VOSL

[3] V (IN) -VOSL> V (OUT)

Under the voltage condition of [1], the voltage at the terminal 45 is high (VCC) because the voltage at the output OUT is higher than the voltage at the terminal 43. The voltage at the terminal 44 also becomes high (VCC). Therefore, the N-channel transistor TN21 is turned on and the P-channel transistor TP21 is cut off to discharge the load. Under the voltage condition of [2], since the voltage at the output OUT is lower than the voltage at the terminal 43, the voltage at the terminal 45 goes low (VSS). The voltage at terminal 44 remains high (VCC). Thus, both transistors TN21 and TP21 are shut off, resulting in a high impedance output. Under the voltage condition of [3], since the voltage at the output OUT is lower than the voltage at the terminal 42, the voltage at the terminal 44 becomes low (VSS). The voltage at terminal 45 remains low (VSS). Thus, the N-channel transistor TN21 is cut off and the P-channel transistor TP21 is conducted to charge the load. As described above, the load is discharged when the output voltage becomes larger than the predetermined range centered on the input voltage, and the load is charged when the output voltage becomes smaller than the predetermined range. If the output voltage is within a predetermined range, the load neither discharges nor charges. That is, a driving circuit having three states is realized. The operation of over-showing this circuit is shown in Fig. 24B. Hereinafter, it is assumed that the input voltage V (IN) falls at time t ₀ and rises at time t ₂ . When a falling input voltage, the output voltage at time t ₀ the voltage at the (steady-state voltage at) + VOSH 'with the same time terminal 45 to t ₁ which is the VCC by conduction of transistor TN21 load To discharge. When the input voltage rises, at time t ₂ , the voltage at terminal 44 becomes VSS until time t ₃ when the output voltage becomes equal to '(voltage in normal state) -VOSL' and the transistor TP21 conducts the load. To charge.

As described above, the combination of the tri-state buffer and the push-pull circuit causes the transistor having high driving capability to conduct when the input / output voltage difference increases to some extent. This improves the response speed of oversight. The values of the two supply voltages VOLS and VOSH to set the offset amount should be as small as possible to accelerate the focusing on the set voltage. However, in order to avoid malfunction, it is necessary to set the two power supply voltages VOLS and VOSH to values sufficiently higher than the input offset voltages of the differential amplifier circuits AMP1 and AMP2. If this circuit is composed of MOS transistors, these values are preferably 50 ns or more. The circuit configuration of the tri-state buffer is not limited to the illustrated embodiment. If the same function is realized, other methods can be used.

An embodiment of an intermediate voltage (VCC / 2) generation circuit method of a dynamic memory to which a voltage follower circuit using a three-state buffer is applied will be described with reference to FIG. 25. 25A is a diagram showing the structure of an intermediate voltage generating circuit according to the present invention. In Fig. 25A, reference numeral 50 denotes a reference voltage generator circuit, 51 denotes a voltage follower circuit described with reference to Fig. 21, and 52 denotes a three-state buffer. This circuit includes a combination of the intermediate voltage generating circuit of Fig. 23A and the tri-state buffer. This improves the restoring ability which appears when the voltage difference between input and output increases. Hereinafter, the structure and operation of the tri-state buffer will be described. The present embodiment is characterized in that the first complementary push-pull circuit is used as it is, the voltage difference is detected using the difference in the mirror ratio of the current mirror circuit, and the tri-state buffer is started. In FIG. 25A, TP36 and TP37 are P-channel MOS transistors, TN36 and TN37 are N-channel MOS transistors, INV ₁ and INV ₂ are inverters, TP38 is a P-channel MOS transistor which drives a load to the output of inverter INV ₁ , and TN38 is Each of the N-channel MOS transistors driving the load with the output of the inverter INV ₂ is shown. Each of TP32 and TP36, TP32 and TP37, TN32 and TN36, and TN32 and TN37 constitute a current mirror circuit. [1] The current flowing through transistor TN31 is represented by IC1, [2] The current flowing through transistor TP31 is represented by ID1, [3] The current flowing through transistor TN36 is represented by ID2, and [4] The current flowing through transistor TP36 is represented by IC2 In other words, the relationship between the error δV and IC1, ID1 in the output voltage is as described above,

Is approximated by

Mirror ratio of the current mirror circuit

If you set it as follows.

Hereinafter, it is assumed that IC2 = ID2 when the offset voltage Vos is applied to the output. If the current value is represented by I ₂ at that time, the offset voltage Vos is given as follows.

here, , Β is the β 1, I ₁ of the transistors constituting a complementary push-pull circuit is in the steady-state current flowing through the first complementary push-pull circuit. For example, I ₁ = 0. 2 ㎂, I ₂ = 1 ㎂, β = 1 ㎃ / V ² _, M _N1 = 1, M _P1 = 0. If it is set to 2, the value of the offset voltage Vos is -100 Hz. That is, when the output voltage falls below 100 kV under the normal state, the input voltage to inverter INV ₁ changes from low to high and the output voltage changes from high to low. Accordingly, the driving P-channel MOS transistor TP38 conducts to charge the load. At the same time, the constants of the transistors TP37 and TN37 are appropriately selected. As a result, the N-channel MOS transistor TN38 is turned on to discharge the load when there is a predetermined positive offset.

As described above, by adopting the circuit configuration described in the present embodiment, the same function as that shown in FIG. 24 is realized. In this circuit system, the offset amount is determined by the mirror ratio of the current mirror circuit. Therefore, when arranged so that the characteristic difference between a pair of transistors may be reduced, the offset amount is set with high precision. In addition, since there is no need to provide a high-precision differential amplifier circuit separately, high performance can be realized with a small power consumption and a simple configuration.

FIG. 25B is a diagram showing the results obtained by computer analysis of the performance comparison between the circuit method of the present invention and the conventional circuit method of FIG. 25B is a graph showing the rise time of the output voltage after the power is turned on with respect to the power supply voltage. Rise time is defined as the time at which the output voltage reaches 90% of the steady state value after power up. The value of the load capacity is the total capacity of the power supply and the plate electrode for precharging the bit line for the 64M bit DRAM. As can be seen from this analysis result, according to the intermediate voltage generating circuit, the rise time is shortened by about half as compared with the embodiment of Fig. 23A. The intermediate voltage generating circuit raises the load at a time shortened by about half a digit compared with the conventional circuit. As described above, the voltage follower circuit is provided to follow the input at high speed by combining the push-pull circuit and the tri-state buffer. The voltage setting accuracy is determined by the push-pull circuit. Therefore, as in the previous embodiment, the voltage difference between input and output is reduced to a very small value.

In the above embodiment, the circuit configuration for driving the large capacity load of the LSI at high speed has been described. However, if the load is to be driven at high speed, the transient current generated at the time of charge / discharge of the load is a big problem. For example, the load capacity of an intermediate voltage generation circuit of a DRAM of about 64 M bits is about 115 kW. If this current reaches 23 mA when this load is driven with current 1 V during 5 mA, this is consistent with the current value consumed by the DRAM. If the load is still driven at high speed, it is not preferable because the influence on the main circuit characteristics, for example, noise generated on the power supply line and reliability of the drive signal line are lowered. In general, an ultra high density LSI, in particular, a memory is composed of several blocks of the same kind, and a part of the block is activated during operation. In such LSI, it is useful to use the embodiments described below.

FIG. 26 is a diagram illustrating an embodiment of an intermediate voltage supply method of a dynamic memory (DRAM) to which the present invention is applied. In Fig. 26A, MB0, MB1-MBi are (i + 1) memory blocks, (60)-(62) are word line selection circuits, and (68)-(70) are intermediate voltage lead-out lines in each memory block. , (76) and (77) are intermediate voltage generation circuits, (74) and (75) are intermediate voltage generation circuits, and the signal lines for supplying the intermediate voltages HVC1 and HVC2 to each memory block, and (71) to (73) are 2 A switch provided in each block is provided to supply one of the three signal lines to the memory block. The memory block MB0 is an input / output control circuit block for amplifying a signal read from the memory cell array MA ₀ , which is a two-dimensional array of memory cells, and outputting the amplified signal to an external circuit and writing the external signal to the memory cell. MC0 and input / output circuit 67 are included.

DL0, , DLj, Is a data line for transmitting a signal to a memory cell, 63 is a plate electrode constituting the counter electrode of the storage capacitor, 64 is a precharge voltage supply line arranged to bring the data line to an intermediate voltage level when not selected, and PC Is a precharge signal line, SA _{0 to} SAj are sense amplifiers for detecting and amplifying a signal read from a memory cell, and 65 and 66 are a common pair of signals for transmitting a signal between the input / output circuit 67 and each data line. input and output lines, IO ₀ ~IOj represents an IO gate for controlling the pair of data lines connected between the pair of common output line selected by the address designation signal.

Hereinafter, it is assumed that only one MB0 of the (i + 1) memory blocks is selected and put into an operating state. At this time, one word line of MA ₀ is selected by the word line selection circuit 60 and is converted to a high level. At the same time, the switch 71 is controlled so that the intermediate voltage lead-out line 68 is connected to the intermediate voltage supply signal line 75. In the non-selection state, the lead lines 69 and 70 in the memory blocks MB1 to MBi are connected to the signal line 74 for supplying the intermediate voltage. By doing so, the loads of the i memory blocks are connected to the intermediate voltage generation circuit 76, and only the load of one memory block is connected to the intermediate voltage generation circuit 77. For example, when i = 15, the load capacity driven by the intermediate voltage generation circuit 77 is 1/5 of the load capacity driven by the intermediate voltage generation circuit 76. Thus, even if the same circuit is used for 76 and 77, the intermediate voltage of the selected block MB0 operates at a speed 15 times faster than the intermediate voltage of the unselected block. In terms of circuit performance, the response speed of an unselected memory block is independent of the memory performance. Therefore, the overall performance of the memory is improved without increasing the transient current.

Fig. 26B is a view showing the time change of the intermediate voltage when the power supply voltage is changed during the memory operation. In particular, assume that the voltage VCC falls between time t ₀ and t ₂ . Further, memory block MB0 is selected between time t ₀ and time t ₁ and after time t ₃ , and memory block MB ₁ is selected between time t ₁ and time t ₃ . Since the block MB1 is not selected between time t ₀ and time t ₁ , the intermediate voltage V 69 responds slowly. On the contrary, since the block MB0 is selected, the intermediate voltage V 68 follows at high speed. When block MB1 is selected at time t ₁ and block MB0 is switched to the non-selected state, V69 rapidly changes toward the voltage to be set. As described above, according to the present embodiment, a large capacity load such as an intermediate voltage in a dynamic memory can be driven at a substantially high speed without substantially increasing the transient current. Although the embodiment in which the present invention is applied to the intermediate voltage in the dynamic memory has been described, the present invention is not limited to this embodiment and can be variously changed within the scope not departing from the gist. The present invention is generally applicable to integrated circuits in which some are activated during operation.

As mentioned above, this invention was demonstrated in detail in each Example. However, the scope to which the present invention can be applied is not limited to these examples. For example, although the case where the LSI is composed of CMOS transistors has been mainly described so far, the present invention is, for example, an LSI using a bipolar transistor, an LSI using a junction FET, a Bi CMOS LSI in which a CMOS transistor and a bipolar transistor are combined. For example, the present invention can be applied directly to LSI in which an element is formed on a substrate made of gallium arsenide in addition to silicon.

In this embodiment, the current mirror circuit is used as the current amplifier circuit. However, other current amplifier circuits may be used. As described above, the present invention alternately arranges an input / output control circuit connecting data lines and I / O lines to the left and right sides of the memory cell array and performs read operation or write transfer impedance between the data lines and I / O lines. It has a circuit configuration that changes according to performing an operation. As a result, the memory of the present invention operates stably and at high speed even at a low power supply voltage.

The present invention can also be applied to parallel test can greatly reduce the test time.

According to the present invention, since the word transistor driving transistor operates at the low gate voltage level, it operates stably as a word driver even if the power supply voltage is reduced. The voltage conversion circuit boosts the data line voltage V _L to the voltage level V _CH higher than the data line voltage V _{L by} the threshold voltage V _T of the switching transistor of the memory cell. The word driver power supply sets the gate voltage of the rectifier transistor therein to a level higher than the drain voltage by the threshold voltage. Since the reverse flow of the charge can be prevented, the output voltage rises to 2V _L which is a theoretical value of the double voltage generating circuit. Since the oscillation circuit and the timing generation circuit using RC delay are used, respectively, the delay time of the oscillation frequency timing mutual becomes stable to the power supply voltage variation. Therefore, the voltage conversion efficiency can always be maintained at the best state. By selecting three threshold values of the transistor, stabilization, high speed, and low power consumption at low power supply voltage can be achieved. As a result, it is possible to realize a semiconductor integrated circuit which operates stably even when the power supply voltage is one electromotive force for one battery.

According to the present invention, there is provided a circuit configuration for driving large load capacity at high voltage with high voltage accuracy at high voltage density, or a circuit system for driving large load capacity at high speed without flowing a large transient current. According to the present invention, for example, when the threshold voltage difference of the transistor is 0.2V, the reference output voltage of 0.775V fluctuates by about 1%, and in the conventional circuit, the reference output voltage fluctuates by about 13% under the same conditions. That is, according to the present invention, the voltage accuracy is improved by one digit. In addition, high-speed response is obtained in which the rise time of the output voltage after power-on is improved by about one or more orders of magnitude compared with the conventional circuit.

Claims (9)

A plurality of first data line pairs arranged at odd positions, a plurality of second data line pairs arranged at even positions, and a plurality of first data lines provided at intersections of a plurality of first word lines crossing the plurality of first and second data line pairs A first memory array including memory cells and formed in a quadrangular region; A plurality of third data line pairs arranged at odd positions, a plurality of fourth data line pairs arranged at even positions, and a plurality of second provided at intersections of a plurality of second word lines crossing the plurality of third and fourth data line pairs; A second memory array including memory cells and formed in a quadrangular region; A Y decoder provided along one side of the quadrilateral area of the first memory array; A plurality of first input / outputs provided between the one side and the Y decoder in the quadrangular region of the first memory array, and connected to each of the plurality of second data line pairs through first switch means; A control circuit; The first and second sides of the first memory array facing each other and the one side in the quadrangular region of the second memory array; And a plurality of second input / output control circuits connected to each of the data line pairs through second switch means and simultaneously connected to each of the plurality of third data line pairs through third switch means. The method of claim 2, Each of the first input / output control circuit and the second input / output control circuit includes a sense amplifier having a pair of N-type MISFETs coupled to a pair of P-type MISFETs and cross-coupled to corresponding data line pairs; Device. The method of claim 3, And each of the first input / output control circuit and the second input / output control circuit further comprises a lead gate for coupling a signal read in a corresponding data line pair to a lead line, and a precharge circuit coupled to the corresponding data line pair. The method of claim 2, The first input / output control circuit is arranged at one ratio for four data lines in total of the first data line pair and the second data line pair, And the second input / output control circuit is arranged at one ratio for four data lines in total of the third data line pair and the fourth data line pair. The method according to any one of claims 2 to 5, The first data line pair and the second data line pair are disposed adjacent to each other, And the third data line pair and the fourth data line pair are disposed adjacent to each other. The method according to any one of claims 2 to 5, In the first memory array, the plurality of first data line pairs have no intersection and the plurality of second data line pairs have intersections. And the plurality of third data line pairs do not intersect and the plurality of fourth data line pairs intersect in the second memory array. The method according to any one of claims 2 to 5, And each of the plurality of first and second memory cells is a dynamic memory cell. The method of claim 2, A plurality of fifth data line pairs arranged at odd positions, a plurality of sixth data line pairs arranged at even positions, and a plurality of thirds provided at intersections of a plurality of third word lines crossing the plurality of fifth and sixth data line pairs; A third memory array including memory cells and formed in a quadrangular region; Along the other side in the quadrilateral region of the second memory array and one side in the quadrilateral region of the third memory array, each of the plurality of fourth data line pairs is provided. And a plurality of third input / output control circuits connected via a fourth switch means and connected to each of the plurality of sixth data line pairs through a fifth switch means. The method of claim 9, And each of the plurality of first, second and third memory cells is a dynamic memory cell.