KR100266425B1 - Semiconductor device operating with low supply voltage - Google Patents

Semiconductor device operating with low supply voltage

Info

Publication number
KR100266425B1
KR100266425B1 KR1020000004825A KR20000004825A KR100266425B1 KR 100266425 B1 KR100266425 B1 KR 100266425B1 KR 1020000004825 A KR1020000004825 A KR 1020000004825A KR 20000004825 A KR20000004825 A KR 20000004825A KR 100266425 B1 KR100266425 B1 KR 100266425B1
Authority
KR
South Korea
Prior art keywords
supply voltage
circuit
inverter
constitute
delay time
Prior art date
Application number
KR1020000004825A
Other languages
Korean (ko)
Inventor
Kiyoo Itoh
Hitoshi Tanaka
Yasushi Watanabe
Eiji Kume
Tatsumi Uchigiri
Masanori Isoda
Eiji Yamasaki
Yoshinobu Nakagome
Original Assignee
Hitachi Ulsi Eng Corp
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2041076A external-priority patent/JP2771880B2/en
Priority claimed from KR1019990038911A external-priority patent/KR100262437B1/en
Application filed by Hitachi Ulsi Eng Corp, Hitachi Ltd filed Critical Hitachi Ulsi Eng Corp
Priority to KR1020000004825A priority Critical patent/KR100266425B1/en
Application granted granted Critical
Publication of KR100266425B1 publication Critical patent/KR100266425B1/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits
    • G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

PURPOSE: A semiconductor device operated at a low supply voltage is provided to perform stably an operation at the low voltage without increasing the chip area by sharing an adjacent memory cell. CONSTITUTION: In the circuit, inverters(I5-I8), resistor(R2), capacitor(C2), NAND gate(NA2), and NOR gate(NO1) constitute a circuit to prevent overlapping of(PA,PA;I2,I3,R1,C1) constitute a circuit to determine a fall delay time of PA and PB; I9-I13 and NA3 constitute a circuit to generate a fall delay of PA and PB; and I14-I25, a buffer inverter. The number of buffer inverter stages is optional as long as it is odd or it is even when required. The number of inverter stages is only required to be adjusted in accordance with the magnitude of the load. The present circuit is characterized by selection of the time constant of RC which is sufficiently large compared to the delay time of the inverter in order to suppress fluctuations of the oscillating frequency due to fluctuations of the supply voltage. Therefore, the oscillating frequency is stabilized even if the ratio of VT of the transistors to the supply voltage is 1/3 or more and the delay time of the inverter greatly depends on the supply voltage.
KR1020000004825A 1989-12-08 2000-02-01 Semiconductor device operating with low supply voltage KR100266425B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020000004825A KR100266425B1 (en) 1989-12-08 2000-02-01 Semiconductor device operating with low supply voltage

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP31751889 1989-12-08
JP1223790 1990-01-22
JP2041076A JP2771880B2 (en) 1990-02-23 1990-02-23 Semiconductor device
KR1019990038911A KR100262437B1 (en) 1989-12-08 1999-09-13 Semiconductor device operating with low supply voltage
KR1020000004825A KR100266425B1 (en) 1989-12-08 2000-02-01 Semiconductor device operating with low supply voltage

Publications (1)

Publication Number Publication Date
KR100266425B1 true KR100266425B1 (en) 2000-09-15

Family

ID=27455763

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000004825A KR100266425B1 (en) 1989-12-08 2000-02-01 Semiconductor device operating with low supply voltage

Country Status (1)

Country Link
KR (1) KR100266425B1 (en)

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