JP3535213B2 - Semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board and a semiconductor device using the printed wiring board.

[0002]

[Prior art]

A. Related Art: (a-1) First Related Art: FIG. 14 is a plan view showing a configuration of a conventional printed wiring board 100. The printed wiring board 100 includes a mounting area 101 on which a semiconductor element, for example, a semiconductor integrated circuit is mounted. Mounting area 101 is 2
It has seed placement regions 102 and 103, and one semiconductor integrated circuit is placed in either of them. The placement region 102 is provided with a plurality of lands (a part for joining and electrically connecting the terminals of the component and the substrate by solder when the electrical component is mounted on the printed board) 102a and a plurality of wirings 102b. Similarly, a plurality of lands 1 are arranged in the arrangement area 103.
03a and a plurality of wirings 103b are provided.

Generally, on the same printed wiring board,
There are cases where it is desired to mount a plurality of types of semiconductor integrated circuits. In such a case, different types of semiconductor integrated circuits are selectively placed in the placement regions 102 and 103.

FIG. 15 shows a case where the semiconductor integrated circuit 104 is arranged in the arrangement region 102, and FIG. 16 shows a case where the semiconductor integrated circuit 105 is arranged in the arrangement region 103. Semiconductor integrated circuits 104, 1
05 have different pin numbers, the semiconductor integrated circuit 104 is compatible with the land 102a, and the semiconductor integrated circuit 10
5 is compatible with the land 103a.

As described above, the required semiconductor integrated circuits are properly used according to various cases and mounted in the appropriate arrangement area.

(A-2) Second Prior Art: FIG. 17 is a plan view showing a structure of a printed wiring board 110 and a semiconductor integrated circuit 106 mounted thereon. The printed wiring board 110 has a pattern 107. The semiconductor integrated circuit 106 includes a land 107 that forms a part of the pattern 107.
a, 107b, 107c, 107d, ... Connected to the pins 106a, 106b, 106c, 106d,
…have.

The pattern 107 includes lands 107a and 107.
b, 107c, 107d, ..., and lands 1071-1
082, ground patterns 10a and 10b, and terminal lands A1 to A4. The land 107a is the lands 1079 and 1080, and the land 107b is the land 107.
5, 1076 and land 107c are land 1071,1
073 and the land 107d are connected to the land A4, respectively. A predetermined power supply and signal are applied to the terminal lands A1 to A4.

If the printed wiring board 110 having such a pattern 107 is used, the same semiconductor integrated circuit 1 can be used depending on which land the chip component is connected to and arranged in.
A plurality of different functions can be realized by applying different signals and potentials to 06.

FIG. 18 shows pins 106a, 106b and 106 of the semiconductor integrated circuit 106 for realizing a certain function.
It is a top view which shows arrangement | positioning of chip components 91-93 at the time of connecting terminal lands A1-A4 to c and 106d, respectively.

The chip component 91 is arranged so as to connect between the land 1079 and the land 1081. Therefore, the pin 106a is connected to the lands 107a, 1079-10.
It is connected to the terminal land A1 via 81.

The chip component 92 is arranged so as to connect between the land 1076 and the land 1078. Therefore, the pin 106b is connected to the lands 107b, 1075, 10
It is connected to the terminal land A2 via 76 and 1078.

The chip component 93 is arranged so as to connect between the land 1073 and the land 1074. Therefore, the pin 106c is connected to the lands 107c, 1073, 10
It is connected to the terminal land A3 via 74.

The pin 106d is connected to the terminal land A4 via the land 107d.

FIG. 19 is a plan view showing the arrangement of the chip parts 91 to 93 for realizing another function.

The chip component 91 is arranged so as to connect between the land 1080 and the land 1082. Therefore, the pin 106a is connected to the lands 107a, 1080, 10
It is connected to the ground pattern 10 a via 82.

The chip component 92 is arranged so as to connect between the land 1076 and the land 1078, and the pin 106b is connected to the terminal land A2.

The chip component 93 is arranged so as to connect between the land 1073 and the land 1074, and the pin 106c is connected to the terminal land A3.

The pin 106d is connected to the terminal land A4 via the land 107d.

FIG. 20 is a plan view showing the arrangement of the chip parts 91 to 93 for realizing another function.

The chip component 91 is arranged so as to connect between the land 1080 and the land 1082, and the pin 10
6a is connected to the ground pattern 10a.

The chip component 92 is arranged so as to connect between the land 1075 and the land 1077. Therefore, the pin 106b is connected to the lands 107b, 1075, 10
It is connected to the ground pattern 10a via 77.

The chip part 93 is arranged so as to connect between the land 1073 and the land 1074, and the pin 106c is connected to the terminal land A3.

The pin 106d is connected to the terminal land A4 via the land 107d.

FIG. 21 is a plan view showing the arrangement of the chip parts 91 to 93 for realizing another function.

By disposing the chip component 93 so as to connect between the land 1071 and the land 1072,
The pin 106c is connected to the terminal land ground pattern 10b through the lands 107c and 1071 to 1073.

FIG. 22 is a perspective view showing how the semiconductor integrated circuit 106 is mounted on the printed board 107. The pin 106a of the semiconductor integrated circuit 106 is connected to the land 107a. Lands 1070a and 10 are included in the land 107a.
70b is connected. On the other hand, land 1070c, 1
070d opposes the lands 1070a and 1070b. Therefore, when it is desired to connect the pin 106a and the land 1070c, the chip component 90 is connected to the land 1070a and the land 1070c.
It is placed between the pin 106a and the land 107.
If you want to connect to
It is placed between 070b and 1070d.

As described above, according to various cases, different arrangements for mounting the chip parts are used to selectively use signals and potentials applied to the same semiconductor integrated circuit to realize a plurality of different functions.

(A-3) Third Prior Art: Switching of signals by properly arranging the mounting of chip components on the printed circuit board is often performed in ordinary board development. Especially in the memory module, it is called PD pin. These are often used in capacity switching or bit number switching.

23 to 25 are plan views showing the layout of the chip component 90 when connecting any one of the terminal lands A5, A6, A7 to the wiring line 13. As shown in FIG.
The wiring line 13 has three lands 14a, 14b, 14c.
, And the terminal lands A5, A6, A7 are connected to the lands 14d, 14e, 14f, respectively.

In FIG. 23, the terminal land A is provided on the wiring line 13.
5 shows the case where 5 are connected, and the chip component 90 is arranged between the land 14a and the land 14d. Further, FIG. 24 shows a case where the terminal land A6 is connected to the wiring line 13, and the chip component 90 is arranged between the land 14b and the land 14e. Further, FIG. 25 shows a case where the terminal land A7 is connected to the wiring line 13, and the chip component 90 is arranged between the land 14c and the land 14f.

As described above, conventionally, a plurality of sets of opposing lands are provided on the printed circuit board, and the chip component 90 is provided.
The terminal lands connected to the wiring line 13 are made different by differently arranging the arrangements.

[0032]

[Problems to be Solved by the Invention]

B. Problems: However, the following problems have occurred in the conventional technology.

(B-1) Problem in the first prior art: In order to improve the mounting density on the printed board, it is necessary to reduce the area of the mounting region 101. In other words, in a specific case, providing an area for a semiconductor integrated circuit that is not used in addition to a placement area for a semiconductor integrated circuit that is used will reduce the mounting density on the printed circuit board. .

For example, when the semiconductor integrated circuit 104 is required (FIG. 15), the arrangement region 103 is not actually used, which causes a reduction in mounting density on the printed board. Conversely, the semiconductor integrated circuit 105
16 is required (FIG. 16), placement area 1
02 is not actually used, and is a factor that reduces the mounting density on the printed circuit board.

As described above, the first conventional technique has a problem in that the printed circuit board for accommodating a plurality of types of semiconductor integrated circuits has a large redundancy with respect to the occupied area and the packaging density cannot be increased.

(B-2) Problem in the second prior art: In order to supply different signals / potentials to the same pin of the semiconductor integrated circuit by changing the arrangement of the chip parts variously, as shown in FIG. Many lands 1071-1082
Is required. Therefore, the second conventional technique has a problem that the area required for realizing a plurality of different functions in the same semiconductor integrated circuit is large and the packaging density cannot be increased.

(B-3) Problem in the third conventional technique: In the third conventional technique, there are a plurality of sets of lands necessary for supplying different signals / potentials to a wiring line. Therefore, similar to the problem in the second conventional technique, there is a problem that the area required for realizing a plurality of functions is large and the packaging density cannot be increased.

The present invention has been made to solve the above problems, and an object thereof is to provide a technique for increasing the mounting density of a printed circuit board.

[0039]

[Means for Solving the Problems] Claim 1 of the present invention
Related to the printed wiring board, an electrical element having a pair of pins arranged on the printed wiring board,
A semiconductor element disposed on the printed wiring board, wherein the printed wiring board is electrically connected to the semiconductor element and at least one of a pair of pins of the electrical element is connected to the first printed wiring board. Two or three second conductive layers are arranged around the first conductive area so that the distances from the first conductive area are substantially the same, and are supplied with different potentials or signals. of and a conductive region, before SL that by selecting one of the second conductive region connects the other one of the pair of pins, a potential or signal is supplied to the semiconductor element can be selected It is a semiconductor device.

According to claim 2 of the present invention,
A semiconductor device according to claim 1, wherein a line connecting the front SL any one said first conductive region of the second conductive region, the other one of the previous SL second conductive region first The angle formed by the line segment connecting the 1 conductive area is approximately 90 degrees or 180 degrees.
Characterized in that there.

[0041]

According to the present invention, one pin is connected to the first conductive region, and the other pin selects one of the plurality of second conductive regions arranged around the first conductive region. Connected.

[0042]

【Example】

C. Example: (c-1) First Example: The first example corresponds to the first prior art. FIG. 1 is a plan view showing a first embodiment of the present invention. The printed circuit board 1 is provided with two sets of lands. One of them is a land line 11a arranged in a line,
The land row 11a includes the same number of lands as the land row 11a.
And a land row 11b arranged in a line so as to face each other. The other side of the land group is the land row 12a arranged in a line.
And the land row 1 includes the same number of lands as the land row 12a.
It has land rows 12b arranged in a row so as to face 2a. Wiring is applied to each land so that a predetermined signal / potential is applied.

The number of lands included in the land row 11a is different from the number of lands included in the land row 12a. Here, the number of lands included in the land row 11a is the land row 12
It is smaller than the number of lands included in a. And land row 11
The land groups having a and 11b form a pair, and in order to connect a semiconductor integrated circuit having a small number of pins, the land row 12
The land groups having a and 12b are provided in pairs to connect a semiconductor integrated circuit having a large number of pins.

FIG. 2 shows a semiconductor integrated circuit 20 having a small number of pins.
FIG. 2 is a plan view showing a state in which 1 is mounted on the printed circuit board 1. The pin on the left side of the semiconductor integrated circuit 201 is the land row 11
a and the right pin are connected to the land row 11b, respectively.

FIG. 3 shows a semiconductor integrated circuit 202 having a large number of pins.
FIG. 3 is a plan view showing a state in which is mounted on the printed circuit board 1.
The pin on the left side of the semiconductor integrated circuit 202 is a land row 12a.
The right pins are connected to the land rows 12b, respectively.

As described above, the printed circuit board 1 is provided with two sets of land groups, and one of the land groups (12a) of one of the land groups has a pair of land rows (11a, 11a, 11b), the required area is smaller than that of the first prior art. Moreover, two different peninsula-pair integrated circuits can be mounted.

(C-2) Second embodiment: The second embodiment is the second
It corresponds to the conventional technology of. FIG. 4 is a perspective view showing the basic concept of the second embodiment of the present invention. The printed circuit board 2 is similar to the printed circuit board 1 of the first embodiment in that it is provided with two sets of lands. However, the number of lands included in each land row is the same. Therefore, by moving the same semiconductor integrated circuit 203 in parallel and mounting it, different potentials and signals can be applied to the same semiconductor integrated circuit 203.

That is, the pin 203 of the semiconductor integrated circuit 203.
a so that a is connected to the land 2a.
03 can be mounted, or the semiconductor integrated circuit 203 can be mounted so that the pin 203a is connected to the land 2B. Therefore, the semiconductor integrated circuit 203 can exert different functions by applying different potentials and signals to the lands 2a and 2b. Moreover, there is no need to provide lands for connection by chip parts.

FIG. 5 is a plan view showing a second embodiment according to the present invention. The printed circuit board 20 includes four land groups. The first land group has a land row 21a and a land row 21b arranged in a row so as to face the land row 21a. The second land group has a land row 22a and a land row 22b arranged in a row so as to face the land row 22a. Third
The land group includes a land row 23a and a land row 23b that faces the land row 23a and is arranged in a row. The fourth land group has a land row 24a and a land row 24b arranged in a row so as to face the land row 24a. Each land row 21a, 2
1b, 22a, 22b, 23a, 23b, 24a, 24
All b have the same number of lands.

The land rows 22a are arranged in order from the bottom.
1a, 222a, 223a, 224a are included. Similarly, the land row 22b includes the lands 221 in order from the bottom.
b, 222b, 223b, 224b. Similarly, the land row 22c includes the lands 221 in order from the bottom.
c, 222c, 223c, 224c. Similarly, the land row 22d includes the lands 221 in order from the bottom.
It includes d, 222d, 223d and 224d.

The printed circuit board 20 further includes the ground pattern 10
And the ground pattern 10 has lands 221a, 2
21b, 221c, 222a, 222b, 223a are connected.

The printed circuit board 20 further includes terminal lands A1, A2, A3, A4. The terminal land A1 is a land 221d, the terminal land A2 is a land 222c, 222d, and the terminal land A3 is a land 22.
3b, 223c, 223d and the terminal land A4 are connected to the lands 224a, 224b, 224c, 224d, respectively.

FIGS. 6 to 9 are plan views showing a state in which the same semiconductor integrated circuit 204 is mounted on the printed circuit board 20 thus configured and different potentials and signals are applied. FIG. 6 is the second prior art FIG. 17, and FIG. 7 is the FIG.
8 corresponds to FIG. 19, and FIG. 9 corresponds to FIG. 20, respectively. That is, the terminal lands connected to the lower four pins of the right side pin of the semiconductor integrated circuit 204 are given the same in the two corresponding figures as described above.

Referring to FIG. 6, the land 221
The terminal lands A1, A2, A3, A4 are respectively connected to the semiconductor integrated circuit 204 via d, 222d, 223d, 224d.

Referring to FIG. 7, the land 221
A ground pattern 10 (hidden under the semiconductor integrated circuit 204 and not shown) and terminal lands A2, A3, A4 via c, 222c, 223c, 224c, respectively.
Are respectively connected to the semiconductor integrated circuit 204.

Referring to FIG. 8, the land 221
b, 222b, the ground pattern 10 is connected to the land 22
The terminal lands A3 and A4 are connected to the semiconductor integrated circuit 204 via 3b and 224b, respectively.

Referring to FIG. 9, the land 221
the ground pattern 10 via a, 222a, 223a,
The terminal lands A4 are connected to the semiconductor integrated circuit 204 via the lands 224a.

Therefore, by moving the same semiconductor integrated circuit 204 in parallel and mounting it on the printed circuit board 20, different potentials and signals can be applied to the same semiconductor integrated circuit 204. Moreover, a large area is not required as in the first embodiment.

(C-3) Third embodiment: the third embodiment is the third
It corresponds to the conventional technology of. FIG. 10 is a perspective view showing the basic concept of the third embodiment of the present invention. FIG. 10 corresponds to FIG. 22 of the third conventional technique.

The printed circuit board 3 has a semiconductor integrated circuit 205.
Is placed. The pin 205a of the semiconductor integrated circuit 205 is connected to the land 3a. Land 3a is
It is connected to the land 3b for switching the function.
The printed circuit board 3 is similar to the printed circuit board 107 shown in the third conventional technique in that a land 301b that faces the land 3b is provided.

However, in the third embodiment, the lands 1070b, 1070d and the land 1070 which face each other and form a pair.
A and 1070c do not always have a plurality of pairs of lands to which chip components arranged for switching are connected. The printed circuit board 3 includes a land 301a, but the land 3b also faces the land 301a. That is, the lands 301a and 301b face the same land 3b, in other words, the lands 301a and 301b are provided around the land 3b. Therefore, different potentials are applied to the lands 301a and 301b.
Even when a signal is applied and a different potential / signal is applied to the pin 205a of the semiconductor integrated circuit 205, one end of the chip component 90 is always connected to the land 3b. Specifically, pin 2
When connecting 05a and the land 301b, the chip component 90 is arranged between the land 3b and the land 301b. When the pin 205a and the land 301a are connected, the chip component 90 includes the land 3b and the land 301a.
It is arranged between a and.

As described above, the number of required lands of the printed circuit board 3 is reduced as compared with the conventional printed circuit board 107 shown in FIG. Therefore, the mounting density of the printed circuit board can be improved.

11 to 13 show a third embodiment of the present invention.
FIG. 26 is a plan view showing an embodiment and corresponds to FIGS. 23 to 25 of the third conventional technique. The printed circuit board 30 includes a wiring line 31 and terminal lands A5, A6 and A7.
Further, the wiring line 31, the terminal lands A5, A6, A7
31a, 32a, 32 connected to each of
b, 32c.

In FIG. 11, the terminal land A is provided on the wiring line 31.
The layout of the chip component 90 when connecting 5 is shown. The chip component 90 is arranged between the land 31a and the land 32a. FIG. 12 shows the arrangement of the chip component 90 when the terminal land A6 is connected to the wiring line 31. The chip component 90 includes the land 31a and the land 32.
It is arranged between b and. FIG. 13 shows the layout of the chip component 90 when the terminal land A7 is connected to the wiring line 31. The chip component 90 is arranged between the land 31a and the land 32c.

As described above, the number of lands required for selectively connecting the three types of terminal lands A5, A6, A7 to the wiring line 31 is four. This is reduced compared to the number of lands of 6 shown in FIGS. 22 to 25. Therefore, according to the third embodiment, the mounting density of the printed circuit board can be increased because the number of necessary lands is reduced.

The land 31a in the third embodiment is provided with the first conductive region 32a, 32b, 3 in the first conductive region.
Reference numerals 2c correspond to the second conductive regions described in claim 1, respectively.

According to the semiconductor device of the first aspect, it is possible to reduce the number of required conductive regions, and consequently to increase the mounting density on the printed wiring board. According to the semiconductor device of the second aspect, when the one of the pair of pins of the electric element is selectively connected to any one of the plurality of second conductive regions, the arrangement of the electric element is 9
It can be changed by rotating it by 0 degree or 180 degrees , and thus the arrangement of the electric elements can be easily set.

[Brief description of drawings]

FIG. 1 is a plan view showing a first embodiment of the present invention.

FIG. 2 is a plan view showing a first embodiment of the present invention.

FIG. 3 is a plan view showing a first embodiment of the present invention.

FIG. 4 is a perspective view showing the basic concept of the second embodiment of the present invention.

FIG. 5 is a plan view showing a second embodiment of the present invention.

FIG. 6 is a plan view showing a second embodiment of the present invention.

FIG. 7 is a plan view showing a second embodiment of the present invention.

FIG. 8 is a plan view showing a second embodiment of the present invention.

FIG. 9 is a plan view showing a second embodiment of the present invention.

FIG. 10 is a perspective view showing the basic idea of the third embodiment of the present invention.

FIG. 11 is a plan view showing a third embodiment of the present invention.

FIG. 12 is a plan view showing a third embodiment of the present invention.

FIG. 13 is a plan view showing a third embodiment of the present invention.

FIG. 14 is a plan view showing a first conventional technique.

FIG. 15 is a plan view showing a first conventional technique.

FIG. 16 is a plan view showing a first conventional technique.

FIG. 17 is a plan view showing a second conventional technique.

FIG. 18 is a plan view showing a second conventional technique.

FIG. 19 is a plan view showing a second conventional technique.

FIG. 20 is a plan view showing a second conventional technique.

FIG. 21 is a plan view showing a second conventional technique.

FIG. 22 is a perspective view showing a third conventional technique.

FIG. 23 is a plan view showing a third conventional technique.

FIG. 24 is a plan view showing a third conventional technique.

FIG. 25 is a plan view showing a third conventional technique.

[Explanation of symbols]

1, 20 and 30 printed circuit boards, 201 to 205 semiconductor integrated circuits, 11a, 11b, 12a, 12b and 21a
-21d, 22a-22d Land row, 31a, 32a
~ 32c, 221a to 224a, 221b to 224b,
221c to 224c and 221d to 224d lands.

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 23/12 H05K 3/34 H05K 1/18

Claims (2)

(57) [Claims] 1. A printed wiring board, an electric element having a pair of pins arranged on the printed wiring board, and a semiconductor element arranged on the printed wiring board, wherein the printed wiring board is the semiconductor. A first conductive region electrically connected to the element and to which either one of a pair of pins of the electrical element is connected, and a distance from the first conductive region around the first conductive region selected but is arranged so as to be respectively substantially the same, and a 2 different potential or signal is supplied, or 3, of the second conductive regions, respectively, any one of the previous SL second conductive region Then, a semiconductor device capable of selecting a potential or a signal applied to the semiconductor element by being connected to the other one of the pair of pins. 2. A line segment connecting the front SL any one said first conductive region of the second conductive region, a front Symbol One and the first conductive region other of the second conductive region The semiconductor device according to claim 1, wherein an angle formed by the connecting line segment is approximately 90 degrees or 180 degrees .