WO1999040762A1 - Printed board - Google Patents

Printed board Download PDF

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Publication number
WO1999040762A1
WO1999040762A1 PCT/JP1998/000486 JP9800486W WO9940762A1 WO 1999040762 A1 WO1999040762 A1 WO 1999040762A1 JP 9800486 W JP9800486 W JP 9800486W WO 9940762 A1 WO9940762 A1 WO 9940762A1
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WO
WIPO (PCT)
Prior art keywords
model
circuit board
printed circuit
semiconductor element
semiconductor
Prior art date
Application number
PCT/JP1998/000486
Other languages
French (fr)
Japanese (ja)
Inventor
Shigeo Shikatani
Original Assignee
Mitsubishi Denki Kabushiki Kaisha
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Denki Kabushiki Kaisha filed Critical Mitsubishi Denki Kabushiki Kaisha
Priority to PCT/JP1998/000486 priority Critical patent/WO1999040762A1/en
Publication of WO1999040762A1 publication Critical patent/WO1999040762A1/en

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0295—Programmable, customizable or modifiable circuits adapted for choosing between different types or different locations of mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
    • H05K2201/09954—More mounting possibilities, e.g. on same place of PCB, or by using different sets of edge pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3421—Leaded components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a print substrate on which an IC such as a memory is mounted.
  • FIG. 1 is a diagram showing a component arrangement of a printed circuit board provided with a conventional IC such as a memory, for example, installed in a car navigation device.
  • reference numerals 1, 2, and 3 denote ICs such as memories
  • FIG. 1 (a) shows a printer sharing a model A using IC 1 and IC 2 with a model B using IC 3
  • FIG. 1 (b) shows a print board 5 dedicated to model A using IC 1 and IC 2 and a print board 6 dedicated to model B using IC 3 .
  • Fig. 2 is a circuit diagram showing the wiring for the CPU to access the data in this memory when the IC is a memory. It corresponds to the printed circuit board 4 which is shared with the user.
  • IC 1, IC 2, and IC 3 are memories of the same type and of the same capacity, and have the same bin configuration.
  • the address signal lines AO, A 1, A 2, A 3, and A 4 from the CPU input the address of IC 3 respectively.
  • address signal lines A1, A2, A3, and A4 from the CPU are connected to the address input terminals AO and A of IC1 and 2, respectively.
  • a 2 Connected to A 3 and the data output terminals DO, D l, D 2, D 3, D 7 of IC 1 are connected to the data signal lines DO, D l, D 2, Connected to D3 and D7, the data output terminals of IC2 are DO, D1, D2, D3 and D7, respectively, and are connected to the CPU.
  • model A since two ICs such as a memory are used as one set, the least significant digit of AO is unnecessary, and address signal lines A l, A 2, A 3, and A4 is connected to the address input terminals AO, Al, A2, A3 of ICs 1 and 2, respectively.
  • the conventional method has a problem that the number of types of substrates is increased or the size of the substrate is increased by sharing the substrate.
  • the present invention has been made to solve the above-described problems.
  • the purpose of the present invention is to obtain a printed circuit board on which ICs such as multiple types of memories can be mounted in various arrangements without increasing the size of the circuit board by devising the arrangement of the ICs and the pattern arrangement. Disclosure of the invention
  • the printed circuit board according to the present invention is a printed circuit board on which a first semiconductor element used for a first model and a second semiconductor element used for a second model are mounted.
  • the element and the second semiconductor element are arranged so that their mounting positions overlap each other, and the first semiconductor element is mounted, the element is used for the first model, and the second semiconductor element is If implemented, it is used for the second model above.
  • the print substrate according to the present invention is characterized in that the first semiconductor element and the second semiconductor element are semiconductor memories.
  • the printed board according to the present invention is characterized in that the first and third semiconductor elements used for the first model and the second semiconductor element used for the second model are mounted on the printed circuit board.
  • the mounting position of the second semiconductor element is arranged in the mounting position of the third semiconductor element, and the first and third semiconductor elements are mounted, so that the mounting position is used for the first model, 2 is used in the second model by mounting the semiconductor element.
  • the print substrate according to the present invention is characterized in that the first semiconductor element, the second semiconductor element, and the third semiconductor element are semiconductor memories.
  • FIG. 1 is a diagram showing a component arrangement of a conventional printed circuit board.
  • FIG. 2 is a circuit diagram for accessing data in an IC such as a memory.
  • FIG. 3 is a diagram showing an arrangement of components on a printed circuit board according to Embodiment 1 of the present invention.
  • FIG. 4 is a diagram showing a pattern arrangement of a print substrate according to Embodiment 1 of the present invention.
  • FIG. 5 is a diagram showing a component arrangement of a printed circuit board according to Embodiment 2 of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 3 is a diagram showing an arrangement of components on a printed circuit board according to Embodiment 1 of the present invention.
  • 1 and 2 are ICs for model A
  • 3 is I for model B
  • C and 7 are print boards that are common to Model A and Model B
  • IC 3 for Model B is used for Model A without increasing the size of the board as in the past. It is arranged so as to overlap a part of IC 1.
  • FIG. 4 is a diagram showing a pattern arrangement of a print substrate according to Embodiment 1 of the present invention.
  • 1 is an IC for model A
  • 3 is an IC for model B
  • 100, 101, 102, and 103 are address input terminals AO
  • Lands connecting A 1, A 2, A 3, 1 1 0, 1 1 1, 1 1 2, 1 1 3, ... 1 1 7 are the data output terminals of IC 1
  • Lands connecting 0, D 1, D 2, D 3, 7, 3 0 0, 3 0 1, 3 0 2, 3 0 3, 3 04 are address input terminals A 0, A of IC 3, respectively.
  • the lands 1 1 0, 1 1 1, 1 1 2, 1 1 3, ... 1 1 7 of IC 1 correspond to the lands 3 1 0, 3 1 1, 3 1 2, 3 of IC 3. 1 3, ... 3 1 7 are connected.
  • the land 300 of IC 3 is not connected to the land of IC 1, but the pattern is drawn independently, and the land 100 0, 100 1, 102, and 103 of IC 1 are not connected.
  • IC 3 lands 310,302,303,304 are connected to each other. This is the circuit diagram of Figure 2, where the address input terminal A 0 of IC 3 is not connected to the address input terminal of IC 1, , A 1, A 2, A 3 are connected to the address input terminals A 1, A 2, A 3, A 4 of IC 3 respectively.
  • the data output terminals of IC 1 used in model A and IC 3 used in model B are connected to the same signal line to the CPU, and the address input terminal is
  • the component arrangement of IC 1 and IC 3 can be slightly displaced so that the common terminal approaches.
  • a land and a pattern connected to the land can be formed.
  • the type of the memory and the like used in the model A and the model B and the contents of the circuit diagram are taken into consideration, and The size of the printed circuit board can be increased or a dedicated printed circuit board can be manufactured by superposing the parts of the IC used in A and model B so that the common terminals are close to each other. There is no need to perform this, and an effect is obtained that a shared print substrate having substantially the same size as the dedicated print substrate can be realized.
  • Embodiment 2 Embodiment 2.
  • FIG. 5 is a diagram showing a component arrangement of a printed circuit board according to the second embodiment.
  • 8 and 9 are ICs for model A
  • 10 is an IC for model B
  • 11 is a printed circuit board shared by model A and model B.
  • I C8, I C9, and I C10 are ICs of memories and the like of different types, respectively. In this way, even in the case of ICs of different types of memories and the like, the components may be superimposed and arranged so that a common terminal approaches, taking into account the type of IC and the contents of the circuit diagram.
  • the area occupied by IC 8 and IC 9 is By arranging the IC 10 board and wiring it, it is possible to create a model A board and a model B board with the same size and without changing other wiring.
  • the size of the printed circuit board can be increased even if the type of IC such as a memory to be mounted is different. Therefore, there is no need to manufacture a dedicated print substrate for each, and an effect is obtained that a shared print substrate having the same size as the dedicated print substrate can be realized.
  • the shared board for the models A and B is created as in the second embodiment, the shared board is used. Can be applied to the existing board assembly line for model A, and the trouble of changing the board assembly line can be saved.
  • the printed circuit board according to the present invention is suitable for a substrate that can be shared without increasing the size, even between different models.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

A printed board on which the mounting positions of ICs (1 and 3) are arranged in an overlapping state, so that the common terminals of the IC (1) used for an A type of machine and the IC (3) used for another B type of machine can be disposed closer to each other.

Description

明 細 書 プリ ン ト基板 技術分野  Description Printed circuit board technical field
この発明は、 メモリ等の I Cを搭載するプリ ン ト基板に関するもので ある。 背景技術  The present invention relates to a print substrate on which an IC such as a memory is mounted. Background art
第 1図は、 従来のメモリ等の I Cを搭載する、 例えば、 自動車用のナ ピゲーシヨン装置内に設置されるプリ ン ト基板の部品配置を示す図であ る。 図において、 1 , 2， 3はメモリ等の I Cであり、 第 1図 （ a) は 、 I C 1及び I C 2を使用する機種 A用と I C 3を使用する機種 B用と を共用するプリ ン ト基板 4を示し、 第 1図 （b) は、 I C 1及び I C 2 を使用する機種 A専用のプリ ン ト基板 5と、 I C 3を使用する機種 B専 用のプリ ン ト基板 6を示す。 第 1図 （a) の共用のプリ ン ト基板 4は、 機種 Aに用いた場合には 1 ( 1及び 1 。 2のみを使用し、 機種 Bに用い た場合には I C 3のみを使用するもので、 I C 1 , I C 2 , I C 3の全 てが搭載されることはない。  FIG. 1 is a diagram showing a component arrangement of a printed circuit board provided with a conventional IC such as a memory, for example, installed in a car navigation device. In the figure, reference numerals 1, 2, and 3 denote ICs such as memories, and FIG. 1 (a) shows a printer sharing a model A using IC 1 and IC 2 with a model B using IC 3; FIG. 1 (b) shows a print board 5 dedicated to model A using IC 1 and IC 2 and a print board 6 dedicated to model B using IC 3 . For the common printed circuit board 4 in Fig. 1 (a), use 1 (1 and 1.2 only) when used for model A, and use only IC 3 when used for model B However, all of IC1, IC2 and IC3 are not mounted.
第 2図は I Cがメモリの場合に、 このメモリ内のデ一夕を C PUがァ クセスするための配線を示した回路図であ り、 第 1図 （ a) の機種 A用 と機種 B用とを共用するプリ ン ト基板 4に対応するものである。 第 2図 において、 I C 1 , I C 2 , I C 3は同一品種の同一容量のメモリであ り、 そのビン構成が同一の場合について説明する。  Fig. 2 is a circuit diagram showing the wiring for the CPU to access the data in this memory when the IC is a memory. It corresponds to the printed circuit board 4 which is shared with the user. In FIG. 2, a case will be described in which IC 1, IC 2, and IC 3 are memories of the same type and of the same capacity, and have the same bin configuration.
機種 B用として使用する I C 3については、 C P Uからのア ドレス信 号線 A O, A 1 , A 2 , A 3， A 4が、 それぞれ I C 3のア ドレス入力 端子 A O , A 1 , A 2， A 3, A 4に接続され、 I C 3のデータ出力端 子 D 0， D 1 , D 2 , D 3 , ·'·ϋ 7は、 それそれ C P Uへのデ一夕信号 線 D O, D l , D 2 , D 3 , D 7に接続され、 8ビッ トのデ一夕とし て出力している。 For the IC 3 used for model B, the address signal lines AO, A 1, A 2, A 3, and A 4 from the CPU input the address of IC 3 respectively. Connected to terminals AO, A1, A2, A3, A4, and data output terminals D0, D1, D2, D3 It is connected to the overnight signal lines DO, Dl, D2, D3, and D7, and outputs as 8-bit data.
一方、 機種 A用として使用する I C 1及び I C 2については、 C PU からのアドレス信号線 A l， A 2， A 3 , A 4が、 それそれ I C 1及び 2のア ドレス入力端子 A O, A 1 , A 2 A 3に接続され、 I C 1のデ —夕出力端子 D O， D l , D 2， D 3， D 7は、 それそれ C PUへの データ信号線 D O, D l , D 2 , D 3 , D 7に接続され、 I C 2のデ —夕出力端子 D O , D 1 , D 2 , D 3， D 7は、 それそれ C P Uへの デ一夕信号線 D 8, D 9 , D 1 0， D l ， … D 1 5に接続され、 1 6 ビッ トのデータとして出力している。 このように機種 Aでは、 メモリ等 の I C 2個を一組として使用しているので、 A Oの最下位の桁は不要と なり、 C P Uからのア ドレス信号線 A l , A 2 , A 3 , A 4が、 それそ れ I C 1及び 2のアドレス入力端子 A O , A l、 A 2、 A 3に接続され ている。  On the other hand, for IC 1 and IC 2 used for model A, address signal lines A1, A2, A3, and A4 from the CPU are connected to the address input terminals AO and A of IC1 and 2, respectively. 1, A 2 Connected to A 3, and the data output terminals DO, D l, D 2, D 3, D 7 of IC 1 are connected to the data signal lines DO, D l, D 2, Connected to D3 and D7, the data output terminals of IC2 are DO, D1, D2, D3 and D7, respectively, and are connected to the CPU. 0, Dl, ... Connected to D15 and output as 16-bit data. As described above, in model A, since two ICs such as a memory are used as one set, the least significant digit of AO is unnecessary, and address signal lines A l, A 2, A 3, and A4 is connected to the address input terminals AO, Al, A2, A3 of ICs 1 and 2, respectively.
このように、 従来、 複数の機種に対応するような回路構成のプリ ン ト 基板を製作する場合、 第 1図 （ a) の共用のプリ ン ト基板のように、 機 種 A用と機種 B用の I C 1， I C 2 , I C 3を個別に配置できるように プリン ト基板の面積を拡大するか、 第 1図 （b) のように、 機種 A用と 機種 B用のそれそれ専用のプリン ト基板を製作する必要があった。  As described above, conventionally, when manufacturing a printed circuit board having a circuit configuration corresponding to a plurality of models, as shown in the shared printed circuit board of FIG. Increase the area of the printed circuit board so that IC1, IC2, and IC3 can be individually arranged. Alternatively, as shown in Fig. 1 (b), prints for model A and model B It was necessary to manufacture a substrate.
このため従来の方法では、 基板の品種が増えるか、 基板の共用化によ り基板サイズの拡大を引き起こすという課題があつた。  For this reason, the conventional method has a problem that the number of types of substrates is increased or the size of the substrate is increased by sharing the substrate.
特に、 メモリの場合には、 メモリ数の増減により、 アドレス指定を変 える必要があり、 配線も大幅に変える必要があった。  In particular, in the case of memories, addressing had to be changed depending on the number of memories, and wiring had to be changed significantly.
この発明は上記のような課題を解決するためになされたもので、 基板 内の I Cの配置やパターンの配置を工夫することで、 基板サイズを拡大 することなく、 複数のタイプのメモリ等の I Cを種々の配置で搭載でき るプリン ト基板を得ることを目的とする。 発明の開示 SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems. The purpose of the present invention is to obtain a printed circuit board on which ICs such as multiple types of memories can be mounted in various arrangements without increasing the size of the circuit board by devising the arrangement of the ICs and the pattern arrangement. Disclosure of the invention
この発明に係るプリ ン ト基板は、 第 1の機種に使用する第 1 の半導体 素子と第 2の機種に使用する第 2の半導体素子とが実装されるものにお いて、 上記第 1の半導体素子と上記第 2の半導体素子の実装位置が重な るように配置され、 上記第 1の半導体素子が実装された場合には、 上記 第 1 の機種に使用され、 上記第 2の半導体素子が実装された場合には、 上記第 2の機種に使用されるものである。  The printed circuit board according to the present invention is a printed circuit board on which a first semiconductor element used for a first model and a second semiconductor element used for a second model are mounted. When the element and the second semiconductor element are arranged so that their mounting positions overlap each other, and the first semiconductor element is mounted, the element is used for the first model, and the second semiconductor element is If implemented, it is used for the second model above.
このことによって、 プリン ト基板のサイズを拡大したり、 それぞれ専 用のプリ ン ト基板を製作する必要がなく、 共用のプリン ト基板を実現で きるという効果を奏する。  As a result, it is not necessary to increase the size of the printed circuit board or to manufacture a dedicated printed circuit board for each of them, so that a shared printed circuit board can be realized.
この発明に係るプリ ン ト基板は、 第 1の半導体素子と第 2の半導体素 子が、 半導体メモリであることを特徴とするものである。  The print substrate according to the present invention is characterized in that the first semiconductor element and the second semiconductor element are semiconductor memories.
このことによって、 プリ ン ト基板のサイズを拡大したり、 それそれ専 用のプリ ン ト基板を製作する必要がなく、 半導体メモリを実装する共用 のプリ ン ト基板を実現できるという効果を奏する。  As a result, there is no need to increase the size of the printed circuit board or to manufacture a dedicated printed circuit board for each, and it is possible to realize a shared printed circuit board on which the semiconductor memory is mounted.
この発明に係るプリ ン ト基板は、 第 1の機種に使用する第 1及び第 3 の半導体素子と第 2の機種に使用する第 2の半導体素子とが実装される ものにおいて、 上記第 1及び第 3の半導体素子の実装位置内に上記第 2 の半導体素子の実装位置が配置され、 上記第 1及び第 3の半導体素子が 実装されることにより、 上記第 1の機種に使用され、 上記第 2の半導体 素子が実装されることにより、 上記第 2の機種に使用されるものである このことによって、 プリ ン ト基板のサイズを拡大した り、 それそれ専 用のプリ ン ト基板を製作する必要がなく、 共用のプリ ン ト基板を実現で きるという効果を奏する。 The printed board according to the present invention is characterized in that the first and third semiconductor elements used for the first model and the second semiconductor element used for the second model are mounted on the printed circuit board. The mounting position of the second semiconductor element is arranged in the mounting position of the third semiconductor element, and the first and third semiconductor elements are mounted, so that the mounting position is used for the first model, 2 is used in the second model by mounting the semiconductor element As a result, there is no need to increase the size of the printed circuit board or to manufacture a dedicated printed circuit board for each of them, and it is possible to realize a shared printed circuit board.
この発明に係るプリ ン ト基板は、 第 1の半導体素子， 第 2の半導体素 子及び第 3の半導体素子が、 半導体メモリであることを特徴とするもの である。  The print substrate according to the present invention is characterized in that the first semiconductor element, the second semiconductor element, and the third semiconductor element are semiconductor memories.
このことによって、 プリ ン ト基板のサイズを拡大した り、 それそれ専 用のプリ ン ト基板を製作する必要がなく、 半導体メモリ を実装する共用 のプリ ン ト基板を実現できるという効果を奏する。 図面の簡単な説明  As a result, there is no need to increase the size of the printed circuit board or to manufacture a dedicated printed circuit board for each, and it is possible to realize a shared printed circuit board on which the semiconductor memory is mounted. BRIEF DESCRIPTION OF THE FIGURES
第 1図は従来のプリ ン ト基板の部品配置を示す図である。  FIG. 1 is a diagram showing a component arrangement of a conventional printed circuit board.
第 2図はメモリ等の I C内のデータをアクセスする回路図である。 第 3図はこの発明の実施の形態 1 によるプリ ン ト基板の部品配置を示 す図である。  FIG. 2 is a circuit diagram for accessing data in an IC such as a memory. FIG. 3 is a diagram showing an arrangement of components on a printed circuit board according to Embodiment 1 of the present invention.
第 4図はこの発明の実施の形態 1 によるプリ ン ト基板のパターン配置 を示す図である。  FIG. 4 is a diagram showing a pattern arrangement of a print substrate according to Embodiment 1 of the present invention.
第 5図はこの発明の実施の形態 2 によるプリ ン ト基板の部品配置を示 す図である。 発明を実施するための最良の形態  FIG. 5 is a diagram showing a component arrangement of a printed circuit board according to Embodiment 2 of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 この発明をよ り詳細に説明するために、 この発明を実施するた めの最良の形態について、 添付の図面に従って説明する。  Hereinafter, in order to explain this invention in greater detail, the preferred embodiments of the present invention will be described with reference to the accompanying drawings.
実施の形態 1 . Embodiment 1
第 3図はこの発明の実施の形態 1 によるプリ ン ト基板の部品配置を示 す図である。 図において、 1 , 2は機種 A用の I C、 3は機種 B用の I C、 7は機種 A及び機種 B共用のプリン ト基板であるが、 この実施の形 態 1では、 従来のように基板のサイズを拡大することなく、 機種 B用の I C 3は機種 A用の I C 1の一部に重なるように配置されている。 この ように配置することにより、 基板上の同じ領域を、 機種 Aでは I C 1及 び I C 2を使用し、 機種 Bでは I C 3を使用するので基板を有効利用す ることができる。 FIG. 3 is a diagram showing an arrangement of components on a printed circuit board according to Embodiment 1 of the present invention. In the figure, 1 and 2 are ICs for model A, and 3 is I for model B C and 7 are print boards that are common to Model A and Model B, but in Embodiment 1, IC 3 for Model B is used for Model A without increasing the size of the board as in the past. It is arranged so as to overlap a part of IC 1. By arranging in this way, the same area on the board is used for model A because IC 1 and IC 2 are used, and for model B, IC 3 is used, so that the board can be used effectively.
第 4図はこの発明の実施の形態 1によるプリ ン ト基板のパターン配置 を示す図である。 図において、 1は機種 A用の I C、 3は機種 B用の I Cであり、 1 0 0, 1 0 1， 1 0 2 , 1 0 3は、 それそれ I C 1のア ド レス入力端子 A O， A 1 , A 2 , A 3を接続するラン ド、 1 1 0, 1 1 1 , 1 1 2 , 1 1 3 , … 1 1 7は、 それそれ I C 1のデ一夕出力端子 D FIG. 4 is a diagram showing a pattern arrangement of a print substrate according to Embodiment 1 of the present invention. In the figure, 1 is an IC for model A, 3 is an IC for model B, and 100, 101, 102, and 103 are address input terminals AO, Lands connecting A 1, A 2, A 3, 1 1 0, 1 1 1, 1 1 2, 1 1 3, ... 1 1 7 are the data output terminals of IC 1
0, D 1 , D 2 , D 3, 7を接続するラン ド、 3 0 0， 3 0 1 , 3 0 2， 3 0 3, 3 04は、 それそれ I C 3のアドレス入力端子 A 0 , ALands connecting 0, D 1, D 2, D 3, 7, 3 0 0, 3 0 1, 3 0 2, 3 0 3, 3 04 are address input terminals A 0, A of IC 3, respectively.
1 , A 2 , A 3 , Α 4を接続するラン ド、 3 1 0， 3 1 1， 3 1 2, 3 1 3， ·'· 3 1 7は、 それそれ I C 3のデータ出力端子 D O， D 1 , D 2 ， D 3， "'D 7を接続するラン ドである。 1, A 2, A 3, Α 4, and 3 10, 3 11, 3 1 2, 3 13, · '· 3 17 are the data output terminals DO, This is the land connecting D1, D2, D3 and "'D7.
第 4図において、 I C 1のラン ド 1 1 0, 1 1 1， 1 1 2， 1 1 3， … 1 1 7は、 I C 3のラン ド 3 1 0 , 3 1 1， 3 1 2 , 3 1 3， … 3 1 7と接続されている。 これは第 2図の回路図からも明らかなように、 I C 1のデ一夕出力端子 D O， D 1 , D 2 , D 3 , ·'·Ε) 7と、 I C 3のデ 一夕出力端子 D O , D l， D 2， D 3 , … D 7とが接続されているため である。 また I C 3のラン ド 3 0 0は I C 1のラン ドとは接続されずに 、 単独にパターンが引き出され、 I C 1のラン ド 1 0 0 , 1 0 1， 1 0 2 , 1 0 3は、 I C 3のラン ド 3 0 1， 3 0 2 , 3 0 3， 3 04とそれ それ接続されている。 これは第 2図の回路図で、 I C 3のアドレス入力 端子 A 0は、 I C 1のア ドレス入力端子とは接続されず、 I C 1の A 0 ， A 1 , A 2 , A 3が、 それそれ I C 3のア ドレス入力端子 A l , A 2 , A 3， A 4と接続されているためである。 In FIG. 4, the lands 1 1 0, 1 1 1, 1 1 2, 1 1 3, ... 1 1 7 of IC 1 correspond to the lands 3 1 0, 3 1 1, 3 1 2, 3 of IC 3. 1 3, ... 3 1 7 are connected. As can be seen from the circuit diagram of Fig. 2, the data output terminals DO, D1, D2, D3, This is because DO, Dl, D2, D3, ... D7 are connected. In addition, the land 300 of IC 3 is not connected to the land of IC 1, but the pattern is drawn independently, and the land 100 0, 100 1, 102, and 103 of IC 1 are not connected. , IC 3 lands 310,302,303,304 are connected to each other. This is the circuit diagram of Figure 2, where the address input terminal A 0 of IC 3 is not connected to the address input terminal of IC 1, , A 1, A 2, A 3 are connected to the address input terminals A 1, A 2, A 3, A 4 of IC 3 respectively.
このように、 機種 Aで使用する I C 1 と機種 Bで使用する I C 3のデ 一夕出力端子は、 C P Uへの同一信号線に接続されていることを利用し 、 またア ドレス入力端子は、 C P Uへのア ドレス信号線に関し、 互いに 1個ずれた信号線に接続されていることを利用することにより、 共通の 端子が近づく ように I C 1と I C 3の部品配置をわずかにずらせるだけ で、 ラン ド及びそれらのラン ドに接続されるパターンを形成することが できる。  Thus, the data output terminals of IC 1 used in model A and IC 3 used in model B are connected to the same signal line to the CPU, and the address input terminal is By using the fact that the address signal lines to the CPU are connected to signal lines that are shifted from each other by one, the component arrangement of IC 1 and IC 3 can be slightly displaced so that the common terminal approaches. , A land and a pattern connected to the land can be formed.
以上のように、 実施の形態 1によれば、 共用のプリ ン ト基板を製作す る場合、 機種 Aと機種 Bで使用するメモリ等の I Cの品種や回路図の内 容を考慮し、 機種 Aと機種 Bで使用する I Cの部品配置を、 共通の端子 が近づく ように、 重ね合わせることによ り、 プリ ン ト基板のサイズを拡 大したり、 それそれ専用のプリ ン ト基板を製作する必要がなく、 また、 専用のプリ ン ト基板とほぼ同一サイズで共用のプリ ン ト基板を実現でき るという効果が得られる。 実施の形態 2.  As described above, according to the first embodiment, when manufacturing a common printed circuit board, the type of the memory and the like used in the model A and the model B and the contents of the circuit diagram are taken into consideration, and The size of the printed circuit board can be increased or a dedicated printed circuit board can be manufactured by superposing the parts of the IC used in A and model B so that the common terminals are close to each other. There is no need to perform this, and an effect is obtained that a shared print substrate having substantially the same size as the dedicated print substrate can be realized. Embodiment 2.
第 5図は実施の形態 2によるプリ ン ト基板の部品配置を示す図である 。 図において、 8， 9は機種 A用の I C、 1 0は機種 B用の I C、 1 1 は機種 A及び機種 B共用のプリ ン ト基板である。 図において、 I C 8, I C 9 , I C 1 0はそれそれ異なった品種のメモリ等の I Cとする。 このように異なった品種のメモリ等の I Cでも、 I Cの品種や回路図 の内容を考慮し、 共通の端子が近づく ように部品を重ね合わせて配置し ても良い。  FIG. 5 is a diagram showing a component arrangement of a printed circuit board according to the second embodiment. In the figure, 8 and 9 are ICs for model A, 10 is an IC for model B, and 11 is a printed circuit board shared by model A and model B. In the drawing, I C8, I C9, and I C10 are ICs of memories and the like of different types, respectively. In this way, even in the case of ICs of different types of memories and the like, the components may be superimposed and arranged so that a common terminal approaches, taking into account the type of IC and the contents of the circuit diagram.
また、 実施の形態 2においては、 I C 8と I C 9が占めている領域内 に I C 1 0用を配置し、 その配線を行うことで、 機種 A用基板と機種 B 用基板とを同じ大きさでかつ他の配線を変更することなく作成すること ができる。 Also, in Embodiment 2, the area occupied by IC 8 and IC 9 is By arranging the IC 10 board and wiring it, it is possible to create a model A board and a model B board with the same size and without changing other wiring.
以上のように、 実施の形態 2 によれば、 共用のプリ ン ト基板を製作す る場合、 実装するメモリ等の I Cの品種が異なっていても、 プリ ン ト基 板のサイズを拡大した り、 それそれ専用のプリ ン ト基板を製作する必要 がなく、 また、 専用のプリ ン ト基板と同一サイズで共用のプリ ン ト基板 を実現できるという効果が得られる。  As described above, according to the second embodiment, when manufacturing a common printed circuit board, the size of the printed circuit board can be increased even if the type of IC such as a memory to be mounted is different. Therefore, there is no need to manufacture a dedicated print substrate for each, and an effect is obtained that a shared print substrate having the same size as the dedicated print substrate can be realized.
さらに、 共用のプリ ン ト基板とすることによ り、 改めて、 基板設計を 始めからやり返す手間を省く ことができ、 また、 専用の基板をそれそれ 作成する場合に比べて、 製作コス トを減少させることができる （例えば 、 機種 A用基板を 5 0 0枚、 機種 B用基板を 5 0 0枚をそれそれ作成す るよ り、 機種 A， B共用基板 1 0 0 0枚を作成した方がコス トが安く な る） 。  Furthermore, by using a common printed circuit board, it is possible to save time and effort in re-designing the circuit board from the beginning, and to reduce the manufacturing cost as compared to the case where dedicated circuit boards are individually created. (For example, rather than creating 50,000 boards for model A and 500 boards for model B, it is better to create 100 boards for both models A and B. Is cheaper).
また、 機種 A用を既に製造していて、 機種 Bを新たに追加する場合に 、 機種 A， B用の共用基板を上述した実施の形態 2のごと く作成した場 合には、 この共用基板を機種 A用の既設の基板組立ライ ンに適用でき 、 基板組立ライ ンの変更をする手間を省く ことができる。  In addition, when the model A is already manufactured and the model B is newly added, and the shared board for the models A and B is created as in the second embodiment, the shared board is used. Can be applied to the existing board assembly line for model A, and the trouble of changing the board assembly line can be saved.
さらに、 上述した実施の形態 1 , 2 においては、 I Cについて説明し たが、 その他のプリ ン ト基板上に実装される素子であればよい。  Furthermore, in Embodiments 1 and 2 described above, IC has been described, but any other element mounted on a printed board may be used.
また、 D— R A Mなどのメモリ に用いた場合、 メモリ数の増減に伴う 、 ア ドレス信号線の配線の変更を容易に行うことができる。 産業上の利用可能性  Also, when used for memories such as DRAMs, it is possible to easily change the wiring of the address signal lines as the number of memories increases or decreases. Industrial applicability
以上のように、 この発明に係るプリ ン ト基板は、 異なった機種でも、 サイズを拡大することなく共用できるものに適している。  As described above, the printed circuit board according to the present invention is suitable for a substrate that can be shared without increasing the size, even between different models.

Claims

請 求 の 範 囲 The scope of the claims
1 . 第 1の機種に使用する第 1の半導体素子と第 2の機種に使用する第 2の半導体素子とが実装されるプリ ン ト基板において、 上記第 1の半導 体素子と上記第 2の半導体素子の実装位置が重なるように配置され、 上 記第 1の半導体素子が実装された場合には、 上記第 1の機種に使用され 、 上記第 2の半導体素子が実装された場合には、 上記第 2の機種に使用 されることを特徴とするプリ ン ト基板。 1. On a printed circuit board on which a first semiconductor element used for a first model and a second semiconductor element used for a second model are mounted, the first semiconductor element and the second When the first semiconductor element is mounted, it is used for the first model, and when the second semiconductor element is mounted, A printed circuit board used for the second model.
2 . 第 1の半導体素子と第 2の半導体素子は、 半導体メモリであること を特徴とする請求の範囲第 1項記載のプリン ト基板。 2. The print substrate according to claim 1, wherein the first semiconductor element and the second semiconductor element are semiconductor memories.
3 . 第 1の機種に使用する第 1及び第 3の半導体素子と第 2の機種に使 用する第 2の半導体素子とが実装されるプリン ト基板において、 上記第 1及び第 3の半導体素子の実装位置内に上記第 2の半導体素子の実装位 置が配置され、 上記第 1及び第 3の半導体素子が実装されることにより 、 上記第 1の機種に使用され、 上記第 2の半導体素子が実装されること により、 上記第 2の機種に使用されることを特徴とするプリ ン ト基板。 3. The printed circuit board on which the first and third semiconductor elements used for the first model and the second semiconductor element used for the second model are mounted, wherein the first and third semiconductor elements are The mounting position of the second semiconductor element is disposed in the mounting position of the second semiconductor element, and the first and third semiconductor elements are mounted, so that the second semiconductor element is used in the first model. A printed circuit board characterized in that the printed circuit board is used in the second model described above by mounting the printed circuit board.
4 . 第 1の半導体素子、 第 2の半導体素子及び第 3の半導体素子は、 半 導体メモリであることを特徴とする請求の範囲第 3項記載のプリン ト基 板。 4. The print substrate according to claim 3, wherein the first semiconductor element, the second semiconductor element, and the third semiconductor element are semiconductor memories.
PCT/JP1998/000486 1998-02-05 1998-02-05 Printed board WO1999040762A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10354036B2 (en) * 2015-07-15 2019-07-16 Yamaha Hatsudoki Kabushiki Kaisha Model data generation device, method of generating model data, mounting reference point determination device, and method of determining mounting reference point

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0446572U (en) * 1990-08-23 1992-04-21
JPH054606U (en) * 1991-06-25 1993-01-22 太陽誘電株式会社 Stripline dielectric resonator
JPH07321451A (en) * 1994-05-26 1995-12-08 Mitsubishi Electric Corp Printed wiring board and semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0446572U (en) * 1990-08-23 1992-04-21
JPH054606U (en) * 1991-06-25 1993-01-22 太陽誘電株式会社 Stripline dielectric resonator
JPH07321451A (en) * 1994-05-26 1995-12-08 Mitsubishi Electric Corp Printed wiring board and semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10354036B2 (en) * 2015-07-15 2019-07-16 Yamaha Hatsudoki Kabushiki Kaisha Model data generation device, method of generating model data, mounting reference point determination device, and method of determining mounting reference point

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