JPS632149B2 - - Google Patents
Info
- Publication number
- JPS632149B2 JPS632149B2 JP16657980A JP16657980A JPS632149B2 JP S632149 B2 JPS632149 B2 JP S632149B2 JP 16657980 A JP16657980 A JP 16657980A JP 16657980 A JP16657980 A JP 16657980A JP S632149 B2 JPS632149 B2 JP S632149B2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- resistor
- group
- block
- terminal group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004020 conductor Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 238000005219 brazing Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Description
【発明の詳細な説明】
本発明は抵抗付端子ブロツクに関するもので、
特にコンピユータなどの高密度集積回路パツケー
ジの回路基板上に外部接続のために設けられる抵
抗付端子ブロツクに関するものである。[Detailed Description of the Invention] The present invention relates to a terminal block with a resistor.
In particular, the present invention relates to a resistor-equipped terminal block provided on a circuit board of a high-density integrated circuit package such as a computer for external connection.
最近、コンピユータの性能は、ますます高速度
のものが要求されてきており、そのために電子回
路は高速度・高集積度のLSIチツプおよびこれら
のLSIチツプを高密度に実装したLSIパツケージ
により構成されている。 Recently, computer performance has been required to be faster and faster, and for this reason, electronic circuits are constructed of high-speed, highly integrated LSI chips and LSI packages that are densely packed with these LSI chips. ing.
また、論理電子回路も、高速化のために周知の
ECL（エミツタカツプルドロジツク）が使用され
ている。 In addition, logic electronic circuits are also well-known to increase speed.
ECL (Emitsuta Katsu Prudology) is used.
従つて、このような電子回路を搭載したLSIパ
ツケージでは、基板上においてLSIチツプ間の高
密度配線を形成するとともにそれぞれの配線に終
端抵抗を接続しなければならない。 Therefore, in an LSI package equipped with such an electronic circuit, it is necessary to form high-density wiring between LSI chips on the substrate and connect a terminating resistor to each wiring.
この終端抵抗は、従来前記LSIパツケージ基板
上に印刷技術によつて形成されるのが普通である
が、このような方法によれば抵抗体の占める面積
が増大しそのためにLSIチツプ間を接続する配線
が高密度に形成されないという欠点がある。 Conventionally, this terminating resistor is usually formed on the LSI package board by printing technology, but this method increases the area occupied by the resistor, which makes it difficult to connect between LSI chips. There is a drawback that wiring cannot be formed with high density.
本発明の目的はLSIパツケージにおいて外部接
続のために設けられた端子ブロツク内に終端抵抗
を形成することによつて上記欠点を解決し、LSI
チツプ間を接続する配線が高密度に形成され得る
抵抗付端子ブロツクを提供することにある。 An object of the present invention is to solve the above-mentioned drawbacks by forming a terminating resistor in a terminal block provided for external connection in an LSI package.
It is an object of the present invention to provide a terminal block with a resistor in which wiring connecting chips can be formed at high density.
本発明による抵抗付端子ブロツクは、LSIパツ
ケージ基板上に外部接続端子を提供するために実
装されるもので、前記LSIパツケージ基板上に搭
載された少なくとも１個のLSIチツプを覆うよう
に取付けられていて、前記LSIパツケージ基板上
に形成された外部接続信号パツドに対応した第１
の端子群と、同じように基板上に形成された終端
抵抗接続パツドに対応した第２の端子群と、前記
第１の端子群に接続されかつ外部接続用ピンを突
設させた第３の端子群と、前記第１および第２の
端子群を接続する抵抗体群を備えていることを特
徴としている。 The terminal block with a resistor according to the present invention is mounted on an LSI package board to provide an external connection terminal, and is attached to cover at least one LSI chip mounted on the LSI package board. The first pad corresponding to the external connection signal pad formed on the LSI package board is
a second group of terminals corresponding to the terminal resistor connection pads similarly formed on the board, and a third group of terminals connected to the first group of terminals and having external connection pins protruding therefrom. It is characterized by comprising a terminal group and a resistor group connecting the first and second terminal groups.
次に本発明について図面を参照して詳細に説明
する。 Next, the present invention will be explained in detail with reference to the drawings.
第１図および第２図は本発明の第１の実施例を
示す全体斜視図および分解斜視図であり、これら
の図において、本発明の抵抗付端子ブロツク１０
は矩形状のブロツク枠１と、このブロツク枠１の
上面を覆う面積を有するブロツク蓋２と、ブロツ
ク枠１の外壁に縦方向に形成された多数の端子か
らなる第１の端子群３と、この第１の端子群３の
各端子と対向してブロツク枠１の内壁に縦方向に
形成された第２の端子群４と、ブロツク枠１の上
面に形成され上記第１および第２の端子群３およ
び４の各端子間を結ぶ抵抗体群５と、ブロツク蓋
２の周壁上において第１の端子群３の各端子に対
応する位置に形成された側面導体６；この側面導
体６の上端に続いてブロツク蓋２の上面に形成さ
れた配線パターン７；この配線パターン７の他端
に突設されたピン８を有する第３の端子群９とか
ら構成されている。 1 and 2 are an overall perspective view and an exploded perspective view showing a first embodiment of the present invention, and in these figures, a resistor-equipped terminal block 10 of the present invention is shown.
1 includes a rectangular block frame 1, a block lid 2 having an area covering the upper surface of the block frame 1, a first terminal group 3 consisting of a large number of terminals formed vertically on the outer wall of the block frame 1, A second terminal group 4 is formed vertically on the inner wall of the block frame 1 to face each terminal of the first terminal group 3, and a second terminal group 4 is formed on the upper surface of the block frame 1 and is connected to the first and second terminals. A resistor group 5 connecting terminals of groups 3 and 4, and a side conductor 6 formed on the peripheral wall of the block lid 2 at a position corresponding to each terminal of the first terminal group 3; the upper end of this side conductor 6 Next, a wiring pattern 7 is formed on the upper surface of the block lid 2; and a third terminal group 9 having a pin 8 protruding from the other end of the wiring pattern 7.
ブロツク枠１およびブロツク蓋２はそれぞれセ
ラミツクから成り、第１，第２の端子群３，４、
および側面導体６が形成される位置に、それぞれ
半円形断面の溝が刻設されている。そして、第
１，第２の端子群３，４および側面導体６はこれ
らの溝に金などの良導体材料をメツキ又は蒸着な
どの方法で固着して形成される。 The block frame 1 and block lid 2 are each made of ceramic, and have first and second terminal groups 3, 4,
Grooves each having a semicircular cross section are formed at the positions where the side conductors 6 are formed. The first and second terminal groups 3 and 4 and the side conductor 6 are formed by fixing a good conductive material such as gold to these grooves by plating or vapor deposition.
一方、抵抗体群５はニクロムなどのような抵抗
体材料を印刷技術によつて形成され、配線パター
ン７は金などの良導体材料を同じように印刷技術
により形成される。 On the other hand, the resistor group 5 is formed using a resistor material such as nichrome using a printing technique, and the wiring pattern 7 is formed using a good conductive material such as gold using a similar printing technique.
また、第３の端子群９の一部を構成するピン８
はそれぞれ例えばブロツク蓋２に明けた穴にさし
込み導体材料で蝋付けすることにより固定、接続
される。 Also, a pin 8 forming part of the third terminal group 9
are fixed and connected, for example, by inserting them into holes made in the block lid 2 and brazing them with a conductive material.
抵抗付端子ブロツク１０は第１図に示すように
ブロツク枠１の上面にブロツク蓋２が組合わせら
れ第１の端子群（以下単に端子という）３と側面
導体６とをそれぞれの接触点１１において、例え
ばハンダ付けなどにより接続されている。 As shown in FIG. 1, the resistor-attached terminal block 10 has a block lid 2 assembled on the top surface of a block frame 1, and connects a first terminal group (hereinafter simply referred to as terminals) 3 and a side conductor 6 at respective contact points 11. , for example, by soldering.
第３図は以上のように構成した抵抗付端子ブロ
ツク１０をLSIパツケージ基板Ｐ上に複数個実装
した状態を示す斜視図であり、第４図は第３図に
示す抵抗付端子ブロツク１０のブロツク蓋２を除
去した状態を示す斜視図である。 FIG. 3 is a perspective view showing a state in which a plurality of terminal blocks 10 with resistors configured as described above are mounted on an LSI package board P, and FIG. 4 is a perspective view of the terminal block 10 with resistors shown in FIG. FIG. 2 is a perspective view showing a state with a lid 2 removed.
第４図において、１２はLSIパツケージ、１３
は終端抵抗接続パツド、１４は信号接続パツドを
示しており、終端抵抗接続パツド１３は基板Ｐ上
の電源又はグランド配線パターンに選択的に接続
され、信号接続パツド１４は同じように基板Ｐ上
の信号線パターンに接続されている。前記パツド
１３，１４と端子４，３とはハンダ付けなどによ
つて容易に基板Ｐ上に接続することができる。さ
らに、本実施例において、終端抵抗接続パツド１
３を基板Ｐ上の配線で終端用電源またはグランド
に接続するか否かによつて前記端子３に終端抵抗
を電気的に接続するか否かを決定できるので、端
子３は入力端子としても出力端子としても使用で
きる。また、ピン８を介して外部に接続すること
ができることは勿論である。 In Figure 4, 12 is an LSI package, 13
14 is a terminal resistor connecting pad, and 14 is a signal connecting pad. The terminating resistor connecting pad 13 is selectively connected to the power supply or ground wiring pattern on the board P, and the signal connecting pad 14 is similarly connected to the power supply or ground wiring pattern on the board P. Connected to the signal line pattern. The pads 13, 14 and the terminals 4, 3 can be easily connected to the substrate P by soldering or the like. Furthermore, in this embodiment, the termination resistor connection pad 1
Terminal 3 can be used as an input terminal as well as an output terminal, since it can be determined whether or not a terminating resistor is electrically connected to the terminal 3 depending on whether or not 3 is connected to the terminating power supply or ground using the wiring on the board P. It can also be used as a terminal. It goes without saying that it can also be connected to the outside via pin 8.
以上説明したように、抵抗付端子ブロツク１０
を使用することにより終端抵抗をLSIパツケージ
基板上に形成する必要がなくなり、極めて高密度
な配線パターンを形成することが容易になり、高
集積度のLSIパツケージを実現することができ
る。 As explained above, the terminal block 10 with resistor
By using this, it is no longer necessary to form a terminating resistor on the LSI package substrate, making it easy to form extremely high-density wiring patterns and realizing highly integrated LSI packages.
本実施例の他のすぐれた効果として、第４図に
示すように基板Ｐ上にブロツク枠１をまず接続し
回路の試験を行なつたのち、ブロツク蓋２を前記
ブロツク枠１の上面に接続することが可能であ
り、また故障などにより端子ブロツク１０内部を
チエツクしたい場合でもブロツク蓋２のみを取外
せばよく製造検査、保守点検上の容易性がある。 Another excellent effect of this embodiment is that, as shown in FIG. 4, the block frame 1 is first connected on the board P and the circuit is tested, and then the block cover 2 is connected to the top surface of the block frame 1. Furthermore, even if it is desired to check the inside of the terminal block 10 due to a failure or the like, it is only necessary to remove the block cover 2, which facilitates manufacturing inspection and maintenance inspection.
第５図は本発明の第２の実施例を示す分解斜視
図である。この場合前記実施例と異なるところ
は、ブロツク枠とこのブロツク枠に形成される第
２の端子群と抵抗体群などである。すなわち第５
図において、ブロツク枠２１は矩形状の中空セラ
ミツクからなり、外周壁には縦方向に複数本の半
円形溝が刻設され第１の端子群２３が形成されて
いる。この第１の端子群２３の各端子に対向して
いてブロツク枠２１の内周壁には下部に第２の端
子群２４が半円形溝に形成されている。この第２
の端子群２４の各端子の上端部からブロツク枠２
１の上面まで延びる抵抗体群２５が形成されてい
る。そしてこの抵抗体群２５の各抵抗体上端部と
前記第１の端子群２３の各端子上端部とがブロツ
ク枠２１の上面において配線２６を介して接続さ
れている。この実施例は前記実施例の場合と等し
い効果を奏することは明らかである。 FIG. 5 is an exploded perspective view showing a second embodiment of the invention. In this case, the differences from the previous embodiment include the block frame, the second terminal group and the resistor group formed in the block frame. That is, the fifth
In the figure, a block frame 21 is made of rectangular hollow ceramic, and a plurality of semicircular grooves are cut in the vertical direction on the outer circumferential wall, and a first terminal group 23 is formed. A second terminal group 24 is formed in a semicircular groove in the lower part of the inner peripheral wall of the block frame 21, facing each terminal of the first terminal group 23. This second
block frame 2 from the upper end of each terminal of the terminal group 24.
A resistor group 25 extending to the upper surface of the resistor 1 is formed. The upper end of each resistor of this resistor group 25 and the upper end of each terminal of the first terminal group 23 are connected via wiring 26 on the upper surface of the block frame 21. It is clear that this embodiment has the same effect as the previous embodiment.
第１，第２及び第３の端子群および抵抗体群と
の位置関係は、上述の二つの実施例に限定される
ものでなくブロツク１０，２０内に配置される限
りすべて本発明に包含されるものである。 The positional relationship between the first, second, and third terminal groups and the resistor group is not limited to the two embodiments described above, and all are included in the present invention as long as they are arranged within the blocks 10 and 20. It is something that
以上説明したように本発明の抵抗付端子ブロツ
クは極めて高密度なLSIパツケージ基板を実現さ
せることができる。 As explained above, the resistor-equipped terminal block of the present invention can realize an extremely high-density LSI package board.
第１図および第２図は本発明の第１の実施例を
示す全体斜視図および分解斜視図、第３図は第１
の実施例を基板に実装した状態を示す斜視図、第
４図は第３図の一部分解拡大斜視図、第５図は本
発明の第２の実施例を示す分解斜視図であつて、
これらの図において、１，２１はブロツク枠、２
はブロツク蓋、３は第１の端子群、４，２４は第
２の端子群、５，２５は抵抗体群、８はピン、１
０，２０は抵抗付端子ブロツクである。
1 and 2 are an overall perspective view and an exploded perspective view showing a first embodiment of the present invention, and FIG. 3 is a first embodiment of the present invention.
4 is a partially exploded enlarged perspective view of FIG. 3, and FIG. 5 is an exploded perspective view showing a second embodiment of the present invention,
In these figures, 1 and 21 are block frames, 2
is the block lid, 3 is the first terminal group, 4 and 24 are the second terminal group, 5 and 25 are the resistor group, 8 is the pin, 1
0 and 20 are terminal blocks with resistors.
Claims (1)
群と、これら第１および第２の端子群のそれぞれ
の端子間を接続する抵抗体群と、前記第１の端子
群のそれぞれの端子に接続されかつ外部接続のた
めにピンを突設させた第３の端子群とを有してい
て、前記回路基板に塔載された少なくとも１個の
ICチツプを覆うように取付けたことを特徴とす
る抵抗付端子ブロツク。1. A first and second terminal group that can be connected to a circuit board, a resistor group that connects the respective terminals of the first and second terminal groups, and a resistor group that connects each terminal of the first terminal group. and a third terminal group having protruding pins for external connection, and at least one terminal group mounted on the circuit board.
A terminal block with a resistor that is installed so as to cover an IC chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16657980A JPS5791585A (en) | 1980-11-28 | 1980-11-28 | Terminal block with resistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16657980A JPS5791585A (en) | 1980-11-28 | 1980-11-28 | Terminal block with resistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5791585A JPS5791585A (en) | 1982-06-07 |
| JPS632149B2 true JPS632149B2 (en) | 1988-01-18 |
Family
ID=15833882
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16657980A Granted JPS5791585A (en) | 1980-11-28 | 1980-11-28 | Terminal block with resistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5791585A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6437042A (en) * | 1987-07-31 | 1989-02-07 | Ibiden Co Ltd | Substrate for carrying electronic component |
| JPH0250465A (en) * | 1988-08-12 | 1990-02-20 | Hitachi Ltd | Module structure |
-
1980
- 1980-11-28 JP JP16657980A patent/JPS5791585A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5791585A (en) | 1982-06-07 |
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