JP3520213B2 - Semiconductor wafer with columnar electrode and method of manufacturing the same - Google Patents

Semiconductor wafer with columnar electrode and method of manufacturing the same

Info

Publication number
JP3520213B2
JP3520213B2 JP01822999A JP1822999A JP3520213B2 JP 3520213 B2 JP3520213 B2 JP 3520213B2 JP 01822999 A JP01822999 A JP 01822999A JP 1822999 A JP1822999 A JP 1822999A JP 3520213 B2 JP3520213 B2 JP 3520213B2
Authority
JP
Japan
Prior art keywords
plating film
semiconductor wafer
columnar
electrode
columnar electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP01822999A
Other languages
Japanese (ja)
Other versions
JP2000216111A (en
Inventor
義博 井原
壮 小林
信一 若林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP01822999A priority Critical patent/JP3520213B2/en
Priority to TW089101296A priority patent/TW444288B/en
Priority to KR1020000003629A priority patent/KR100687548B1/en
Priority to EP00300613A priority patent/EP1024531A3/en
Publication of JP2000216111A publication Critical patent/JP2000216111A/en
Priority to US10/323,645 priority patent/US7220657B2/en
Application granted granted Critical
Publication of JP3520213B2 publication Critical patent/JP3520213B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01046Palladium [Pd]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Landscapes

  • Electrodes Of Semiconductors (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体ウエハを用い
てチップサイズパッケージを製造する際に使用する柱状
電極付き半導体ウエハとその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor wafer with columnar electrodes used for manufacturing a chip size package using a semiconductor wafer and a method for manufacturing the semiconductor wafer.

【0002】[0002]

【従来の技術】図5は半導体ウエハを用いてチップサイ
ズパッケージを製造する際に使用する柱状電極が形成さ
れた半導体ウエハの製造方法を示す。図5(a) は半導体
ウエハ10を拡大して示す断面図で、半導体ウエハ10
の表面に電極端子12とパッシベーション膜14が形成
された状態を示す。この半導体ウエハ10の表面に、ポ
リイミド膜をコーティングし、電極端子12を露出させ
た絶縁層16を形成する(図5(b))。次に、スパッタリ
ングを施して絶縁層16と電極端子12の表面にめっき
給電層となる導体層18を形成する(図5(c))。次に、
レジストを塗布し、半導体ウエハ10の表面に形成する
配線パターンにしたがってレジストパターン20を形成
し(図5(d))、前記導体層18をめっき給電層として銅
めっきを施して配線パターン22を形成する(図5
(e))。配線パターン22は一端側が電極端子12に接続
し、他端側に柱状電極を立設するためのパッド部が形成
されたものである。
2. Description of the Related Art FIG. 5 shows a method for manufacturing a semiconductor wafer having columnar electrodes used for manufacturing a chip size package using the semiconductor wafer. FIG. 5A is a sectional view showing the semiconductor wafer 10 in an enlarged manner.
2 shows a state in which the electrode terminals 12 and the passivation film 14 are formed on the surface of the. A polyimide film is coated on the surface of the semiconductor wafer 10 to form an insulating layer 16 exposing the electrode terminals 12 (FIG. 5 (b)). Next, sputtering is performed to form a conductor layer 18 serving as a plating power supply layer on the surfaces of the insulating layer 16 and the electrode terminal 12 (FIG. 5 (c)). next,
A resist is applied, a resist pattern 20 is formed according to the wiring pattern formed on the surface of the semiconductor wafer 10 (FIG. 5 (d)), and copper plating is performed using the conductor layer 18 as a plating power supply layer to form a wiring pattern 22. Yes (Fig. 5
(e)). The wiring pattern 22 has one end connected to the electrode terminal 12 and the other end formed with a pad portion for standingly providing a columnar electrode.

【0003】次に、電解めっきを施して柱状電極24を
形成する。そのため、まず、図5(e) の状態からレジス
トパターン20を除去した後、再度、半導体ウエハ10
の表面にレジスト26を塗布し、配線パターン22のパ
ッド部に位置合わせして柱状電極24を形成する部位の
レジスト26を除去し、開口穴26aを形成する。柱状
電極24は高さ100μm程度に形成するもので、レジ
スト26は柱状電極24の高さよりもやや厚く形成する
ようにする。
Next, electrolytic plating is performed to form columnar electrodes 24. Therefore, first, the resist pattern 20 is removed from the state of FIG.
A resist 26 is applied to the surface of the above, and the resist 26 in the portion where the columnar electrode 24 is formed by aligning with the pad portion of the wiring pattern 22 is removed to form an opening hole 26a. The columnar electrode 24 is formed to have a height of about 100 μm, and the resist 26 is formed to be slightly thicker than the height of the columnar electrode 24.

【0004】柱状電極24は電解銅めっきを施して開口
穴26a内に銅めっきを盛り上げて形成する。図5(f)
は柱状電極24を形成した状態で、柱状電極24の頂部
端面にはめっき被膜が形成されている。図5(g) はレジ
スト26を除去した後、半導体ウエハの表面に露出した
導体層18をエッチングして除去した状態である。導体
層18をエッチングすることによって、電極端子形成面
に一端側で電極端子12に電気的に接続された配線パタ
ーン22が形成され、配線パターン22の他端側に柱状
電極24が形成された半導体ウエハ10が得られる。
The columnar electrodes 24 are formed by electrolytic copper plating and raising the copper plating in the opening holes 26a. Figure 5 (f)
With the columnar electrode 24 formed, a plating film is formed on the top end surface of the columnar electrode 24. FIG. 5G shows a state in which after removing the resist 26, the conductor layer 18 exposed on the surface of the semiconductor wafer is removed by etching. By etching the conductor layer 18, the wiring pattern 22 electrically connected to the electrode terminal 12 at one end side is formed on the electrode terminal forming surface, and the columnar electrode 24 is formed at the other end side of the wiring pattern 22. The wafer 10 is obtained.

【0005】こうして得られた半導体ウエハ10は各々
の電極端子12に対応して一つずつ柱状電極24が形成
されたものであり、半導体ウエハ10の表面には多数個
の柱状電極24が形成されている。図6はこの柱状電極
24が形成された半導体ウエハ10を樹脂封止する方法
を示す。柱状電極24を上向きにして下型31に半導体
ウエハ10をのせ、半導体ウエハ10の上に封止用の樹
脂材28を供給した後、封止用フィルム30をクランプ
面に吸着した上型32により下型31との間で半導体ウ
エハ10をクランプする。このクランプ操作により半導
体ウエハ10の電極端子形成面側に溶融樹脂が広がって
樹脂封止される。樹脂封止後、封止用フィルム30が被
着した半導体ウエハ10を金型から取り出し、封止用フ
ィルム30を半導体ウエハ10から引き剥がす。柱状電
極24の頂部端面にに実装用の端子(例えばはんだボー
ル)を接合した後、半導体ウエハを個片のチップサイズ
に切断することによってチップサイズパッケージが得ら
れる。
The semiconductor wafer 10 thus obtained has columnar electrodes 24 formed one by one corresponding to each electrode terminal 12, and a large number of columnar electrodes 24 are formed on the surface of the semiconductor wafer 10. ing. FIG. 6 shows a method of resin-sealing the semiconductor wafer 10 on which the columnar electrodes 24 are formed. The semiconductor wafer 10 is placed on the lower mold 31 with the columnar electrode 24 facing upward, and the resin material 28 for sealing is supplied onto the semiconductor wafer 10, and then the upper mold 32 that adsorbs the sealing film 30 on the clamp surface is used. The semiconductor wafer 10 is clamped between the lower die 31 and the lower die 31. By this clamping operation, the molten resin spreads on the surface of the semiconductor wafer 10 on which the electrode terminals are formed, and the resin is sealed. After the resin sealing, the semiconductor wafer 10 with the sealing film 30 adhered is taken out from the mold, and the sealing film 30 is peeled off from the semiconductor wafer 10. A chip size package is obtained by bonding a mounting terminal (for example, a solder ball) to the top end surface of the columnar electrode 24 and then cutting the semiconductor wafer into individual chip sizes.

【0006】[0006]

【発明が解決しようとする課題】上述した製造方法で、
半導体ウエハ10を樹脂封止する際に封止用フィルム3
0で柱状電極24の頂部端面を被覆しているのは、柱状
電極24の頂部端面に封止樹脂が付着しないようにする
ためであるが、柱状電極24の高さにばらつきがあると
いった理由により、樹脂封止した際に柱状電極24の頂
部端面に封止樹脂が侵入し柱状電極24に樹脂が付着し
て残留することがある。半導体ウエハ10を樹脂封止し
た後、封止用フィルム30を半導体ウエハ10から引き
剥がすようにするのは、柱状電極24の頂部端面に残留
した樹脂を封止用フィルム30に付着させて除去するた
めである。
With the above-described manufacturing method,
Film 3 for sealing when the semiconductor wafer 10 is resin-sealed
The reason why the top end surface of the columnar electrode 24 is covered with 0 is to prevent the sealing resin from adhering to the top end surface of the columnar electrode 24. However, the height of the columnar electrode 24 varies. When the resin is sealed, the sealing resin may enter the top end surface of the columnar electrode 24, and the resin may adhere to and remain on the columnar electrode 24. After the semiconductor wafer 10 is resin-sealed, the sealing film 30 is peeled off from the semiconductor wafer 10. The resin remaining on the top end surface of the columnar electrode 24 is attached to the sealing film 30 and removed. This is because.

【0007】しかし、封止用フィルム30を半導体ウエ
ハ10から引き剥がしただけで柱状電極24の頂部端面
に残留した樹脂が確実に除去されるとは限らない。柱状
電極24の頂部端面は、はんだボール等の実装用の端子
を接合する接合面であるから、樹脂が柱状電極24の頂
部端面に付着していることは柱状電極24と端子との接
合性の点で問題となる。このため、封止用フィルム30
を引き剥がした後、ブラスト等によって柱状電極24の
頂部端面をクリーニングすることがなされている。
However, just peeling off the sealing film 30 from the semiconductor wafer 10 does not necessarily ensure that the resin remaining on the top end surface of the columnar electrode 24 is removed. Since the top end surface of the columnar electrode 24 is a joint surface for joining a mounting terminal such as a solder ball or the like, the fact that the resin is attached to the top end surface of the columnar electrode 24 indicates that the columnar electrode 24 and the terminal are joined together. There is a problem in terms. Therefore, the sealing film 30
After peeling off, the top end surface of the columnar electrode 24 is cleaned by blasting or the like.

【0008】しかしながら、このようなクリーニングに
よっても必ずしも柱状電極24の頂部端面に残留した樹
脂を完全に取り除くことができず、また、柱状電極24
の頂部端面から完全に樹脂を取り除くため過度にクリー
ニングすると、逆に封止樹脂を劣化させてしまうといっ
た問題も生じる。このように、従来の柱状電極付き半導
体ウエハの製造方法では柱状電極の端面に樹脂が残留し
て、柱状電極と実装用の端子との接合性が阻害されるこ
とが課題となっていた。本発明はこれら従来の課題を解
決すべくなされたものであり、その目的とするところ
は、柱状電極と実装用の端子との接合性を良好にし、こ
れによって信頼性の高いチップサイズパッケージを得る
ことができる柱状電極付き半導体ウエハ及びその好適な
製造方法を提供することにある。
However, such cleaning cannot always completely remove the resin remaining on the top end surface of the columnar electrode 24, and the columnar electrode 24
If the resin is excessively cleaned to completely remove the resin from the top end surface of the above, there is a problem that the sealing resin is deteriorated. As described above, in the conventional method for manufacturing a semiconductor wafer with columnar electrodes, the resin remains on the end faces of the columnar electrodes, which impairs the bondability between the columnar electrodes and the mounting terminals. The present invention has been made to solve these conventional problems, and an object thereof is to improve the bondability between a columnar electrode and a mounting terminal, thereby obtaining a highly reliable chip size package. It is an object of the present invention to provide a semiconductor wafer with a columnar electrode and a suitable method for manufacturing the semiconductor wafer.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するた
め、本発明は次の構成を備える。すなわち、半導体ウエ
ハの電極端子形成面に、一端側が各電極端子に接続され
た配線パターンが絶縁層を介して形成され、該各配線パ
ターンの他端側に柱状電極が形成され、該柱状電極の頂
部端面を露出して樹脂封止された柱状電極付き半導体ウ
エハにおいて、前記柱状電極の頂部端面に、ニッケルめ
っき被膜が形成され、該ニッケルめっき被膜上にパラジ
ウムめっき被膜及び金めっき被膜が順次形成されている
ことを特徴とする。めっき被膜としては、前記パラジウ
ムめっき被膜が0.1μm以下の厚さに形成され、金め
っき被膜が0.001μm〜0.1μmの厚さに形成さ
れているものが好適であり、パラジウムめっき被膜が
0.05μm〜0.1μmの厚さに形成され、金めっき
被膜が0.01μm〜0.05μmの厚さに形成されて
いるものがさらに好適である。
In order to achieve the above object, the present invention has the following constitution. That is, a wiring pattern whose one end side is connected to each electrode terminal is formed on an electrode terminal formation surface of a semiconductor wafer through an insulating layer, and a columnar electrode is formed on the other end side of each wiring pattern. In a semiconductor wafer with a columnar electrode having a top end face exposed and resin-sealed, a nickel plating film is formed on the top end face of the columnar electrode, and a palladium plating film and a gold plating film are sequentially formed on the nickel plating film. It is characterized by As the plating film, it is preferable that the palladium plating film is formed to a thickness of 0.1 μm or less and the gold plating film is formed to a thickness of 0.001 μm to 0.1 μm. It is more preferable that the gold plating film is formed to a thickness of 0.05 μm to 0.1 μm, and the gold plating film is formed to a thickness of 0.01 μm to 0.05 μm.

【0010】また、柱状電極付き半導体ウエハの製造方
法として、半導体ウエハの電極端子形成面を電極端子を
露出して絶縁層により被覆し、前記電極端子及び絶縁層
の表面に導体層を形成した後、導体層の表面にレジスト
パターンを形成して前記導体層をめっき給電層として銅
めっきを施すことにより一端側が各電極端子に接続する
配線パターンを形成し、前記レジストパターンを除去し
た後、前記導体層及び配線パターンの表面にレジストを
塗布し、配線パターンの他端側の柱状電極を形成する部
位のレジストに、底面に配線パターンの他端側が露出す
る開口穴を形成し、前記導体層をめっき給電層として前
記開口穴内に銅めっきを施して、前記開口穴内に柱状電
極を形成した後、該柱状電極の頂部端面にニッケルめっ
き被膜を形成し、該ニッケルめっき被膜上にパラジウム
めっき被膜及び金めっき被膜を順次形成し、前記レジス
トを除去して、表面に露出する前記導体層を除去した
後、前記金めっき被膜の表面が露出するように半導体ウ
エハの電極端子形成面側を樹脂封止することを特徴とす
る。
Further, as a method of manufacturing a semiconductor wafer with columnar electrodes, after the electrode terminal forming surface of the semiconductor wafer is exposed with an electrode layer and covered with an insulating layer, a conductor layer is formed on the surface of the electrode terminal and the insulating layer. A conductor pattern is formed on the surface of the conductor layer, and the conductor layer is subjected to copper plating as a plating power supply layer to form a wiring pattern whose one end side is connected to each electrode terminal, and after removing the resist pattern, the conductor A resist is applied to the surface of the layer and the wiring pattern, an opening hole is formed in the bottom surface of the wiring pattern where the other end of the wiring pattern is exposed, and the conductor layer is plated in the resist at the site where the columnar electrode is to be formed. Copper plating is performed in the opening hole as a power supply layer to form a columnar electrode in the opening hole, and then a nickel plating film is formed on the top end surface of the columnar electrode, A palladium plating film and a gold plating film are sequentially formed on the nickel plating film, the resist is removed, and the conductor layer exposed on the surface is removed, and then the surface of the gold plating film is exposed on the semiconductor wafer. It is characterized in that the electrode terminal formation surface side is resin-sealed.

【0011】[0011]

【発明の実施の形態】以下、本発明の好適な実施形態を
添付図面に基づいて詳細に説明する。本発明に係る柱状
電極付き半導体ウエハは半導体ウエハに形成する柱状電
極の構成をもっとも特徴とする。図1は本発明に係る柱
状電極付き半導体ウエハの実施形態の構成を示す全体
図、図2は柱状電極付き半導体ウエハに形成された柱状
電極の構成を拡大して示す断面図である。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The semiconductor wafer with columnar electrodes according to the present invention is most characterized by the structure of columnar electrodes formed on the semiconductor wafer. FIG. 1 is an overall view showing the configuration of an embodiment of a semiconductor wafer with columnar electrodes according to the present invention, and FIG. 2 is an enlarged sectional view showing the configuration of columnar electrodes formed on a semiconductor wafer with columnar electrodes.

【0012】本実施形態の柱状電極付き半導体ウエハ
は、前述した従来の柱状電極付き半導体ウエハと比較し
て柱状電極部分のめっき被膜に関する構成を除いては同
一の構成である。したがって、以下では、本発明で特徴
的な柱状電極部分の構成を主として説明する。なお、以
下の説明で従来の柱状電極付き半導体ウエハと同一の部
位については同一の番号を付している。
The semiconductor wafer with columnar electrodes of the present embodiment has the same structure as that of the conventional semiconductor wafer with columnar electrodes described above, except for the structure relating to the plating film on the columnar electrode portion. Therefore, in the following, the configuration of the columnar electrode portion that is characteristic of the present invention will be mainly described. In the following description, the same parts as those of the conventional semiconductor wafer with columnar electrodes are designated by the same reference numerals.

【0013】柱状電極付ウエハは、半導体ウエハ10の
電極端子形成面に絶縁層16を介して一端側で電極端子
12に電気的に接続する配線パターン22を形成し、配
線パターン22の他端側に柱状電極24を立設し、半導
体ウエハ10の電極端子形成面側を柱状電極24の頂部
端面を露出して封止樹脂28によって封止して成るもの
である。図1に示すように、樹脂28は隣接するすべて
の柱状電極24の間を充填して半導体ウエハ10の電極
端子形成面を封止している。
In the wafer with columnar electrodes, a wiring pattern 22 electrically connected to the electrode terminals 12 at one end side is formed on the electrode terminal formation surface of the semiconductor wafer 10 through the insulating layer 16, and the other end side of the wiring pattern 22 is formed. The columnar electrode 24 is erected on the surface of the semiconductor wafer 10, and the electrode terminal formation surface side of the semiconductor wafer 10 is sealed with a sealing resin 28 with the top end surface of the columnar electrode 24 exposed. As shown in FIG. 1, the resin 28 fills the space between all adjacent columnar electrodes 24 to seal the electrode terminal formation surface of the semiconductor wafer 10.

【0014】本実施形態の柱状電極付き半導体ウエハで
特徴とする構成は、図2に示すように、柱状電極24の
導体部として銅めっき部40が設けられ、銅めっき部4
0の頂部端面にニッケルめっき被膜42、パラジウムめ
っき被膜44、金めっき被膜46から成るめっき被膜4
1をこの順に設けることにある。
As shown in FIG. 2, the semiconductor wafer with a columnar electrode of the present embodiment is characterized in that a copper plated portion 40 is provided as a conductor portion of the columnar electrode 24 and a copper plated portion 4 is provided.
A plating film 4 including a nickel plating film 42, a palladium plating film 44, and a gold plating film 46 on the top end surface of 0.
1 is provided in this order.

【0015】柱状電極24の銅めっき部40の頂部端面
にめっき被膜を設けることは従来も行われている。本発
明に係る柱状電極24は銅めっき部40の上にニッケル
めっき被膜42、パラジウムめっき被膜44、金めっき
被膜46の3層構造から成るめっき被膜41を設けたこ
とによって、実装用の外部接続端子(例えば、はんだボ
ール)と柱状電極24との接合性を良好とすることがで
き、また、めっき被膜41に形成するパラジウムめっき
被膜44の厚さを薄くすることが可能となる。
It has been conventionally practiced to form a plating film on the top end surface of the copper plating portion 40 of the columnar electrode 24. In the columnar electrode 24 according to the present invention, the plating film 41 having a three-layer structure of the nickel plating film 42, the palladium plating film 44, and the gold plating film 46 is provided on the copper plating part 40, so that the external connection terminal for mounting is provided. (For example, a solder ball) and the columnar electrode 24 can be bonded well, and the thickness of the palladium plating film 44 formed on the plating film 41 can be reduced.

【0016】柱状電極24に設けるめっき被膜を、はん
だ拡散防止用のニッケルめっき被膜と、はんだ濡れ性を
良好にするパラジウムめっき被膜の2層構造にした場合
は、ニッケルめっき被膜の厚さを3μm程度、パラジウ
ムめっき被膜の厚さを0.1〜0.15μm程度とする
必要がある。これに対して、本実施形態のように、ニッ
ケルめっき被膜42、パラジウムめっき被膜44、金め
っき被膜46の3層構造のめっき被膜41とした場合
は、パラジウムめっき被膜44の厚さは0.1μm以下
(好適には、0.05μm〜0.1μm)と2層構造の
場合の半分程度の厚さとすることができる。また、金め
っき被膜46の厚さも0.001μm〜0.1μm(好
適には、0.01μm〜0.05μm)のきわめて薄い
ものでよい。このように、パラジウムめっき被膜44の
厚さを薄くできる理由は、金めっき被膜46を設けるこ
とによってパラジウムめっき被膜44のみを設けた場合
にくらべてはんだの濡れ性を効果的に改善できるからで
ある。
When the plating film provided on the columnar electrode 24 has a two-layer structure of a nickel plating film for preventing solder diffusion and a palladium plating film for improving solder wettability, the thickness of the nickel plating film is about 3 μm. The thickness of the palladium plating film needs to be about 0.1 to 0.15 μm. On the other hand, when the plating film 41 having the three-layer structure of the nickel plating film 42, the palladium plating film 44, and the gold plating film 46 is used as in the present embodiment, the thickness of the palladium plating film 44 is 0.1 μm. The thickness may be the following (preferably 0.05 μm to 0.1 μm), which is about half the thickness of the two-layer structure. Further, the thickness of the gold plating film 46 may be extremely thin such as 0.001 μm to 0.1 μm (preferably 0.01 μm to 0.05 μm). As described above, the reason why the thickness of the palladium plating film 44 can be reduced is that the wettability of the solder can be effectively improved by providing the gold plating film 46 as compared with the case where only the palladium plating film 44 is provided. .

【0017】柱状電極に外部接続端子としてはんだボー
ルを接合した場合は、溶融したはんだ中に金めっき被膜
46とパラジウムめっき被膜44がともに拡散してはん
だボールはニッケルめっき被膜42に接合することにな
る。このように、金めっき被膜46およびパラジウムめ
っき被膜44ははんだの濡れ性に寄与するものであり、
本実施形態のようにめっき被膜の外表面に金めっき被膜
46を設けると、パラジウムめっき被膜44を単独で設
けた場合にくらべてパラジウムめっき被膜44の厚さを
薄くしても十分なはんだ濡れ性を得ることが可能にな
る。そして、金めっき被膜46もフラッシュめっき程度
にきわめて薄く設けるだけで良好なはんだ付け性を得る
ことができる。
When a solder ball is bonded to the columnar electrode as an external connection terminal, the gold plating film 46 and the palladium plating film 44 are both diffused in the molten solder and the solder ball is bonded to the nickel plating film 42. . Thus, the gold plating film 46 and the palladium plating film 44 contribute to the wettability of the solder,
When the gold plating film 46 is provided on the outer surface of the plating film as in the present embodiment, the solder wettability is sufficient even if the thickness of the palladium plating film 44 is reduced as compared with the case where the palladium plating film 44 is provided alone. It will be possible to obtain. Good solderability can be obtained by providing the gold plating film 46 as thin as flash plating.

【0018】そして、パラジウムめっき被膜44と金め
っき被膜46によりはんだ濡れ性を改善することによっ
て、半導体ウエハ10を封止した際に樹脂28が柱状電
極24の頂部端面に形成しためっき被膜の表面に多少付
着していても、はんだボール等の実装用の外部接続端子
と柱状電極24とを確実に接合することが可能になる。
これによって、半導体ウエハ10を封止した後、めっき
被膜41の表面に残留した樹脂を完全に除去するために
柱状電極24の頂部端面に形成しためっき被膜41を過
度にクリーニングしたりする必要がなくなる。
By improving the solder wettability with the palladium plating film 44 and the gold plating film 46, the resin 28 is formed on the surface of the plating film formed on the top end face of the columnar electrode 24 when the semiconductor wafer 10 is sealed. Even if a small amount is attached, the external connection terminal for mounting such as a solder ball and the columnar electrode 24 can be reliably joined.
Thus, after sealing the semiconductor wafer 10, there is no need to excessively clean the plating film 41 formed on the top end surface of the columnar electrode 24 in order to completely remove the resin remaining on the surface of the plating film 41. .

【0019】また、樹脂28と金めっき被膜46の表面
との密着性が低いことから、めっき被膜46の表面を金
めっき被膜46とすることにより、半導体ウエハ10の
電極端子形成面側を樹脂封止した後、封止用フィルム3
0を引き剥がす際に金めっき被膜46の表面に付着して
残った樹脂28を封止用フィルム30に付着させて剥離
しやすくし、金めっき被膜46の表面に樹脂28が残留
しないようにすることができるという作用もある。
Further, since the adhesion between the resin 28 and the surface of the gold plating film 46 is low, the surface of the plating film 46 is made the gold plating film 46 so that the surface of the semiconductor wafer 10 on which the electrode terminals are formed is sealed with resin. After stopping, sealing film 3
The resin 28 remaining on the surface of the gold plating film 46 when the 0 is peeled off is attached to the sealing film 30 to facilitate the peeling, and the resin 28 does not remain on the surface of the gold plating film 46. There is also the effect that you can.

【0020】図3は柱状電極付き半導体ウエハの製造方
法の実施形態を示す。柱状電極付き半導体ウエハの製造
方法は柱状電極24に設けるめっき被膜41の構成を除
いて従来方法と同一である。したがって、図3では主と
してめっき被膜41を形成する工程を示す。図3(a)
は、半導体ウエハ10の電極端子形成面に絶縁層16を
介して、一端側が電極端子12と電気的に接続する配線
パターン22を形成し、導体層18及び配線パターン2
2の表面にレジスト26を塗布し、配線パターン22の
他端側の柱状電極を形成する部位のレジスト26に、底
面に配線パターン22の他端側が露出する開口穴26a
を形成した状態を示す。
FIG. 3 shows an embodiment of a method of manufacturing a semiconductor wafer with columnar electrodes. The method of manufacturing the semiconductor wafer with columnar electrodes is the same as the conventional method except for the configuration of the plating film 41 provided on the columnar electrodes 24. Therefore, FIG. 3 mainly shows the step of forming the plating film 41. Figure 3 (a)
Forms a wiring pattern 22 whose one end side is electrically connected to the electrode terminal 12 through the insulating layer 16 on the electrode terminal formation surface of the semiconductor wafer 10, and the conductor layer 18 and the wiring pattern 2 are formed.
The resist 26 is applied to the surface of No. 2 and the opening 26a where the other end side of the wiring pattern 22 is exposed on the bottom surface is formed in the resist 26 at the portion where the columnar electrode is formed on the other end side of the wiring pattern 22.
The state in which the is formed is shown.

【0021】開口穴26aを形成した後、導体層18を
めっき給電層として電解銅めっきを施し開口穴26a内
に銅めっき部40を形成する(図3(b))。銅めっき部4
0は柱状電極24の導体部となるもので、開口穴26a
をほぼ充填する程度の厚さにめっきを盛り上げて形成す
る。柱状電極24の高さは100μm程度であり、レジ
スト26もこれに合わせて100μm程度の厚さに形成
する。
After forming the opening hole 26a, electrolytic copper plating is performed using the conductor layer 18 as a plating power supply layer to form a copper plating portion 40 in the opening hole 26a (FIG. 3 (b)). Copper plating part 4
Reference numeral 0 indicates a conductor portion of the columnar electrode 24, and the opening hole 26a
Is formed by swelling the plating to a thickness that substantially fills the. The height of the columnar electrode 24 is about 100 μm, and the resist 26 is also formed to a thickness of about 100 μm in accordance with this.

【0022】次に、ニッケルめっき、パラジウムめっ
き、金めっきをこの順に施して銅めっき部40の上にめ
っき被膜41を形成する(図3(c))。めっき被膜41は
ニッケルめっき被膜42、パラジウムめっき被膜44、
金めっき被膜46の3層構造となる。前述したように、
ニッケルめっき被膜42の厚さは3μm、パラジウムめ
っき被膜44の厚さは0.05μm、金めっき被膜46
の厚さは0.01μmである。
Next, nickel plating, palladium plating and gold plating are performed in this order to form a plating film 41 on the copper plating portion 40 (FIG. 3 (c)). The plating film 41 is a nickel plating film 42, a palladium plating film 44,
It has a three-layer structure of the gold plating film 46. As previously mentioned,
The nickel plating film 42 has a thickness of 3 μm, the palladium plating film 44 has a thickness of 0.05 μm, and the gold plating film 46.
Has a thickness of 0.01 μm.

【0023】めっき被膜41を形成した後、レジスト2
6を除去し、半導体ウエハ10の表面に露出した導体層
18をエッチングすることによって、ニッケルめっき被
膜42、パラジウムめっき被膜44、金めっき被膜46
の3層構造からなるめっき被膜41が頂部端面に形成さ
れた柱状電極24を有する半導体ウエハ10が得られ
る。導体層18は0.05μm程度の厚さであり、柱状
電極24および配線パターン22にくらべてきわめて薄
く形成されているから、柱状電極24と配線パターン2
2をレジスト等で被覆して保護することなく、導体層1
8のみをエッチングして除去することができる。
After forming the plating film 41, the resist 2
By removing 6 and etching the conductor layer 18 exposed on the surface of the semiconductor wafer 10, the nickel plating film 42, the palladium plating film 44, and the gold plating film 46.
The semiconductor wafer 10 having the columnar electrodes 24 having the plating film 41 having the three-layer structure formed on the top end face thereof is obtained. Since the conductor layer 18 has a thickness of about 0.05 μm and is formed extremely thinner than the columnar electrode 24 and the wiring pattern 22, the columnar electrode 24 and the wiring pattern 2 are formed.
Conductor layer 1 without covering 2 with resist or the like for protection
Only 8 can be removed by etching.

【0024】本実施形態でのめっき被膜41を形成する
工程は、銅めっき部40にめっきを施す従来方法がその
まま適用でき、ニッケルめっき被膜42、パラジウムめ
っき被膜44、金めっき被膜46の3層のめっき層を積
層することは容易である。こうして、半導体ウエハ10
に柱状電極24を形成した後、図6に示すように、柱状
電極24の頂部端面に形成した金めっき被膜の表面を露
出させて半導体ウエハ10の電極端子形成面側を樹脂封
止することによって柱状電極付き半導体ウエハが得られ
る。
In the step of forming the plating film 41 in this embodiment, the conventional method of plating the copper plating portion 40 can be applied as it is, and the three layers of the nickel plating film 42, the palladium plating film 44 and the gold plating film 46 can be used. It is easy to stack plating layers. Thus, the semiconductor wafer 10
After the columnar electrode 24 is formed on the surface of the semiconductor wafer 10, the surface of the gold-plated coating formed on the top end surface of the columnar electrode 24 is exposed to seal the electrode terminal forming surface side of the semiconductor wafer 10 with resin, as shown in FIG. A semiconductor wafer with columnar electrodes is obtained.

【0025】なお、従来の柱状電極付き半導体ウエハに
設けられている柱状電極24は円柱状に形成されてい
る。図4(b) は従来の柱状電極24を拡大して示す斜視
図で、円柱状の柱状電極24が配線パターン22のパッ
ド部22a上に立設されている状態を示す。柱状電極付
き半導体ウエハは柱状電極24を形成した電極端子形成
面側が樹脂封止され、図1、2に示すように、隣接する
柱状電極24の間に樹脂28が充填される。ところが、
樹脂と金属とは一般的に密着性が良いとはいえないか
ら、柱状電極24にはんだボール等の実装用の外部接続
端子を接合した際に、柱状電極24の側面と樹脂28と
の界面にはんだが流れ込んだり、界面に水分が吸着され
たりする。
The columnar electrodes 24 provided on the conventional semiconductor wafer with columnar electrodes are formed in a columnar shape. FIG. 4B is an enlarged perspective view showing the conventional columnar electrode 24, showing a state where the columnar columnar electrode 24 is erected on the pad portion 22 a of the wiring pattern 22. The semiconductor wafer with columnar electrodes is resin-sealed on the electrode terminal formation surface side on which the columnar electrodes 24 are formed, and resin 28 is filled between the adjacent columnar electrodes 24, as shown in FIGS. However,
Generally, resin and metal do not have good adhesion, so that when the external connection terminal for mounting such as a solder ball is joined to the columnar electrode 24, the side surface of the columnar electrode 24 and the resin 28 are bonded to each other. Solder may flow in or moisture may be adsorbed at the interface.

【0026】この結果、柱状電極24に接合された外部
接続端子と柱状電極24との接合信頼性が低下するとい
う問題があった。図4(a) はこれらの問題を解消した柱
状電極24の形状を示すもので、柱状電極24の側面を
凹凸面形状とした例である。このように、柱状電極24
の側面を凹凸面に形成しておけば、柱状電極24の側面
と樹脂28との接触面積が増大し、柱状電極24の側面
での樹脂28と柱状電極24とのくいつき性が向上し、
柱状電極24の側面と樹脂28との密着性が改善され
る。
As a result, there is a problem in that the reliability of the connection between the external connection terminal joined to the columnar electrode 24 and the columnar electrode 24 is reduced. FIG. 4A shows the shape of the columnar electrode 24 that solves these problems, and is an example in which the side surface of the columnar electrode 24 has an uneven surface shape. In this way, the columnar electrode 24
If the side surface of the columnar electrode is formed into an uneven surface, the contact area between the side surface of the columnar electrode 24 and the resin 28 increases, and the clinging property between the resin 28 and the columnar electrode 24 on the side surface of the columnar electrode 24 improves.
Adhesion between the side surface of the columnar electrode 24 and the resin 28 is improved.

【0027】柱状電極24は図3で示したように、レジ
スト26に形成する開口穴26aの形状によって側面の
形状が規定されるから、レジスト26を開口穴26aの
形状にならって露光、現像する際に、開口穴26aの内
壁面が凹凸面になるように露光すればよい。開口穴26
aを適宜形状に形成することは容易である。そして、こ
のように柱状電極24の側面を凹凸形状に形成すること
により、柱状電極24と樹脂28との密着性が良好とな
り、柱状電極24にはんだボール等の外部接続端子を接
合した場合に柱状電極24の外側面と樹脂28との界面
にはんだが流れ込んだり、水分が侵入したりすることを
効果的に防止することができる。
As shown in FIG. 3, the columnar electrode 24 has its side surface defined by the shape of the opening hole 26a formed in the resist 26. Therefore, the resist 26 is exposed and developed according to the shape of the opening hole 26a. At this time, the exposure may be performed so that the inner wall surface of the opening hole 26a becomes an uneven surface. Opening hole 26
It is easy to form a into an appropriate shape. By forming the side surface of the columnar electrode 24 in a concavo-convex shape in this way, the adhesion between the columnar electrode 24 and the resin 28 becomes good, and when the columnar electrode 24 is joined to an external connection terminal such as a solder ball, the columnar electrode 24 is formed. It is possible to effectively prevent the solder from flowing into the interface between the outer surface of the electrode 24 and the resin 28 and the intrusion of water.

【0028】なお、柱状電極24と樹脂28との密着性
をさらに高めるために、柱状電極24を形成し、レジス
ト26を除去した後、プラズマアッシング等によって柱
状電極24の側面を粗面に形成することも有効である。
また、柱状電極24の側面を凹凸面あるいは粗面に形成
して樹脂28との密着性を向上させる形状に形成するこ
ととあわせて、前述したと同様に柱状電極24の頂部の
めっき被膜41の構成をニッケルめっき被膜42、パラ
ジウムめっき被膜44、金めっき被膜46の3層構造と
することも可能であり、これによってさらに信頼性の高
い半導体装置を得ることが可能となる。
In order to further improve the adhesion between the columnar electrode 24 and the resin 28, the columnar electrode 24 is formed, the resist 26 is removed, and then the side surface of the columnar electrode 24 is roughened by plasma ashing or the like. That is also effective.
Further, in addition to forming the side surface of the columnar electrode 24 into an uneven surface or a rough surface so as to improve the adhesion with the resin 28, the plating film 41 on the top of the columnar electrode 24 is formed in the same manner as described above. It is also possible to have a three-layer structure of a nickel plating film 42, a palladium plating film 44, and a gold plating film 46 in the configuration, and thereby a more reliable semiconductor device can be obtained.

【0029】[0029]

【発明の効果】本発明に係る柱状電極付き半導体ウエハ
は、上述したように、柱状電極に外部接続端子を接合す
る際のはんだ濡れ性が良好となり、はんだボール等の実
装用の外部接続端子と柱状電極とを確実に接合すること
が可能であり、これによって、信頼性の高い半導体装置
を製造することを可能にする。また、本発明に係る製造
方法によれば、信頼性の高い半導体装置を得るための柱
状電極付き半導体ウエハを好適に製造することができ
る。
As described above, the semiconductor wafer with the columnar electrode according to the present invention has good solder wettability when the external connection terminal is joined to the columnar electrode, and thus can be used as an external connection terminal for mounting a solder ball or the like. It is possible to reliably bond the columnar electrode, and this makes it possible to manufacture a highly reliable semiconductor device. Further, according to the manufacturing method of the present invention, it is possible to preferably manufacture a semiconductor wafer with columnar electrodes for obtaining a highly reliable semiconductor device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る柱状電極付き半導体ウエハの構成
を示す断面図である。
FIG. 1 is a sectional view showing a configuration of a semiconductor wafer with columnar electrodes according to the present invention.

【図2】本発明に係る柱状電極付き半導体ウエハの柱状
電極を拡大して示す断面図である。
FIG. 2 is an enlarged sectional view showing a columnar electrode of a semiconductor wafer with a columnar electrode according to the present invention.

【図3】本発明に係る柱状電極付き半導体ウエハの製造
方法を示す説明図である。
FIG. 3 is an explanatory view showing a method for manufacturing a semiconductor wafer with columnar electrodes according to the present invention.

【図4】柱状電極の他の形成例を示す斜視図である。FIG. 4 is a perspective view showing another example of forming columnar electrodes.

【図5】半導体ウエハを用いたチップサイズパッケージ
の製造で用いる柱状電極付き半導体ウエハの従来の製造
方法を示す説明図である。
FIG. 5 is an explanatory diagram showing a conventional method for manufacturing a semiconductor wafer with columnar electrodes used in manufacturing a chip size package using a semiconductor wafer.

【図6】半導体ウエハを用いたチップサイズパッケージ
の製造で用いる柱状電極付き半導体ウエハの製造方法を
示す説明図である。
FIG. 6 is an explanatory view showing a method of manufacturing a semiconductor wafer with columnar electrodes used in manufacturing a chip size package using a semiconductor wafer.

【符号の説明】[Explanation of symbols]

10 半導体ウエハ 12 電極 18 導体層 20 レジストパターン 22 配線パターン 24 柱状電極 26 レジスト 26a 開口穴 28 樹脂 30 封止用フィルム 40 銅めっき部 41 めっき被膜 42 ニッケルめっき被膜 44 パラジウムめっき被膜 46 金めっき被膜 10 Semiconductor wafer 12 electrodes 18 Conductor layer 20 resist pattern 22 wiring pattern 24 columnar electrodes 26 Resist 26a Open hole 28 resin 30 Sealing film 40 Copper plating part 41 plating film 42 Nickel plating film 44 Palladium plating film 46 gold plating film

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平10−287994(JP,A) (58)調査した分野(Int.Cl.7,DB名) H01L 21/288 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-10-287994 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 21/288

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 半導体ウエハの電極端子形成面に、一端
側が各電極端子に接続された配線パターンが絶縁層を介
して形成され、該各配線パターンの他端側に柱状電極が
形成され、該柱状電極の頂部端面を露出して樹脂封止さ
れた柱状電極付き半導体ウエハにおいて、 前記柱状電極の頂部端面に、ニッケルめっき被膜が形成
され、該ニッケルめっき被膜上にパラジウムめっき被膜
及び金めっき被膜が順次形成されていることを特徴とす
る柱状電極付き半導体ウエハ。
1. A wiring pattern having one end side connected to each electrode terminal is formed on an electrode terminal formation surface of a semiconductor wafer through an insulating layer, and a columnar electrode is formed on the other end side of each wiring pattern. In a semiconductor wafer with a columnar electrode in which the top end face of the columnar electrode is exposed and resin-sealed, a nickel plating film is formed on the top end face of the columnar electrode, and a palladium plating film and a gold plating film are formed on the nickel plating film. A semiconductor wafer with columnar electrodes, which is sequentially formed.
【請求項2】 パラジウムめっき被膜が0.1μm以下
の厚さに形成され、金めっき被膜が0.001μm〜
0.1μmの厚さに形成されていることを特徴とする請
求項1記載の柱状電極付き半導体ウエハ。
2. A palladium plating film having a thickness of 0.1 μm or less, and a gold plating film having a thickness of 0.001 μm or more.
The semiconductor wafer with columnar electrodes according to claim 1, wherein the semiconductor wafer has a thickness of 0.1 μm.
【請求項3】 パラジウムめっき被膜が0.05μm〜
0.1μmの厚さに形成され、金めっき被膜が0.01
μm〜0.05μmの厚さに形成されていることを特徴
とする請求項1記載の柱状電極付き半導体ウエハ。
3. The palladium plating film has a thickness of 0.05 μm or more.
Formed to a thickness of 0.1 μm, with a gold plating film of 0.01
The semiconductor wafer with a columnar electrode according to claim 1, wherein the semiconductor wafer has a thickness of μm to 0.05 μm.
【請求項4】 半導体ウエハの電極端子形成面を電極端
子を露出して絶縁層により被覆し、前記電極端子及び絶
縁層の表面に導体層を形成した後、導体層の表面にレジ
ストパターンを形成して前記導体層をめっき給電層とし
て銅めっきを施すことにより一端側が各電極端子に接続
する配線パターンを形成し、 前記レジストパターンを除去した後、前記導体層及び配
線パターンの表面にレジストを塗布し、配線パターンの
他端側の柱状電極を形成する部位のレジストに、底面に
配線パターンの他端側が露出する開口穴を形成し、 前記導体層をめっき給電層として前記開口穴内に銅めっ
きを施して、前記開口穴内に柱状電極を形成した後、該
柱状電極の頂部端面にニッケルめっき被膜を形成し、該
ニッケルめっき被膜上にパラジウムめっき被膜及び金め
っき被膜を順次形成し、 前記レジストを除去して、表面に露出する前記導体層を
除去した後、前記金めっき被膜の表面が露出するように
半導体ウエハの電極端子形成面側を樹脂封止することを
特徴とする柱状電極付き半導体ウエハの製造方法。
4. A surface of the semiconductor wafer on which the electrode terminals are formed is exposed to cover the electrode terminals with an insulating layer, a conductor layer is formed on the surfaces of the electrode terminals and the insulating layer, and then a resist pattern is formed on the surface of the conductor layer. Then, a wiring pattern whose one end side is connected to each electrode terminal is formed by performing copper plating using the conductor layer as a plating power supply layer, and after removing the resist pattern, a resist is applied to the surface of the conductor layer and the wiring pattern. Then, in the resist of the portion forming the columnar electrode on the other end side of the wiring pattern, an opening hole is formed on the bottom surface where the other end side of the wiring pattern is exposed, and copper plating is performed in the opening hole using the conductor layer as a plating power supply layer. After forming a columnar electrode in the opening, a nickel plating film is formed on the top end surface of the columnar electrode, and a palladium plating film and a nickel plating film are formed on the nickel plating film. A gold plating film is sequentially formed, the resist is removed, and the conductor layer exposed on the surface is removed, and then the electrode terminal formation surface side of the semiconductor wafer is resin-sealed so that the surface of the gold plating film is exposed. A method for manufacturing a semiconductor wafer with a columnar electrode, comprising:
JP01822999A 1999-01-27 1999-01-27 Semiconductor wafer with columnar electrode and method of manufacturing the same Expired - Fee Related JP3520213B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP01822999A JP3520213B2 (en) 1999-01-27 1999-01-27 Semiconductor wafer with columnar electrode and method of manufacturing the same
TW089101296A TW444288B (en) 1999-01-27 2000-01-26 Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device
KR1020000003629A KR100687548B1 (en) 1999-01-27 2000-01-26 Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device
EP00300613A EP1024531A3 (en) 1999-01-27 2000-01-27 Semiconductor wafer and device having columnar electrodes
US10/323,645 US7220657B2 (en) 1999-01-27 2002-12-20 Semiconductor wafer and semiconductor device provided with columnar electrodes and methods of producing the wafer and device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP01822999A JP3520213B2 (en) 1999-01-27 1999-01-27 Semiconductor wafer with columnar electrode and method of manufacturing the same

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JP3520213B2 true JP3520213B2 (en) 2004-04-19

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JP4653447B2 (en) 2004-09-09 2011-03-16 Okiセミコンダクタ株式会社 Manufacturing method of semiconductor device
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