WO2006109997A1 - Window manufacture method of semiconductor package type printed circuit board - Google Patents
Window manufacture method of semiconductor package type printed circuit board Download PDFInfo
- Publication number
- WO2006109997A1 WO2006109997A1 PCT/KR2006/001354 KR2006001354W WO2006109997A1 WO 2006109997 A1 WO2006109997 A1 WO 2006109997A1 KR 2006001354 W KR2006001354 W KR 2006001354W WO 2006109997 A1 WO2006109997 A1 WO 2006109997A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- masking
- bond finger
- solder
- circuit board
- printed circuit
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 title claims abstract description 21
- 238000007747 plating Methods 0.000 claims abstract description 51
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 42
- 229910000679 solder Inorganic materials 0.000 claims abstract description 27
- 239000010931 gold Substances 0.000 claims abstract description 23
- 229910052737 gold Inorganic materials 0.000 claims abstract description 23
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 21
- 238000003384 imaging method Methods 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 13
- 229910000906 Bronze Inorganic materials 0.000 claims abstract description 12
- 239000010974 bronze Substances 0.000 claims abstract description 12
- KUNSUQLRTQLHQQ-UHFFFAOYSA-N copper tin Chemical compound [Cu].[Sn] KUNSUQLRTQLHQQ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000009713 electroplating Methods 0.000 claims abstract description 6
- 238000003825 pressing Methods 0.000 claims abstract description 6
- 230000000873 masking effect Effects 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 13
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 238000003892 spreading Methods 0.000 claims description 11
- 238000004299 exfoliation Methods 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 18
- 230000000694 effects Effects 0.000 description 3
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/241—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
- H05K3/242—Reinforcing the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0166—Polymeric layer used for special processing, e.g. resist for etching insulating material or photoresist used as a mask during plasma etching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0044—Mechanical working of the substrate, e.g. drilling or punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
Definitions
- Window manufacture method of semiconductor package type printed circuit board of the present invention comprises an imaging step to expose to outer as pressing a dry film, excepts a bond finger part is formed in both sides of bronze coated circuit board, an etching step to be formed bond finger to get rid of bronze of exposed the imaging step, a strip step to eliminate the pressed dry film after formed bond finger in the etching step, a solder regist spread step to isolate all area except bond finger and solder boland to be formed by the strip step, a nickel/gold plating to be formed nickel/gold plating layer to do electroplating on exposed bond finger and solder boland in the solder regist spreading step, a masking spread step to support by masking plating line after plating in the nickel/gold plating step, a routing step to be formed improving shape and slot of a printed circuit board as to be centered masking plating line in the masking spread step, and a masking exfoliation step to eliminate spread masking in plating line after manufacturing a slot in the routing step.
- the present invention relates a window manufacture method of semiconductor package type printed circuit board, to be formed a circuit by an imaging, etching, and an exfoliation in a section, both sides, multi-layer product s upper and lower sides entire pressed board, to be formed an isolation layer in a part except bond finger and solder boland of the formed circuit, plating by a nickel/gold plating layer in the bond finger and solder boland through a lead wire for plating, after masking on the bond finger part for eliminating a metal burr which is happened when the lead wire for plating and window slot is manufactured, that is providing a window manufacture method of semiconductor package type printed circuit board of the present invention to be able to progress electronic noise and reliability by a metal burr as routing and exfoliation.
- Figure 1 is a flow chart view showing a manufacture method of semiconductor package type printed circuit board according to the prior art.
- the prior art comprised:
- an imaging step to be exposed to outside except a part to be formed a bond finger as pressing a dry film in both sides of coated board with bronze;
- a etching step to be formed a bond finger to eliminate bronze of exposed part to outside in the imaging step;
- solder regist spreading step to be isolated all area except formed bond finger and solder boland by the strip step
- a nickel/gold plating step to be formed a nickel/gold plating layer as performing electroplating in exposed bond finger and solder boland in the solder regist spreading step;
- BOC Board On Chip
- FBGA Fe Pitch Ball Grid Array
- metal burr (40) happened to be pushed a plating line of the bond finger (20) when a slot (30) was manufactured by routing method in case of non-plating other extra materials on the bond finger (20), the metal burr (40) could make contact or came close to bonding wire which was an electrical connection wire of a semiconductor chip, thus there was a problem that printed circuit board was failed due to shock as electronic noise if the metal burr (40) made contact with adjacent bond finger.
- An object of the present invention for overcoming the above-mentioned problems is to provide a window manufacture method of semiconductor package type printed circuit board to protect to be happened metal burr as supporting plating line of processing part by masking after nickel/gold plating for protecting that plating line is to be pushed situation to processing direction of a router when the router is processed after the nickel/gold plating in a manufacturing of printed circuit board to be used in a semiconductor package.
- the above-mentioned present invention has an effect to solve to be pushed situation by a router processing to protect not to be generated a gap in a slot to apply a separate masking on gold plating line to be arranged in a slot processing part for a metal burr to be generated when a slot is processed as indicating the above-mentioned method problem of the prior art, and also has an effect to reduce remarkably a failed rate of printed circuit board because it can be minimized electrical noise by the metal burr.
- Figure 1 is a flow chart view showing a manufacture method of semiconductor package type printed circuit board according to the prior art.
- Figure 2 is a routing step view showing in a manufacture method of semiconductor package type printed circuit board according to the prior art.
- Figure 3 is a flow chart view showing a manufacture method of semiconductor package type printed circuit board according to the present invention.
- Figure 4 is a masking spread step view showing in a manufacture method of semiconductor package type printed circuit board according to the present invention.
- Figure 5 is a masking exfoliation step view showing in a manufacture method of semiconductor package type printed circuit board according to the present invention. Best Mode for Carrying Out the Invention
- window manufacture method of semiconductor package type printed circuit board comprises:
- solder regist spreading step to be isolated all area except formed bond finger and solder boland by the strip step
- a nickel/gold plating step to be formed a nickel/gold plating layer as performing electroplating in exposed bond finger and solder boland in the solder regist spreading step;
- the present invention provides a manufacture method of semiconductor package type printed circuit board as not to be generated a metal burr, and to reduce electrical noise by a metal burr to be generated in window slot processing for a wire bonding of semiconductor chip and to eliminate plating lead line of wire bond finger of printed circuit board.
- an etching step to be formed a bond finger to eliminate bronze of exposed part to outside in the imaging step
- solder regist spreading step to be isolated all area except formed bond finger and solder boland by the strip step
- a nickel/gold plating step to be formed a nickel/gold plating layer as performing electroplating in exposed bond finger and solder boland in the solder regist spreading step;
- a masking exfoliation step to eliminate spread masking in plating line after manufacturing a slot in the routing step.
- Formation of a masking area in a masking spread step for the routing step is using exposure or phenomenon after a masking material spread, the masking spread material means for using material of a solid-state or a liquid-state.
- a shape of the printed circuit board and slot is processing to take a shape of a window slot (130) after spreading a masking (120) by center of the bond finger (100) and a plating line (110).
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Electroplating Methods And Accessories (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Wire Bonding (AREA)
Abstract
Window manufacture method of semiconductor package type printed circuit board of the present invention comprises an imaging step to expose to outer as pressing a dry film, excepts a bond finger part is formed in both sides of bronze coated circuit board, an etching step to be formed bond finger to get rid of bronze of exposed the imaging step, a strip step to eliminate the pressed dry film after formed bond finger in the etching step, a solder regist spread step to insulate all area except bond finger and solder boland to be formed by the strip step, a nickel/gold plating to be formed nickel/gold plating layer to do electroplating on exposed bond finger and solder boland in the solder regist spread step.
Description
Description
WINDOW MANUFACTURE METHOD OF SEMICONDUCTOR PACKAGE TYPE PRINTED CIRCUIT BOARD
Technical Field
[1] Window manufacture method of semiconductor package type printed circuit board of the present invention comprises an imaging step to expose to outer as pressing a dry film, excepts a bond finger part is formed in both sides of bronze coated circuit board, an etching step to be formed bond finger to get rid of bronze of exposed the imaging step, a strip step to eliminate the pressed dry film after formed bond finger in the etching step, a solder regist spread step to isolate all area except bond finger and solder boland to be formed by the strip step, a nickel/gold plating to be formed nickel/gold plating layer to do electroplating on exposed bond finger and solder boland in the solder regist spreading step, a masking spread step to support by masking plating line after plating in the nickel/gold plating step, a routing step to be formed improving shape and slot of a printed circuit board as to be centered masking plating line in the masking spread step, and a masking exfoliation step to eliminate spread masking in plating line after manufacturing a slot in the routing step. Background Art
[2] The present invention relates a window manufacture method of semiconductor package type printed circuit board, to be formed a circuit by an imaging, etching, and an exfoliation in a section, both sides, multi-layer product s upper and lower sides entire pressed board, to be formed an isolation layer in a part except bond finger and solder boland of the formed circuit, plating by a nickel/gold plating layer in the bond finger and solder boland through a lead wire for plating, after masking on the bond finger part for eliminating a metal burr which is happened when the lead wire for plating and window slot is manufactured, that is providing a window manufacture method of semiconductor package type printed circuit board of the present invention to be able to progress electronic noise and reliability by a metal burr as routing and exfoliation.
Disclosure of Invention Technical Problem
[3] Figure 1 is a flow chart view showing a manufacture method of semiconductor package type printed circuit board according to the prior art. As Figure 1, the prior art comprised:
[4] an imaging step to be exposed to outside except a part to be formed a bond finger as pressing a dry film in both sides of coated board with bronze;
[5] a etching step to be formed a bond finger to eliminate bronze of exposed part to outside in the imaging step;
[6] a strip step to get rid of the pressed dry film after as formed a bond finger in the etching step;
[7] a solder regist spreading step to be isolated all area except formed bond finger and solder boland by the strip step;
[8] a nickel/gold plating step to be formed a nickel/gold plating layer as performing electroplating in exposed bond finger and solder boland in the solder regist spreading step; and
[9] a routing step to be formed to manufacture a shape and slot of printed circuit board after plating in the nickel/gold plating step.
[10]
[11] Through the method as mentioned above, manufactured semiconductor package
BOC (Board On Chip) or FBGA (Fine Pitch Ball Grid Array) board was that wire- bonding area arranged a center of package, and a plating line for gold plating in wire bond finger arranged a center. However, as Figure 2, metal burr (40) happened to be pushed a plating line of the bond finger (20) when a slot (30) was manufactured by routing method in case of non-plating other extra materials on the bond finger (20), the metal burr (40) could make contact or came close to bonding wire which was an electrical connection wire of a semiconductor chip, thus there was a problem that printed circuit board was failed due to shock as electronic noise if the metal burr (40) made contact with adjacent bond finger. Technical Solution
[12] An object of the present invention for overcoming the above-mentioned problems is to provide a window manufacture method of semiconductor package type printed circuit board to protect to be happened metal burr as supporting plating line of processing part by masking after nickel/gold plating for protecting that plating line is to be pushed situation to processing direction of a router when the router is processed after the nickel/gold plating in a manufacturing of printed circuit board to be used in a semiconductor package. Advantageous Effects
[13] The above-mentioned present invention has an effect to solve to be pushed situation by a router processing to protect not to be generated a gap in a slot to apply a separate masking on gold plating line to be arranged in a slot processing part for a metal burr to be generated when a slot is processed as indicating the above-mentioned method problem of the prior art, and also has an effect to reduce remarkably a failed rate of printed circuit board because it can be minimized electrical noise by the metal burr.
[14]
Brief Description of the Drawings
[15] The present invention will become better understand with reference to accompanying drawings which are given only by way of illustration and thus are not limitative of the present invention, wherein;
[16] Figure 1 is a flow chart view showing a manufacture method of semiconductor package type printed circuit board according to the prior art.
[17] Figure 2 is a routing step view showing in a manufacture method of semiconductor package type printed circuit board according to the prior art.
[18] Figure 3 is a flow chart view showing a manufacture method of semiconductor package type printed circuit board according to the present invention.
[19] Figure 4 is a masking spread step view showing in a manufacture method of semiconductor package type printed circuit board according to the present invention.
[20] Figure 5 is a masking exfoliation step view showing in a manufacture method of semiconductor package type printed circuit board according to the present invention. Best Mode for Carrying Out the Invention
[21] In a manufacture method of semiconductor package type printed circuit board as not to be generated a metal burr, window manufacture method of semiconductor package type printed circuit board comprises:
[22] an imaging step to be exposed to outside except a part to be formed a bond finger as pressing a dry film in both sides of coated board with bronze;
[23] an etching step to be formed a bond finger to eliminate bronze of exposed part to outside in the imaging step;
[24] a strip step to get rid of the pressed dry film after as formed a bond finger in the etching step;
[25] a solder regist spreading step to be isolated all area except formed bond finger and solder boland by the strip step;
[26] a nickel/gold plating step to be formed a nickel/gold plating layer as performing electroplating in exposed bond finger and solder boland in the solder regist spreading step;
[27] a masking spread step to support plating line by a masking after plating in the nickel/gold plating step; and
[28] a routing step to be formed to manufacture a shape and slot of printed circuit board after plating in the masking spread step.
[29] a masking exfoliation step to eliminate spread masking in plating line after manufacturing a slot in the routing step. Mode for the Invention
[30] The present invention provides a manufacture method of semiconductor package type printed circuit board as not to be generated a metal burr, and to reduce electrical noise by a metal burr to be generated in window slot processing for a wire bonding of semiconductor chip and to eliminate plating lead line of wire bond finger of printed circuit board.
[31]
[32] As Figure 3 for achievement of the purposes, the present invention comprises that
[33] an imaging step to be exposed to outside except a part to be formed a bond finger as pressing a dry film in both sides of coated board with bronze;
[34] an etching step to be formed a bond finger to eliminate bronze of exposed part to outside in the imaging step;
[35] a strip step to get rid of the pressed dry film after as formed a bond finger in the etching step;
[36] a solder regist spreading step to be isolated all area except formed bond finger and solder boland by the strip step;
[37] a nickel/gold plating step to be formed a nickel/gold plating layer as performing electroplating in exposed bond finger and solder boland in the solder regist spreading step;
[38] a masking spread step to support plating line by a masking after plating in the nickel/gold plating step; and
[39] a routing step to be formed to manufacture a shape and slot of printed circuit board after plating in the masking spread step.
[40] a masking exfoliation step to eliminate spread masking in plating line after manufacturing a slot in the routing step.
[41]
[42] Formation of a masking area in a masking spread step for the routing step is using exposure or phenomenon after a masking material spread, the masking spread material means for using material of a solid-state or a liquid-state.
[43]
[44] In more detail explanation about embodiment of window manufacture method of semiconductor package type printed circuit board according to the present invention through Figure 4 as follows:
[45] If a printed circuit board is completed as formed bond finger (100) and solder boland in the imaging step to nickel/gold plating step, a shape of the printed circuit board and slot is processing to take a shape of a window slot (130) after spreading a masking (120) by center of the bond finger (100) and a plating line (110).
[46]
[47] As showing in Figure 5, masking which is spread a window slot (130) after the
routing processing, is eliminated, a printed circuit board is completed as not to be generated a metal burr if spread masking (120) of around bond finger (100) is removed.
[48]
[49] The present invention is not limited to the above embodiment. As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described examples are not limited by any of the details of the foregoing description, unless otherwise specified, but rather should be constructed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.
Claims
Claims
[1] A window manufacture method of semiconductor package type printed circuit board as not to be generated a metal burr, comprising: an imaging step in which exposes to outside except a part to be formed a bond finger as pressing a dry film in both sides of coated board with bronze; an etching step in which is formed a bond finger to eliminate bronze of exposed part to outside in the imaging step; a strip step in which gets rid of the pressed dry film after making a bond finger in the etching step; a solder regist spreading step in which is isolated all area except formed bond finger and solder boland by the strip step; a nickel/gold plating step in which is formed a nickel/gold plating layer as performing electroplating in an exposed bond finger and solder boland in the solder regist spreading step; a masking spread step in which supports plating line as in a formation of area by a masking after plating in the nickel/gold plating step; and a routing step in which is formed to manufacture a shape and slot of printed circuit board after plating in the masking spread step. a masking exfoliation step in which eliminates spread masking in plating line after manufacturing a slot in the routing step. [2] As in claim 1, wherein said formation of area to support plating line in the masking spread step for the routing step means for using exposure or developing after spreading a masking material. [3] As in claim 1, wherein said masking in the masking spread step means for using material of a solid-state or a liquid-state.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007532258A JP4701248B2 (en) | 2005-04-12 | 2006-04-12 | Slot processing method for printed circuit board for semiconductor package |
| TW095135043A TWI333265B (en) | 2005-04-12 | 2006-09-22 | Window manufacture method of semiconductor package type printed circuit board |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2005-0030136 | 2005-04-12 | ||
| KR1020050030136A KR100648916B1 (en) | 2005-04-12 | 2005-04-12 | Window manufacture method of semiconductor package type printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2006109997A1 true WO2006109997A1 (en) | 2006-10-19 |
Family
ID=37087238
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/KR2006/001307 WO2006109967A2 (en) | 2005-04-12 | 2006-04-10 | Window manufacture method of semiconductor package type printed circuit board |
| PCT/KR2006/001354 WO2006109997A1 (en) | 2005-04-12 | 2006-04-12 | Window manufacture method of semiconductor package type printed circuit board |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/KR2006/001307 WO2006109967A2 (en) | 2005-04-12 | 2006-04-10 | Window manufacture method of semiconductor package type printed circuit board |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JP4701248B2 (en) |
| KR (1) | KR100648916B1 (en) |
| CN (1) | CN100514612C (en) |
| TW (1) | TWI333265B (en) |
| WO (2) | WO2006109967A2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100891334B1 (en) | 2007-05-25 | 2009-03-31 | 삼성전자주식회사 | Circuit board, semiconductor package having the board, and methods of fabricating the circuit board and the semiconductor package |
| TWI334320B (en) | 2007-07-16 | 2010-12-01 | Nanya Technology Corp | Fabricating method of gold finger of circuit board |
| CN101488486B (en) * | 2008-01-15 | 2010-06-02 | 力成科技股份有限公司 | Circuit substrate capable of opening slots |
| KR100941982B1 (en) * | 2008-04-07 | 2010-02-11 | 삼성전기주식회사 | Manufacturing method of board on chip package substrate |
| CN102480844B (en) * | 2010-11-23 | 2014-05-07 | 深南电路有限公司 | Process for manufacturing diffusion coating prevention PCB (printed circuit board) gold-plated board |
| CN108513433A (en) * | 2018-04-24 | 2018-09-07 | 苏州维信电子有限公司 | A kind of flexible circuit board PAD and its manufacturing method every tin |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5281851A (en) * | 1992-10-02 | 1994-01-25 | Hewlett-Packard Company | Integrated circuit packaging with reinforced leads |
| US5677571A (en) * | 1991-11-12 | 1997-10-14 | Kabushiki Kaisha Toshiba | Semiconductor package having reinforced lead pins |
| KR20020085635A (en) * | 2001-05-09 | 2002-11-16 | 주식회사 심텍 | Routing method of the outside of a castle type printed circuit board |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3415089B2 (en) * | 1999-03-01 | 2003-06-09 | 住友金属鉱山株式会社 | Manufacturing method of printed wiring board |
| JP2001110838A (en) * | 1999-10-07 | 2001-04-20 | Hitachi Chem Co Ltd | Semiconductor device, semiconductor support substrate which is used for that and manufacturing method of semiconductor device |
| JP2002299790A (en) * | 2001-03-30 | 2002-10-11 | Ibiden Co Ltd | Router processing method and router processed substrate |
| KR100617585B1 (en) * | 2004-01-28 | 2006-09-01 | 주식회사 뉴프렉스 | Method for manufacturing a flexible printed circuit board |
-
2005
- 2005-04-12 KR KR1020050030136A patent/KR100648916B1/en active IP Right Grant
-
2006
- 2006-04-10 WO PCT/KR2006/001307 patent/WO2006109967A2/en unknown
- 2006-04-12 WO PCT/KR2006/001354 patent/WO2006109997A1/en active Application Filing
- 2006-04-12 JP JP2007532258A patent/JP4701248B2/en active Active
- 2006-04-12 CN CNB2006800001281A patent/CN100514612C/en active Active
- 2006-09-22 TW TW095135043A patent/TWI333265B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5677571A (en) * | 1991-11-12 | 1997-10-14 | Kabushiki Kaisha Toshiba | Semiconductor package having reinforced lead pins |
| US5281851A (en) * | 1992-10-02 | 1994-01-25 | Hewlett-Packard Company | Integrated circuit packaging with reinforced leads |
| KR20020085635A (en) * | 2001-05-09 | 2002-11-16 | 주식회사 심텍 | Routing method of the outside of a castle type printed circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2006109967A2 (en) | 2006-10-19 |
| CN100514612C (en) | 2009-07-15 |
| KR100648916B1 (en) | 2006-11-27 |
| JP2008519426A (en) | 2008-06-05 |
| CN1989612A (en) | 2007-06-27 |
| TWI333265B (en) | 2010-11-11 |
| JP4701248B2 (en) | 2011-06-15 |
| KR20060108045A (en) | 2006-10-17 |
| TW200816407A (en) | 2008-04-01 |
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