KR100941982B1 - Manufacturing method of board on chip package substrate - Google Patents

Manufacturing method of board on chip package substrate Download PDF

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Publication number
KR100941982B1
KR100941982B1 KR1020080032062A KR20080032062A KR100941982B1 KR 100941982 B1 KR100941982 B1 KR 100941982B1 KR 1020080032062 A KR1020080032062 A KR 1020080032062A KR 20080032062 A KR20080032062 A KR 20080032062A KR 100941982 B1 KR100941982 B1 KR 100941982B1
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South Korea
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forming
solder ball
wire bonding
pad
insulating substrate
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KR1020080032062A
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Korean (ko)
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KR20090106741A (en
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김동헌
윤상미
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삼성전기주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/043—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having a conductive base as a mounting as well as a lead for the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

보드온칩(BOC, board on chip) 패키지 기판 제조방법이 개시된다. 절연기판의 일면에 와이어본딩 패드와 솔더볼 패드 및 도금인입선을 형성하는 단계; 와이어본딩 패드와 솔더볼 패드 및 도금인입선에 상응하는 개구부가 형성된 솔더레지스트를 절연기판의 일면에 형성하는 단계; 와이어본딩 패드와 솔더볼 패드의 표면에 표면처리층을 형성하는 단계; 잉크젯 방식을 이용하여, 도금인입선의 표면에 포토레지스트 잉크를 선택적으로 도포하는 단계; 및 포토레지스트 잉크가 도포된 영역을 가공하여, 절연기판을 관통하는 윈도우를 형성하는 단계를 포함하는 보드온칩 패키지 기판 제조방법은, 포토레지스트 잉크를 가공 부위에만 국소적으로 인쇄한 후 윈도우를 형성함으로써, 버어의 발생을 효율적으로 줄일 수 있다.A method of manufacturing a board on chip (BOC) package substrate is disclosed. Forming a wire bonding pad, a solder ball pad, and a plating lead on one surface of the insulating substrate; Forming a solder resist having an opening corresponding to the wire bonding pad, the solder ball pad, and the plating lead on one surface of the insulating substrate; Forming a surface treatment layer on surfaces of the wire bonding pad and the solder ball pad; Selectively applying photoresist ink on the surface of the plating lead wire using an inkjet method; And processing the region to which the photoresist ink is applied to form a window penetrating the insulating substrate. The method of manufacturing a board-on-chip package substrate includes forming a window after locally printing the photoresist ink only on the processed portion. In addition, the occurrence of burrs can be efficiently reduced.

보드온칩, BOC, 잉크젯, 포토레지스트 잉크 Board-on-Chip, BOC, Inkjet, Photoresist Ink

Description

보드온칩 패키지 기판 제조방법{Manufacturing method of board on chip package substrate}Manufacturing method of board on chip package substrate

본 발명은 보드온칩 패키지 기판 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a board-on-chip package substrate.

최근 반도체 기술은 급속도로 집적 회로의 고속도화 및 고밀도화 되어 가고 있다. 이에 따라, 집적 회로간의 전반적인 신호전달 시간을 단축할 필요성이 제기되어서, 집적 회로간의 신호 경로를 단축시키는 기술이 요구되었다. 이러한 요구에 부응하는 하나의 방안으로, 보드온칩(BOC, board on chip) 패키지가 제안되었다.Recently, semiconductor technology is rapidly increasing the speed and density of integrated circuits. Accordingly, there is a need to shorten the overall signal transfer time between integrated circuits, and a technique for shortening the signal path between integrated circuits is required. As a solution to this demand, a board on chip (BOC) package has been proposed.

도 1 내지 도 5는 종래기술에 따른 보드온칩 패키지 기판 제조방법을 나타내는 흐름도이다. 도 1 내지 도 5를 참조하면, 절연기판(11), 회로패턴(12), 와이어본딩 패드(12b), 도금인입선(12c), 솔더볼 패드(12a), 솔더레지스트(13), 도금층(14), 윈도우(15), 버어(burr, 16), 라우터 비트(router bit, 20)가 도시되어 있다.1 to 5 are flowcharts illustrating a method for manufacturing a board-on-chip package substrate according to the prior art. 1 to 5, the insulating substrate 11, the circuit pattern 12, the wire bonding pad 12b, the plating lead wire 12c, the solder ball pad 12a, the solder resist 13, and the plating layer 14 are described. The window 15, burr 16, and router bit 20 are shown.

종래기술에 따르면, 도 1에 도시된 바와 같이, 절연기판(11)에 솔더볼 패 드(12a), 와이어본딩 패드(12b) 및 도금인입선(12c)을 형성하고, 그 다음, 도 2에 도시된 바와 같이, 그 위에 솔더레지스트(solder resist, 13)을 형성한다.According to the prior art, as shown in FIG. 1, a solder ball pad 12a, a wire bonding pad 12b, and a plating lead wire 12c are formed on the insulating substrate 11, and then, as shown in FIG. As such, a solder resist 13 is formed thereon.

그리고 나서, 도 3에 도시된 바와 같이, 도금인입선(12a), 와이어본딩 패드(12b) 및 솔더볼 패드(12a)와 같이 노출된 부분에 Ni/Au 도금층(14)을 형성한다.Then, as shown in FIG. 3, the Ni / Au plating layer 14 is formed on exposed portions such as the plating lead wire 12a, the wire bonding pad 12b, and the solder ball pad 12a.

이 후, 도 4 및 도 5에 도시된 바와 같이, 라우터 비트(20)를 사용하여 절연기판(11)의 중앙부에 위치한 도금인입선(12a)을 절단함으로써 와이어본딩을 위한 윈도우(15)를 형성한다.Thereafter, as shown in FIGS. 4 and 5, the router bit 20 is used to cut the plating lead wire 12a positioned at the center of the insulating substrate 11 to form a window 15 for wire bonding. .

그러나, 이러한 종래기술에 따르면, 도 5에 도시된 바와 같이, 라우터 비트(20)를 이용하여 윈도우(15)를 형성하는 과정에서 회전절삭 공구의 가열로 인하여 절삭면에 도금인입선(12a)의 금속 버어(burr, 16)가 발생하는 문제점이 있었다.However, according to this prior art, as shown in FIG. 5, the metal of the plating lead wire 12a on the cutting surface due to the heating of the rotary cutting tool in the process of forming the window 15 using the router bit 20. Burr (16) was a problem that occurs.

이러한 금속 버어(burr, 16)는 인접한 와이어본딩 패드(12b)간을 연결하여 제품의 불량을 발생시키는 심각한 문제점이 되었다.The metal burr 16 has become a serious problem of connecting the adjacent wire bonding pads 12b to cause product defects.

본 발명은 윈도우 가공 시 버어의 발생을 효율적으로 줄일 수 있는 보드온칩 패키지 기판 제조방법을 제공하는 것이다.The present invention is to provide a board-on-chip package substrate manufacturing method that can efficiently reduce the occurrence of burrs during window processing.

본 발명의 일 측면에 따르면, 절연기판의 일면에 와이어본딩 패드와 솔더볼 패드 및 도금인입선을 형성하는 단계; 와이어본딩 패드와 솔더볼 패드 및 도금인입 선에 상응하는 개구부가 형성된 솔더레지스트를 절연기판의 일면에 형성하는 단계; 와이어본딩 패드와 솔더볼 패드의 표면에 표면처리층을 형성하는 단계; 잉크젯 방식을 이용하여, 도금인입선의 표면에 포토레지스트 잉크를 선택적으로 도포하는 단계; 및 포토레지스트 잉크가 도포된 영역을 가공하여, 절연기판을 관통하는 윈도우를 형성하는 단계를 포함하는 보드온칩 패키지 기판 제조방법을 제공할 수 있다.According to an aspect of the invention, forming a wire bonding pad and a solder ball pad and a plating lead on one surface of the insulating substrate; Forming a solder resist having an opening corresponding to the wire bonding pad, the solder ball pad, and the plating lead on one surface of the insulating substrate; Forming a surface treatment layer on surfaces of the wire bonding pad and the solder ball pad; Selectively applying photoresist ink on the surface of the plating lead wire using an inkjet method; And processing the region to which the photoresist ink is applied to form a window penetrating the insulating substrate.

윈도우를 형성하는 단계 이후에, 솔더볼 패드에 솔더볼을 형성하는 단계; 절연기판의 타면에 칩을 부착하는 단계; 및 윈도우를 통하여, 칩과 와이어본딩 패드를 와이어본딩 하는 단계를 더 수행할 수 있다.After forming the window, forming solder balls on the solder ball pads; Attaching a chip to the other surface of the insulating substrate; And wire bonding the chip and the wire bonding pad through the window.

한편, 표면처리층을 형성하는 단계는, 도금인입선의 상면에 도금레지스트를 형성하는 단계; 및 전해도금을 통하여 와이어본딩 패드와 솔더볼 패드에 도금층을 형성하는 단계를 포함할 수 있다.On the other hand, forming the surface treatment layer, forming a plating resist on the upper surface of the plating lead wire; And forming a plating layer on the wire bonding pad and the solder ball pad through electroplating.

윈도우를 형성하는 단계는 라우팅 비트를 이용하여 수행될 수 있다.Forming the window may be performed using routing bits.

본 발명의 바람직한 실시예에 따르면, 포토레지스트 잉크를 가공 부위에만 국소적으로 인쇄한 후 윈도우를 형성함으로써, 버어의 발생을 효율적으로 줄일 수 있다. According to a preferred embodiment of the present invention, by locally printing the photoresist ink only on the processing site and forming a window, it is possible to efficiently reduce the occurrence of burr.

본 발명은 다양한 변환을 가할 수 있고 여러 가지 실시예를 가질 수 있는 바, 특정 실시예들을 도면에 예시하고 상세한 설명에 상세하게 설명하고자 한다. 그러나, 이는 본 발명을 특정한 실시 형태에 대해 한정하려는 것이 아니며, 본 발명의 사상 및 기술 범위에 포함되는 모든 변환, 균등물 내지 대체물을 포함하는 것으로 이해되어야 한다. 본 발명을 설명함에 있어서 관련된 공지 기술에 대한 구체적인 설명이 본 발명의 요지를 흐릴 수 있다고 판단되는 경우 그 상세한 설명을 생략한다.As the invention allows for various changes and numerous embodiments, particular embodiments will be illustrated in the drawings and described in detail in the written description. However, this is not intended to limit the present invention to specific embodiments, it should be understood to include all transformations, equivalents, and substitutes included in the spirit and scope of the present invention. In the following description of the present invention, if it is determined that the detailed description of the related known technology may obscure the gist of the present invention, the detailed description thereof will be omitted.

본 출원에서 사용한 용어는 단지 특정한 실시예를 설명하기 위해 사용된 것으로, 본 발명을 한정하려는 의도가 아니다. 단수의 표현은 문맥상 명백하게 다르게 뜻하지 않는 한, 복수의 표현을 포함한다. 본 출원에서, "포함하다" 또는 "가지다" 등의 용어는 명세서상에 기재된 특징, 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것이 존재함을 지정하려는 것이지, 하나 또는 그 이상의 다른 특징들이나 숫자, 단계, 동작, 구성요소, 부품 또는 이들을 조합한 것들의 존재 또는 부가 가능성을 미리 배제하지 않는 것으로 이해되어야 한다.The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the present invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this application, the terms "comprise" or "have" are intended to indicate that there is a feature, number, step, operation, component, part, or combination thereof described in the specification, and one or more other features. It is to be understood that the present invention does not exclude the possibility of the presence or the addition of numbers, steps, operations, components, components, or a combination thereof.

이하, 본 발명에 따른 보드온칩 패키지 기판의 바람직한 실시예를 첨부도면을 참조하여 상세히 설명하기로 하며, 첨부 도면을 참조하여 설명함에 있어, 동일하거나 대응하는 구성 요소는 동일한 도면번호를 부여하고 이에 대한 중복되는 설명은 생략하기로 한다.Hereinafter, a preferred embodiment of a board-on-chip package substrate according to the present invention will be described in detail with reference to the accompanying drawings, in the description with reference to the accompanying drawings, the same or corresponding components are given the same reference numerals and Duplicate explanations will be omitted.

도 6은 본 발명의 일 실시예에 따른 보드온칩 패키지 기판 제조방법을 나타내는 순서도이고, 도 7 내지 도 14는 본 발명의 일 실시예에 따른 보드온칩 패키지 기판 제조방법을 나타내는 흐름도이다. 도 7 내지 도 14를 참조하면, 절연기 판(110), 회로패턴(120), 와이어본딩 패드(121), 솔더볼 패드(122), 도금인입선(123), 솔더레지스트(130), 도금레지스트(140), 표면처리층(150), 윈도우(160), 솔더볼(170), 잉크젯 헤드(200), 포토레지스트 잉크(210), 라우터 비트(230), 칩(300), 접착층(310), 와이어(320), 인캡슐레이션부(330)가 도시되어 있다.6 is a flowchart illustrating a method for manufacturing a board-on-chip package substrate according to an embodiment of the present invention, and FIGS. 7 to 14 are flowcharts illustrating a method for manufacturing a board-on-chip package substrate according to an embodiment of the present invention. 7 to 14, the insulator plate 110, the circuit pattern 120, the wire bonding pad 121, the solder ball pad 122, the plating lead wire 123, the solder resist 130, and the plating resist ( 140, surface treatment layer 150, window 160, solder ball 170, inkjet head 200, photoresist ink 210, router bit 230, chip 300, adhesive layer 310, wire 320, encapsulation 330 is shown.

먼저, 도 7에 도시된 바와 같이, 절연기판(110)의 일면에 와이어본딩 패드(121)와 솔더볼 패드(122) 및 도금인입선(123)을 형성한다(S10). 와이어본딩 패드(121)는 추후에 실장되는 칩(300)과의 전기적인 접속을 위한 것이며, 솔더볼 패드(122)는 별도의 마더보드(mother board) 등과의 전기적인 접속을 위해 솔더볼(170)이 안착되는 곳이다. 또한, 도금인입선(123)은 와이어본딩 패드(121)와 솔더볼 패드(122)에 전해도금을 수행하기 위한 전극으로 이용될 수 있는 것이다. 이 밖에, 도면에는 도시되지는 않았으나, 전기신호의 흐름을 위한 다양한 배선패턴들이 함께 형성될 수 있음은 물론이다.First, as shown in FIG. 7, the wire bonding pad 121, the solder ball pad 122, and the plating lead wire 123 are formed on one surface of the insulating substrate 110 (S10). The wire bonding pad 121 is for electrical connection with the chip 300 to be mounted later, and the solder ball pad 122 has a solder ball 170 for electrical connection with a separate motherboard. It is a place to rest. In addition, the plating lead wire 123 may be used as an electrode for performing electroplating on the wire bonding pad 121 and the solder ball pad 122. In addition, although not shown in the drawings, various wiring patterns for the flow of the electric signal may be formed together.

이러한 와이어본딩 패드(121), 솔더볼 패드(122), 도금인입선(123) 등을 형성하는 방법으로, 절연기판(110)에 적층된 금속층의 일부를 식각하는 서브트랙티브(subtractive) 공법을 이용할 수 있으며, 무전해 도금과 전해도금을 이용하는 에디티브(additive) 공법을 이용할 수도 있다. 이 외에도 다양한 방법을 이용할 수 있음은 물론이다.As a method of forming the wire bonding pad 121, the solder ball pad 122, the plating lead wire 123, and the like, a subtractive method of etching a part of the metal layer laminated on the insulating substrate 110 may be used. In addition, an additive method using electroless plating and electroplating may be used. In addition, various methods can be used.

그리고 나서, 도 8에 도시된 바와 같이, 와이어본딩 패드(121)와 솔더볼 패드(122) 및 도금인입선(123)에 상응하는 개구부가 형성된 솔더레지스트(130)를 절연기판(110)의 일면에 형성한다(S20). 솔더레지스트(130)는 절연기판(110)에 형성 된 각종 패턴들을 보호하는 기능을 수행할 수 있다. 다만, 제조공정 상에 있어서 외부와의 접속을 위해 노출되어야 할 필요가 있는 부분에는 개구부가 형성될 수 있다. 도 8에는 와이어본딩 패드(121)와 솔더볼 패드(122) 및 도금인입선(123)이 노출되어 있는 모습이 도시되어 있다.Then, as shown in FIG. 8, a solder resist 130 having an opening corresponding to the wire bonding pad 121, the solder ball pad 122, and the plating lead line 123 is formed on one surface of the insulating substrate 110. (S20). The solder resist 130 may function to protect various patterns formed on the insulating substrate 110. However, an opening may be formed in a portion that needs to be exposed for connection to the outside in the manufacturing process. 8 illustrates the wire bonding pad 121, the solder ball pad 122, and the plating lead wire 123 being exposed.

그리고 나서, 와이어본딩 패드(121)와 솔더볼 패드(122)의 표면에 표면처리층(150)을 형성한다(S30). 표면처리층(150)은 와이어본딩 패드(121)와 솔더볼 패드(122)의 표면을 보호함과 동시에 전기적인 접속력을 확보할 수 있도록 하는 기능을 수행할 수 있다.Then, the surface treatment layer 150 is formed on the surfaces of the wire bonding pad 121 and the solder ball pad 122 (S30). The surface treatment layer 150 may perform a function of protecting the surfaces of the wire bonding pad 121 and the solder ball pad 122 and at the same time ensuring electrical connection force.

이러한 표면처리층(150)을 형성하기 위하여, 도 9에 도시된 바와 같이 도금인입선(123)의 상면에 도금레지스트(140)를 형성한 다음(S31), 도 10에 도시된 바와 같이, 전해도금을 통하여 와이어본딩 패드(121)와 솔더볼 패드(122)에 도금층을 형성하는 방법을 이용할 수 있다. 물론, 전해도금이 완료된 다음에는 도금인입선(123)의 상면에 형성되었던 도금레지스트(140)를 제거할 수 있다. 도금층은 니켈/금 도금층일 수 있으며, 그 밖의 물질이 이용될 수도 있음은 물론이다.In order to form the surface treatment layer 150, as shown in FIG. 9, a plating resist 140 is formed on the upper surface of the plating lead wire 123 (S31), and as shown in FIG. 10, electroplating. A method of forming a plating layer on the wire bonding pad 121 and the solder ball pad 122 may be used. Of course, after the electroplating is completed, the plating resist 140 formed on the upper surface of the plating lead wire 123 may be removed. The plating layer may be a nickel / gold plating layer, and other materials may be used.

이렇게 표면처리층(150)을 형성한 다음, 도 11에 도시된 바와 같이, 잉크젯 방식을 이용하여, 도금인입선(123)의 표면에 포토레지스트 잉크(210)를 선택적으로 도포하고(S40), 도 12에 도시된 바와 같이, 포토레지스트 잉크(210)가 도포된 영역을 가공하여, 절연기판(110)을 관통하는 윈도우(160)를 형성한다(S50).After forming the surface treatment layer 150, as shown in FIG. 11, the photoresist ink 210 is selectively coated on the surface of the plating lead wire 123 using an inkjet method (S40). As shown in FIG. 12, the region coated with the photoresist ink 210 is processed to form a window 160 penetrating the insulating substrate 110 (S50).

즉, 라우터 비트(230) 등을 이용한 기계적인 가공이 수행되는 영역에 포토레지스트 잉크(210)를 도포한 다음에 가공을 수행하는 것이다. 이러한 방법을 통하여 금속 버어가 형성되는 현상을 줄일 수 있게 된다. 가공을 수행하기에 앞서 도포된 포토레지스트 잉크(210)를 경화시킬 수도 있음은 물론이다.That is, the photoresist ink 210 is applied to an area where mechanical processing using the router bit 230 is performed, and then processing is performed. Through this method it is possible to reduce the phenomenon that the metal burr is formed. Of course, the applied photoresist ink 210 may be cured prior to performing the processing.

또한, 잉크젯 방식을 이용하여 포토레지스트 잉크(210)를 가공 부위에만 국소적으로 인쇄할 수 있어, 포토레지스트 잉크(210)의 사용량을 줄일 수 있을 뿐만 아니라 공정을 간략화 할 수도 있게 된다.In addition, the inkjet method may locally print the photoresist ink 210 only at the processing site, thereby reducing the amount of photoresist ink 210 used and simplifying the process.

한편, 도 12에 도시된 바와 같이, 윈도우(160) 가공 후 포토레지스트 잉크(210)의 일부가 잔존하는 경우, 에칭액 등을 이용하여 잔존 부분을 제거할 수 있다. 이러한 공정을 거쳐 윈도우(160)가 형성된 모습이 도 13에 도시되어 있다.12, when a part of the photoresist ink 210 remains after the window 160 is processed, the remaining part may be removed using an etching solution or the like. 13 shows the window 160 formed through such a process.

그리고 나서, 도 14에 도시된 바와 같이, 솔더볼 패드(122)에 솔더볼(170)을 형성하고(S60), 절연기판(110)의 타면에 칩(300)을 부착한 다음(S70), 윈도우(160)를 통하여, 칩(300)과 와이어본딩 패드(121)를 와이어본딩 함으로써(S80), 보드온칩 패키지를 구현할 수 있다.Then, as shown in FIG. 14, the solder ball 170 is formed on the solder ball pad 122 (S60), the chip 300 is attached to the other surface of the insulating substrate 110 (S70), and the window ( Through the 160, by wire bonding the chip 300 and the wire bonding pad 121 (S80), a board-on-chip package may be implemented.

상기에서는 본 발명의 바람직한 실시예를 참조하여 설명하였지만, 해당 기술 분야에서 통상의 지식을 가진 자라면 하기의 특허 청구의 범위에 기재된 본 발명의 사상 및 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art to which the present invention pertains without departing from the spirit and scope of the present invention as set forth in the claims below It will be appreciated that modifications and variations can be made.

전술한 실시예 외의 많은 실시예들이 본 발명의 특허청구범위 내에 존재한다.Many embodiments other than the above-described embodiments are within the scope of the claims of the present invention.

도 1 내지 도 5는 종래기술에 따른 보드온칩 패키지 기판의 제조방법을 나타내는 흐름도.1 to 5 are flowcharts illustrating a method of manufacturing a board-on-chip package substrate according to the prior art.

도 6은 본 발명의 일 실시예에 따른 보드온칩 패키지 기판 제조방법을 나타내는 순서도.Figure 6 is a flow chart showing a method for manufacturing a board-on-chip package substrate according to an embodiment of the present invention.

도 7 내지 도 14는 본 발명의 일 실시예에 따른 보드온칩 패키지 기판 제조방법을 나타내는 흐름도.7 to 14 are flowcharts illustrating a method for manufacturing a board-on-chip package substrate according to an embodiment of the present invention.

<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>

110: 절연기판 120: 회로패턴110: insulating substrate 120: circuit pattern

121: 와이어본딩 패드 122: 솔더볼 패드121: wire bonding pad 122: solder ball pad

123: 도금인입선 130: 솔더레지스트123: plating lead wire 130: solder resist

140: 도금레지스트 150: 표면처리층140: plating resist 150: surface treatment layer

160: 윈도우 170: 솔더볼160: Windows 170: solder ball

200: 잉크젯 헤드 210: 포토레지스트 잉크200: inkjet head 210: photoresist ink

230: 라우터 비트 300: 칩230: router bit 300: chip

310: 접착층 320: 와이어310: adhesive layer 320: wire

330: 인캡슐레이션부330: encapsulation

Claims (4)

절연기판의 일면에 와이어본딩 패드와 솔더볼 패드 및 도금인입선을 형성하는 단계;Forming a wire bonding pad, a solder ball pad, and a plating lead on one surface of the insulating substrate; 상기 와이어본딩 패드와 상기 솔더볼 패드 및 상기 도금인입선에 상응하는 개구부가 형성된 솔더레지스트를 상기 절연기판의 일면에 형성하는 단계;Forming a solder resist having an opening corresponding to the wire bonding pad, the solder ball pad, and the plating lead on one surface of the insulating substrate; 상기 와이어본딩 패드와 상기 솔더볼 패드의 표면에 표면처리층을 형성하는 단계;Forming a surface treatment layer on surfaces of the wire bonding pads and the solder ball pads; 잉크젯 방식을 이용하여, 상기 도금인입선의 표면에 포토레지스트 잉크를 선택적으로 도포하는 단계; 및Selectively applying photoresist ink on a surface of the plating lead wire using an inkjet method; And 상기 포토레지스트 잉크가 도포된 영역을 가공하여, 상기 절연기판을 관통하는 윈도우를 형성하는 단계를 포함하며,Processing the region to which the photoresist ink is applied to form a window penetrating the insulating substrate; 상기 표면처리층을 형성하는 단계는,Forming the surface treatment layer, 상기 도금인입선의 상면에 도금레지스트를 형성하는 단계; 및Forming a plating resist on the upper surface of the plating lead wire; And 전해도금을 통하여 상기 와이어본딩 패드와 상기 솔더볼 패드에 도금층을 형성하는 단계를 포함하는 것을 특징으로 하는 보드온칩 패키지 기판 제조방법.And forming a plating layer on the wire bonding pad and the solder ball pad through electroplating. 제1항에 있어서,The method of claim 1, 상기 윈도우를 형성하는 단계 이후에,After forming the window, 상기 솔더볼 패드에 솔더볼을 형성하는 단계;Forming a solder ball on the solder ball pad; 상기 절연기판의 타면에 칩을 부착하는 단계; 및Attaching a chip to the other surface of the insulating substrate; And 상기 윈도우를 통하여, 상기 칩과 상기 와이어본딩 패드를 와이어본딩 하는 단계를 더 포함하는 것을 특징으로 하는 보드온칩 패키지 기판 제조방법.And wire-bonding the chip and the wire bonding pad through the window. 삭제delete 제1항 또는 제2항에 있어서,The method according to claim 1 or 2, 상기 윈도우를 형성하는 단계는 라우팅 비트를 이용하여 수행되는 것을 특징으로 하는 보드온칩 패키지 기판 제조방법.Forming the window is a board-on-chip package substrate manufacturing method, characterized in that performed using the routing bit.
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KR20050006503A (en) * 2003-07-09 2005-01-17 매그나칩 반도체 유한회사 Method for forming resist pattern using inkjet nozzle in fabrication of semiconductor device
KR20060108045A (en) * 2005-04-12 2006-10-17 주식회사 심텍 Window manufacture method of semiconductor package type printed circuit board
KR100648916B1 (en) 2005-04-12 2006-11-27 주식회사 심텍 Window manufacture method of semiconductor package type printed circuit board

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