JP2002299790A - Router processing method and router processed substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a router processed method in which on flashes are not generated in processed traces, and to provide a substrate formed thereby. SOLUTION: A processing position is covered with colder resists 1, 1. When the substrates are overlapped, to be subjected to a router process and chips of a resin generated from a core insulated layer 2 of an underside substrate, reach between the substrates, the chip are immediately brought into contact with the section of the solder resist 1, so that the chips are cut by the impact of rotation and are pulverized. The pulverized chips are discharged upwardly, as it is. For this reason, the chips stay in a space between the substrates, and flashes do not occur. Even if the substrate is subjected to the router process in a state of a paper being interposed between the substrates, the same effect can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to router processing on a substrate on a thin plate such as a printed wiring board. More particularly, the present invention relates to a router processing method for preventing generation of burrs due to processing and a substrate using the method.

[0002]

2. Description of the Related Art Conventionally, a slit is formed in a substrate such as between a piece portion and a frame portion of a multi-piece substrate by a router process. Generally, a plurality of substrates to be processed are overlapped and processed at a time in terms of work efficiency.

[0003]

However, conventionally,
When router processing is performed in the state of being overlapped as described above, there has been a problem that burrs are easily generated in the processing trace (FIG. 9). FIG. 9 shows the processing trace and its surroundings, which was the upper side during processing. Such burrs are particularly noticeable in FIG.
As shown in FIG. 0, it often occurs at the processing trace (indicated by an arrow X in the figure) on the upper side (the root side of the processing bit 90) in the figure at the time of processing and on the surface facing the other substrate.
Furthermore, it tends to occur particularly when the substrate is made of a material called an RCF material or the like.

The present invention has been made to solve the above-mentioned problems of the conventional router processing technology.
That is, it is an object of the present invention to provide a router processing method in which burrs are not generated on a processing mark and a substrate using the same.

[0005]

According to the router processing method of the present invention which has been made to solve this problem, at least one side of the substrate having an uneven surface is provided with an uneven surface facing inward. When performing router processing in a state of being superimposed on a substrate, a chip cutting member is arranged at a position to be processed between the uneven surface and another substrate, and router processing is performed in that state. Of course, "other substrates" and chip cutting members are also router-processed at the same time.

[0006] When the substrate is subjected to the router processing as described above, the cuttings shaved from the substrate by the router bit are discharged toward the root of the router bit by the rotation of the router bit. In this method, at the time of processing, a cutting powder cutting member exists at a position to be processed between the substrates. Therefore, the cutting powder discharged from the cross section of the substrate and reaching between the substrate and the substrate is immediately hit by the cutting powder cutting member and cut and crushed. For this reason, the cutting powder does not adhere to the substrate while staying between the substrates and does not form burrs. As a result, a clean processing trace with no burrs remaining after processing is obtained.

The router processing method of the present invention is realized by forming a solder resist at least at a position to be processed on the uneven surface. This is because the solder resist at the processing position acts as a cutting powder cutting member. Alternatively, it can also be realized by sandwiching paper covering at least the processing position between the uneven surface and another substrate, and performing router processing in that state. This is because the paper at the processing position functions as a cutting powder cutting member.

[0008] The substrate of the present invention has an irregular surface having an irregular pattern on at least one side, is subjected to router processing, and a solder resist is formed at least at a router processing position on the irregular surface. Substrate. In other words, this substrate has a clean processing trace without burrs because the solder resist at the router processing position has acted as the above-mentioned chip cutting member when the router processing is performed.

[0009]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings.

(First Embodiment) In the present embodiment, as shown in FIG. 1, a surface of a solder resist 1, 1 covers a processing position on a processing target substrate. Although the processed position is originally a place that does not need to be covered with the solder resists 1, 1, it is intentionally covered with the solder resists 1, 1 in the present embodiment. In this substrate, the core insulating layer 2 exists at the center in the thickness direction. And
Copper patterns 3 and 3 are formed on the front and back sides. Most of the copper patterns 3, 3 are covered with the solder resist 1, 1. This board also has copper patterns on the front and back.
There is also provided a through hole 4 for establishing conduction between them.

At the time of processing, as shown in FIG. 2, two substrates (of course, three or more substrates) of FIG. 1 are superimposed, and in this state, the processing position is processed by the processing bit 90. Although FIG. 2 depicts a slight gap between the two substrates, the substrate is actually processed by being sandwiched and brought into close contact with an appropriate fixture. At the time of this processing, the core insulating layer 2 and the solder resist 1 of the substrate are scraped off by the processing bit 90, and the portion becomes a slit. That is, each substrate is processed together with the front and back solder resists 1. At this time, chips generated from the cross section of the processed core insulating layer 2 and the solder resist 1 are discharged toward the root side (upward in FIG. 2) by the rotation of the processing bit 90.

In FIG. 2, the solder resist 1 also exists at a position directly in contact with the processing bit 90 between the two processing target substrates. For this reason, the resin chips generated from the core insulating layer 2 of the lower substrate in FIG. 2 are transported upward by the rotation of the processing bit 90 and escape from the core insulating layer 2, and immediately, the solder resist 1 Touch the cross section. For this reason, it is cut and crushed by the impact of rotation. The crushed swarf is discharged upward as it is. Therefore, the chips do not stay in the space between the substrates to form burrs. As a result, as shown in FIG. 3, a clean machining trace without burrs can be obtained. That is, in FIG. 3, no burrs are projected from the end face of the slit 5 formed by the processing. Thus, the solder resist 1 is also formed at the router processing position on the surface, and a substrate on which the solder resist 1 has been router processed is obtained.

As shown in FIG. 10, if there is no solder resist 1 at a position in contact with the processing bit 90 between the two substrates, resin chips stay in the space of this part during processing. For this reason, the retained cuttings adhere to the position of the shoulder between the surface and the cross section of the substrate on the lower side in the figure and become burrs. In this embodiment, such a situation is excluded.

As described above, in the case of FIG. 10, burrs are likely to occur particularly when the substrate is made of the RCF material. The reason is presumed to be as follows. That is, in many cases, the resin layer of the RCF material is provided with flexibility by adding a plasticizer in order to prevent cracking and peeling due to a difference in thermal expansion coefficient from the copper foil. For this reason,
If chips stay in the space between the substrates, they easily adhere to the substrates and easily become burrs. Of course, in this form,
Even when the substrate is made of the RCF material, burrs are hardly generated.

(Second Embodiment) In this embodiment, as shown in FIG. 4, the surface of the solder resist 1, 1 does not cover the position to be processed in the substrate to be processed. This is rather common as the pattern of the solder resists 1 and 1.
The other points are the same as those in the first embodiment shown in FIG.

At the time of processing, as shown in FIG. 5, two substrates (of course, three or more substrates) of FIG. 4 are superimposed, and paper 6 is sandwiched between them. To process the processing position. Examples of usable paper types include high-quality paper, semi-paper, kraft paper, and the like. Although FIG. 5 depicts a slight gap between the two substrates, the substrate is actually processed by being sandwiched and brought into close contact with an appropriate fixture. At the time of this processing, the core insulating layer 2 of the substrate is scraped off by the processing bit 90, and the portion becomes a slit. The part of the paper 6 is also processed at the same time. At this time, chips generated from the cross section of the core insulating layer 2 being processed are discharged toward the root side (upward in FIG. 5) by the rotation of the processing bit 90.

In FIG. 5, the paper 6 is present between the two substrates to be processed up to a position directly in contact with the processing bit 90. For this reason, the resin chips generated from the core insulating layer 2 of the lower substrate in FIG.
When it is transported upward by the rotation of 0 and escapes from the core insulating layer 2, it hits the paper 6. For this reason, it is cut and crushed by the impact of rotation. The crushed swarf is discharged upward as it is. Therefore, the chips do not stay in the space between the substrates to form burrs. As a result, as shown in FIG. 6, a clean machining trace without burrs can be obtained. That is, in FIG. 6, no burrs are projected from the end face of the slit 5 formed by processing.

As shown in FIG. 10, if there is no paper 6 between the two substrates, resin chips stay in the space at the time of processing. For this reason, the retained cuttings adhere to the position of the shoulder between the surface and the cross section of the substrate on the lower side in the figure and become burrs. In this embodiment, such a situation is excluded. Of course, the same is true even when the substrate is made of the RCF material.

Here, it is considered that there is a concern that the processing accuracy may be reduced by inserting the paper 6 between the substrates. Therefore, paper 6 (30 g of the above usable paper)
/ m ² , a 40 μm-thick product may be used). The test is
When the paper 6 is processed without being sandwiched, when the paper 6 is processed by being sandwiched, one sheet of paper 6 is processed by being sandwiched,
For the three cases, the measurement was performed by measuring the positional accuracy of the slit 6 after processing. Further, two diameters of 1.6 mm (for the long outer diameter) and 1.1 mm (for the short piece) are used.
Each type of machining bit was tested. In each case, the N number was 20.

As a result of the test, the results shown in FIG. 7 (1.6 mm diameter) and FIG. 8 (1.1 mm diameter) were obtained. Regardless of the processing bit diameter and the condition of no paper, one sheet, or two sheets, the width of the processing position variation is 0.04 to 0.06.
There is not much difference in about mm. Thus, paper 6 between the substrates
It can be seen that even if router processing is carried out in a state in which is sandwiched, there is almost no reduction in processing accuracy due to that.

As described above in detail, in the present embodiment, the processing position is also covered with the solder resists 1 and 1 (first embodiment). Alternatively, processing is performed with the paper 6 sandwiched between the substrates (second embodiment). Thereby, when the resinous chips shaved from the substrate are conveyed by the rotation of the processing bit 90 and reach between the substrates, the chips are cut and crushed. As a result, a router processing method has been realized in which chips are prevented from staying in gaps between substrates and causing burrs.

The present embodiment is merely an example, and does not limit the present invention. Therefore, naturally, the present invention can be variously modified and modified without departing from the gist thereof.

For example, the substrate to be processed may have an inner layer structure. In the first embodiment,
Only the upper surface of the lower substrate in FIG. 2 needs to cover the processing position with the solder resist 1. This is because the generation of burrs due to swarf remains a problem only here. Further, in the first embodiment, the solder resist 1 may cover the entire plate surface. Even in this case, usually, the copper pattern 3 under the solder resist 1 is used.
Since there is such an uneven pattern, it corresponds to the “uneven surface” in the present invention. Further, in the second embodiment, the paper 6 does not necessarily have to cover the entire surface of the plate, but it is sufficient if the paper 6 exists only at the position to be processed and its periphery.

[0024]

As is apparent from the above description, according to the present invention, there is provided a router processing method in which burrs are not generated in a processing trace, and a substrate using the same.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a substrate to be processed in a first embodiment.

FIG. 2 is a diagram illustrating router processing of a substrate according to the first embodiment.

FIG. 3 is a partial plan view showing a processing trace obtained by performing router processing in the first embodiment.

FIG. 4 is a sectional view of a substrate to be processed in a second embodiment.

FIG. 5 is a diagram illustrating router processing of a substrate according to a second embodiment.

FIG. 6 is a partial plan view showing a processing trace obtained by performing router processing in the second embodiment.

FIG. 7 is a graph showing the processing accuracy in the case of performing router processing by sandwiching paper between substrates (processing bit diameter 1.6 m).
m).

FIG. 8 is a graph showing the processing accuracy in the case of performing router processing by inserting paper between substrates (a processing bit diameter of 1.1 m);
m).

FIG. 9 is a partial plan view of a router processing trace according to the related art.

FIG. 10 is a diagram showing a conventional router processing of a substrate.

[Explanation of symbols]

 1 Solder resist 6 paper

Claims (4)

[Claims] When a substrate having at least one surface which is an uneven surface having an uneven pattern is router-processed in a state where the uneven surface is directed inward and the other substrate is superimposed on the substrate, the uneven surface and the other substrate are overlapped. A router processing method, comprising disposing a cutting powder cutting member at a processing position between them and performing router processing in that state. 2. The router processing method according to claim 1, wherein a solder resist is formed at least at a position to be processed on the uneven surface, and the solder resist is used as the cutting powder cutting member. Processing method. 3. The router processing method according to claim 1, wherein a paper covering at least a processing position is sandwiched between the uneven surface and another substrate, and the paper is used as the cutting powder cutting member. A router processing method characterized by the above-mentioned. 4. At least one surface is an uneven surface having an uneven pattern, is router-processed, a solder resist is formed at least in a router processing position of the uneven surface, and the solder resist is router-processed together with the solder resist. Characterized by a router processed substrate.