JP3498570B2 - Driving circuit and driving method for electro-optical device and electronic apparatus - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistor (hereinafter referred to as TFT) driving, thin film diode (hereinafter referred to as TFT)
Drive circuit and driving method for supplying an image signal, a clock signal, etc. to an electro-optical device provided with an electro-optical panel such as a liquid crystal panel of an active matrix drive system by driving, etc., and the electro-optical device and drive. It belongs to the technical field of electronic devices equipped with circuits. In particular, the present invention is
Vertical scanning, field scanning, or frame scanning is performed based on the clock signal, and at least scanning lines (rows)
It belongs to the technical field of a driving circuit or the like that inverts the polarity of the voltage applied to the pixel electrode every time, that is, drives the voltage applied to the pixel electrode by an inversion driving method in which the center of the amplitude of the image signal is inverted as a reference potential.

[0002]

2. Description of the Related Art Conventionally, in an active matrix drive type liquid crystal device by TFT drive, TFD drive, etc.,
A large number of scanning lines and data lines arranged in the vertical and horizontal directions, and a large number of pixel electrodes corresponding to the respective intersections thereof are provided on the TFT array substrate. Then, a scanning signal is sequentially supplied from a scanning line driving circuit to each scanning line based on a Y clock signal which is a reference for driving the scanning line, and in parallel with this, based on an X clock signal which is a reference for driving the data line. A data signal corresponding to an image signal to be displayed is supplied to each data line from the data line driving circuit line-sequentially or a plurality of lines simultaneously,
Vertical scanning in field units or frame units, that is,
Generally, field scanning or frame scanning is performed.

As described above, when the liquid crystal panel is driven by the drive circuit, in order to prevent the deterioration of the liquid crystal due to the application of the DC voltage and the flicker on the display screen,
Field inversion drive method or frame inversion drive method that inverts the liquid crystal applied voltage for each field or frame, scanning line inversion drive method that inverts the liquid crystal applied voltage for each scanning line (row), liquid crystal applied voltage for each data line (column) Various inversion drive methods such as a data line inversion drive method in which the liquid crystal applied voltage is inverted for each scanning line (row) and data line (column), that is, for each dot (pixel) are used. ing.

Among these inversion driving methods, the method of reversing the polarity at least for each scanning line (row) has a high function of preventing liquid crystal deterioration and flicker, and is the mainstream from the viewpoint of circuit configuration and controllability. There is.

Here, as shown in FIG. 16, scanning lines (rows)
In the method of performing the inversion drive every time, for example, by suspending (stopping) the X clock signal within the vertical blanking period from one field scan (display period) to the next field scan (display period), If the polarity inversion is stopped, the potential on the data line at the end of each vertical blanking period is inverted, so that the field frequency (for example, 6
A flicker having a frequency (for example, 30 Hz) that is ½ of 0 Hz is generated.

Therefore, conventionally, not only during the display period but also during the vertical retrace period, the X clock signal is continuously supplied to the scanning line drive circuit and the polarity of the liquid crystal applied voltage is inverted.

[0007]

In the technical field of liquid crystal devices, there is a strong demand for energy saving and high quality display images.

However, as described above, if the liquid crystal applied voltage is inverted during the vertical blanking period, the power consumption increases due to the inverting operation of the data line driving circuit during this vertical blanking period. There is a point. According to the research conducted by the inventors of the present application, for example, the power consumption is 7 compared to the case where the clock signal is stopped within the vertical blanking period as described above.
% (That is, the ratio of the vertical blanking period to the total time) also increases. On the other hand, in the method in which the clock signal is paused in the vertical blanking period, the image quality is significantly deteriorated due to the occurrence of flicker, and it does not meet the recent demand for higher quality display images. There is no.

Therefore, according to the present invention, a driving circuit and a driving method for an electro-optical device such as a liquid crystal device, which can reduce the power consumption in the vertical blanking period while reducing the occurrence of flicker, the electro-optical device and the electronic device. The challenge is to provide equipment.

[0010]

In order to solve the above-mentioned problems, a drive circuit for an electro-optical device according to a first aspect of the present invention has a plurality of data lines and a plurality of scanning lines arranged in a matrix, and the plurality of scan lines. A switching unit provided corresponding to the intersection of the data line and the plurality of scanning lines, a pixel electrode connected to the switching unit, and an image signal supplied via the image signal line according to a clock signal. A driving circuit of an electro-optical device comprising a data line driving unit for sampling and applying to the plurality of data lines, and a scanning line driving circuit for supplying a scanning signal to the plurality of scanning lines. Signal processing means for supplying the image signal to the image signal line after processing the image signal so that the polarity of the applied voltage applied to the liquid crystal part via the liquid crystal portion is inverted every vertical scanning period and at least every scanning line. A voltage supply means for supplying a voltage signal of the same fixed potential to the image signal line instead of the image signal in each vertical retrace period, and a clock signal to the data line driving means, and the voltage signal And a clock supply control means for suspending the clock signal during a predetermined period within the vertical blanking period after being applied to the data line.

According to the driving circuit of the electro-optical device according to the first aspect, when the image signal is input from the external image signal source, the signal processing unit first converts the image signal into a format corresponding to vertical scanning. Processed and processed so that the polarity of the applied voltage is inverted at least every scanning line. And
The image signal that has undergone these processes is supplied to the image signal line. In parallel with this, the clock supply control means supplies the clock signal to the data line driving means. When the image signal and the clock signal are thus supplied, the data line driving means samples the image signal in accordance with the clock signal and applies the image signal to the plurality of data lines as a data signal. At the same time, the scanning line driving means applies scanning signals to the plurality of scanning lines. As a result, vertical scanning of the scanning line (row) inversion driving method is performed in the plurality of pixel electrodes by the data signal and the scanning signal.

On the other hand, in each vertical blanking period, the voltage supply unit supplies the voltage signal of the same fixed potential to the image signal line instead of the image signal. And, in particular, during a predetermined period after the voltage signal is applied to the data line by the data line driving means, for example, immediately after (or just before) the start of the vertical blanking period, this clock signal is stopped by the clock supply control means. It As a result, the sampling of the data line driving means according to the clock signal is suspended during a predetermined period within the vertical blanking period, so that the power consumption consumed as the applied voltage is not suspended by the conventional clock signal. Compared with the case, it can be reduced by the ratio of the predetermined period to the total time. Since the predetermined period is set after the voltage signal is applied in the vertical retrace line period, it does not matter whether it is after odd field scanning or even field scanning even in the field inversion driving method. Instead, the potential on the data line in each predetermined period is basically the predetermined potential. That is, unlike the example of FIG. 16 described above, the potentials on the data line do not differ in a predetermined period before and after, so that it is possible to reduce the occurrence of flicker having a period twice the period of the predetermined period.

A driving circuit of the electro-optical device according to a second aspect is the driving circuit of the electro-optical device according to the first aspect, wherein the voltage supply unit selects the fixed constant potential source and the signal processing unit. It is characterized by further comprising switch means connected to the image signal line.

According to the drive circuit of the electro-optical device according to the second aspect, the constant potential source of the fixed potential and the signal processing unit are selectively connected to the image signal line by the switch unit provided in the voltage supply unit. To be done. Therefore, to the data line driving means, it is possible to supply the image signal from the signal processing means during the display period and the voltage signal of the fixed potential from the constant potential source immediately after or immediately before the start of the vertical blanking period. it can. As a result, the potential on the data line in each predetermined period is basically fixed potential, and the occurrence of flicker described above can be reduced.

A drive circuit for an electro-optical device according to a third aspect is the drive circuit for an electro-optical device according to the first aspect, wherein the signal processing means includes the voltage supply means, and the vertical blanking period. A dummy signal of the fixed potential is supplied to the image signal line instead of the image signal.

According to the driving circuit of the electro-optical device according to the third aspect, the dummy signal of the fixed potential is supplied to the data line driving means during the vertical retrace period by the voltage supply means included in the signal processing means. It is supplied instead of the image signal. As a result, the potential on the data line in each predetermined period is basically fixed potential, and the occurrence of flicker described above can be reduced.

A drive circuit for an electro-optical device according to a fourth aspect is the drive circuit for an electro-optical device according to any one of the first to third aspects, wherein the voltage supply unit sets the minimum value of the applied voltage. It is characterized in that a corresponding potential is supplied as the fixed potential.

According to the drive circuit of the electro-optical device of the fourth aspect, the potential corresponding to the minimum value of the applied voltage is the fixed potential. Therefore, during each predetermined period, the potential on the data line corresponds to the minimum value of the applied voltage, for example, the potential corresponding to white display in the normally white mode when the electro-optical device is a liquid crystal device. Since it is said that
The aforementioned flicker does not occur.

In order to solve the above-mentioned problems, the drive circuit of the electro-optical device according to a fifth aspect of the invention has a plurality of data lines and a plurality of scanning lines arranged in a matrix, a plurality of the data lines and the plurality of the data lines. The switching means provided at the intersection with the scanning line, the pixel electrode connected to the switching means, and the image signal supplied via the image signal line are sampled in accordance with a clock signal to perform the sampling. A drive circuit of an electro-optical device comprising a data line drive means for applying to a data line and a scan line drive circuit for supplying a scan signal to the plurality of scan lines, wherein the drive circuit is provided to the liquid crystal part via the pixel electrodes. Signal processing means for supplying the image signal line after processing the image signal so that the polarity of the applied voltage is inverted at least every scanning line and every field; and the clock signal. To the data line driving means, and in the vertical blanking period, the clock signal is paused during a predetermined period in which the lengths differ by one horizontal scanning period between the odd field scanning and the even field scanning. A control means, and the signal processing means supplies a fixed potential of the same polarity to the image signal line during the vertical blanking period.

According to the driving circuit of the electro-optical device of the fifth aspect, when the image signal is inputted from the external image signal source, the image signal is first processed by the signal processing means so as to correspond to the odd and even field scanning. And the polarity of the applied voltage is inverted at least every scanning line and every field. Then, the image signal that has undergone these processes is supplied to the image signal line. In parallel with this, the clock signal is controlled by the clock supply control means,
It is supplied to the data line driving means. When the image signal and the clock signal are supplied in this way, the image signal is sampled by the data line driving means in accordance with the clock signal and applied as a data signal to the plurality of data lines. At the same time, the scanning line driving means applies scanning signals to the plurality of scanning lines. As a result, vertical scanning of the scanning line (row) inversion drive and the field inversion drive system is performed in the plurality of pixel electrodes by the data signal and the scanning signal.

On the other hand, during a predetermined period within the vertical blanking period, this clock signal is stopped by the clock supply control means. As a result, since the sampling of the data line driving means according to the clock signal is suspended during the predetermined period, the power consumption consumed as the applied voltage is compared with the conventional case where the clock signal is not suspended, It can be reduced by the ratio of the predetermined period to the total time. In particular, since the length of the predetermined period differs between the odd field scan and the even field scan by one horizontal scan period, the potential on the data line and the even number of the potential on the data line in the predetermined period after the odd field scan are even while performing the field inversion drive. The potential on the data line in a predetermined period after field scanning is at least a fixed potential having the same polarity. That is, unlike the example of FIG. 16 described above, the polarities of the potentials on the data lines do not differ in a predetermined period in which the potentials on the data line are consecutive, so that it is possible to reduce the occurrence of flicker having a period twice the period of the predetermined period.

A drive circuit for an electro-optical device according to a sixth aspect of the present invention is the drive circuit for an electro-optical device according to the fifth aspect, wherein the signal processing means outputs the dummy signal of a fixed potential during the vertical blanking period to the image. The image signal line is supplied instead of the signal.

According to the drive circuit of the electro-optical device of the seventh aspect, during the vertical blanking period, the dummy signal of the fixed potential is supplied to the image signal line instead of the image signal. Therefore, the potential on the data line in the predetermined period after the odd field scanning and the potential on the data line in the predetermined period after the even field scanning are both fixed potentials of the dummy signal while performing the field inversion drive. Therefore, the occurrence of the above-mentioned flicker can be reduced.

A drive circuit for an electro-optical device according to a seventh aspect is the drive circuit for an electro-optical device according to the sixth aspect, wherein the signal processing means sets the potential corresponding to the maximum value of the applied voltage to the fixed potential. Is supplied with the dummy signal.

According to another aspect of the drive circuit of the electro-optical device of the present invention, both the potential on the data line in the predetermined period after the odd field scanning and the potential on the data line in the predetermined period after the even field scanning are applied voltage. Is set to a potential corresponding to the maximum value of, for example, a potential corresponding to black display in the normally white mode when the electro-optical device is a liquid crystal device, so that the occurrence of flicker described above can be reduced.

In order to solve the above-mentioned problems, an electronic apparatus according to an eighth aspect comprises the drive circuit for the electro-optical device according to any one of the first to seventh aspects and the electro-optical device. Characterize.

According to the eighth aspect of the present invention, the electronic device is provided with the drive circuit for the electro-optical device and the electro-optical device according to the present invention described above, so that it is possible to reduce power consumption during a predetermined period and prevent flicker. Thus, it is possible to realize an electronic device that saves energy and improves the quality of displayed images.

In order to solve the above-mentioned problems, a driving method of an electro-optical device according to a ninth aspect of the present invention, a plurality of data lines and a plurality of scanning lines arranged in a matrix, a plurality of the data lines and the plurality of the data lines. The switching means provided at the intersection with the scanning line, the pixel electrode connected to the switching means, and the image signal supplied via the image signal line are sampled in accordance with a clock signal to perform the sampling. A driving method of an electro-optical device comprising a data line driving means for applying to a data line and a scanning line driving circuit for supplying a scanning signal to the plurality of scanning lines, the method comprising: The image signal is processed so that the polarity of the applied voltage is inverted every vertical scanning period and at least every scanning line, and then supplied to the image signal line. The voltage signal is supplied to the data line through the image signal line, and then the clock signal is temporarily stopped.

According to the driving method of the electro-optical device in the ninth aspect, in each vertical blanking period, first, the voltage signal of the same fixed potential is supplied to the data line via the image signal line. After that, the clock signal is temporarily suspended.
As a result, the sampling of the data line driving means in response to the clock signal is suspended during a predetermined period within the vertical blanking period, so that power consumption consumed as an applied voltage can be reduced. Since the predetermined period is set after the voltage signal is applied in the vertical retrace line period, it does not matter whether it is after odd field scanning or even field scanning even in the field inversion driving method. Instead, the potential on the data line in each predetermined period is basically a fixed potential. That is, it is possible to reduce the occurrence of flicker having a cycle that is twice the cycle of the predetermined period.

In order to solve the above-mentioned problems, a driving method of an electro-optical device according to a tenth aspect of the present invention is configured such that a plurality of data lines and a plurality of scanning lines arranged in a matrix form, a plurality of the data lines and the plurality of the data lines. The switching means provided at the intersection with the scanning line, the pixel electrode connected to the switching means, and the image signal supplied via the image signal line are sampled in accordance with a clock signal to perform the sampling. A driving method of an electro-optical device comprising a data line driving means for applying to a data line and a scanning line driving circuit for supplying a scanning signal to the plurality of scanning lines, the method comprising: The image signal is processed so that the polarity of the applied voltage is inverted at least every scanning line and every field, and then supplied to the image signal line, and the clock signal is supplied to the data signal. The signal is supplied to the line driving means, and in the vertical blanking period, the clock signal is paused in a predetermined period whose lengths are different by one horizontal scanning period after the odd field scanning and after the even field scanning, and the vertical blanking period is performed. In the above, a fixed potential having the same polarity is supplied to the image signal line.

According to the driving method of the electro-optical device according to the tenth aspect, the clock signal is supplied in a predetermined period different in one horizontal scanning period between the odd field scanning and the even field scanning in the vertical blanking period. It is temporarily suspended. Further, during the predetermined period, the potential on the data line in the predetermined period after the odd field scanning and the potential on the data line in the predetermined period after the even field scanning are at least fixed potentials having the same polarity while performing the field inversion drive. . That is, since the polarities of the potentials on the data lines do not differ in a predetermined period before and after, the occurrence of flicker having a period twice the period of the predetermined period can be reduced.

[0032]

[0033]

[0034]

[0035]

[0036]

[0037]

[0038]

[0039]

[0040]

[0041]

[0042]

The operation and other advantages of the present invention will be apparent from the embodiments described below.

[0044]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) First, a first embodiment will be described with reference to FIGS. Figure 1
2 is an overall block diagram of a liquid crystal device and a signal supply device for supplying an image signal, a clock signal and the like to the drive circuit as an example of an electro-optical device including a liquid crystal panel provided with a drive circuit. FIG. 3 is a block diagram showing the configuration of various wirings, peripheral circuits, etc. provided on the TFT array substrate of FIG. 3A is a circuit diagram of a sampling circuit included in the drive circuit of FIG. 1, and FIG. 3B is a timing chart thereof. 4A is a block diagram of a main part of the timing generation circuit included in the signal supply device of FIG. 1, and FIG. 4B is a timing chart thereof. 5 and 6 are timing charts of various signals in the signal supply device and the drive circuit of FIG. 1, respectively. In the present embodiment, the present invention is applied to an active matrix drive type liquid crystal device driven by a TFT.

In FIG. 1, the liquid crystal device 200 comprises a liquid crystal display section 1a in which liquid crystal is sealed between a pair of substrates, a data line driving circuit 101, and a scanning line driving circuit 104. The data line driving circuit 101 samples the image signal Vi supplied from the image signal line 400 in accordance with a clock signal CLX which is a reference clock signal for applying a data signal, and applies the image signal Vi to each of the plurality of data lines 35 as a data signal. . Then, the scan line driver circuit 104
Is a reference clock for applying a scanning signal in order to perform vertical scanning in the direction (Y direction) perpendicular to the scanning line 31 by the data signal and the scanning signal in the liquid crystal display unit 1a including a plurality of pixel units arranged in a matrix. Clock signal C which is
The scanning signals are sequentially applied to the plurality of scanning lines 31 based on LY.

The liquid crystal device 200 further comprises a sampling circuit 301. Sampling circuit 30
1 includes a plurality of sampling switches 302 respectively connected to the plurality of data lines 35. The image signal Vi is supplied to each sampling switch 302, and each sampling switch 302 is closed by a transfer signal from a shift register circuit (see FIG. 3) described later included in the data line driving circuit 101. That is, the image signal Vi is transferred to the data line 3
5 is sampled in accordance with the transfer signal and applied to each of the plurality of data lines 35 as a data signal.

On the other hand, the signal supply device 300 includes a signal processing circuit 310, a timing generation circuit 320, and a constant potential source 330.
And a changeover switch 340.

The signal processing circuit 310 processes the image signal Vi in a format corresponding to vertical scanning, and the polarities of the liquid crystal applied voltages applied to the liquid crystal portions in the plurality of pixel portions constituting the liquid crystal display portion 1a are at least. After being processed so as to be inverted for each scanning line 31 (that is, for each row), it is supplied to the changeover switch 340 and the image signal line 400.

The constant potential source 330 is the changeover switch 34.
By connecting to the image signal line 400 by 0, the voltage signal VOL having a predetermined potential is supplied to the image signal line 400 instead of the image signal Vi in the vertical retrace line period of the vertical scanning.

Then, the timing generation circuit 320, which constitutes an example of the clock supply control means, uses the clock signal CL.
X is supplied to the data line driving circuit 101, and the voltage signal V
It is configured to pause the clock signal CLX during a pause period of a predetermined length within the vertical blanking period after OL is applied to the data line.

Next, the configuration of the liquid crystal device 200 will be further described with reference to FIG. In addition, in FIG. 2, as a specific example of the liquid crystal device 200 shown in FIG. 1, image signals Vi are composed of image signals VID1 to VID6 in which six phases are expanded, and further, a data line driving circuit 101, a scanning line driving circuit 104, and Although an example of a device in which the sampling circuits 301 are all formed on the same substrate is shown, the formation position of the driving circuit is not limited to this. For example, the drive circuit may be configured by an external IC (integrated circuit) and connected to the liquid crystal panel including the liquid crystal display unit 1a.

In FIG. 2, the liquid crystal device 200 includes a TFT array substrate 1 made of, for example, a quartz substrate, hard glass or a silicon substrate. TFT array substrate 1
A plurality of pixel electrodes 11 arranged in a matrix are formed on the upper side.
A plurality of data lines 35 (source electrode lines) arranged in the X direction and each extending in the Y direction, and a plurality of scanning lines 31 arranged in the Y direction and each extending in the X direction.
The (gate electrode line) and each data line 35 and the pixel electrode 11 are respectively interposed, and a conductive state and a non-conductive state between the data line 35 and the pixel electrode 11 are respectively set according to the scanning signals supplied via the scanning line 31. A plurality of TFTs 30 to be controlled are formed. In addition, the pixel electrode 11 is formed on the TFT array substrate 1.
A capacitance line 31 ′ (storage capacitance electrode), which is a wiring for a storage capacitance that keeps the voltage applied to, for a long time, is formed in parallel with the scanning line 31.

A sampling circuit 301, a data line driving circuit 101, and a scanning line driving circuit 104 are further formed on the TFT array substrate 1.

The scanning line drive circuit 104 has a shift register circuit, and a clock signal CLY and a shift register start signal D supplied from the signal supply device 300.
Based on Y, a power supply, etc., a scanning signal having a predetermined waveform and a predetermined timing is generated from the transfer signal output from the shift register circuit, and is applied to the scanning line 31 (gate electrode line) in a pulse-sequential manner. It is configured.

The data line driving circuit 101 has a shift register circuit (see FIG. 3) which will be described later, and based on the clock signal CLX, the shift register start signal DX, the power supply, etc., supplied from the signal supply device 300. A sampling circuit drive signal having a predetermined waveform and predetermined timing is generated from the transfer signal output from the shift register circuit,
The six image input signal lines VID1 to VID6 are aligned with the timing at which the scanning line driving circuit 104 applies the scanning signal.
The sampling circuit 30 is provided for each data line 35.
1 through the sampling circuit drive signal line 306.

The sampling circuit 301 is, for example, a TFT
Sampling switch 302 composed of each of the data lines 35 is provided, and image input signal lines VID1 to VI are provided.
D6 is connected to the source electrode of the sampling switch 302, and the sampling circuit drive signal line 306 is connected to the gate electrode of the sampling switch 302. When six parallel image signals Vi are input via the image input signal lines VID1 to VID6, these image signals Vi are sampled. When a sampling circuit drive signal is input from the data line drive circuit 101 via the sampling circuit drive signal line 306, the image signal Vi sampled for each of the six image input signal lines VID1 to VID6 The data signals are simultaneously applied to the six adjacent data lines 35 forming the line group, and further such an image signal Vi is sequentially applied for each data line group. That is, the data line drive circuit 101 and the sampling circuit 301 are expanded into six phases and the image input signal line V
The six parallel image signals Vi input from ID1 to VID6 are supplied to the data line 35. The sampling circuit 301 is a circuit that samples the image signal Vi in order to stably supply the high-frequency image signal Vi to each data line 35 at a predetermined timing in synchronization with the scanning signal. Sampling circuit 30
The number of phase expansions of the image signal Vi input to the sampling circuit 301 is determined according to the sampling capability of 1.
That is, when the number of data lines 35 is fixed, the higher the sampling capability, the more the number of phase expansions of the image signal Vi can be reduced. As a result, the sampling circuit 301 reduces the load on the signal source of the image signal such as the image signal processing IC for performing high-resolution display.

In the above description with reference to FIG. 2, the sampling circuit 301 applies the six-phase expanded image signal Vi to the six data lines 35 belonging to one data line group at the same time after sampling. Further, although the image signal Vi is applied to each data line group in sequence, the number of phase expansions and the number of data lines to be applied simultaneously (that is, the number of data lines forming the data line group are The number) is not limited to six. For example, if the sampling capability of the sampling circuit 301 is high, one data line 35
May be sequentially supplied with the image signals Vi that have not been phase expanded, or three, 12
The image signal Vi that has been subjected to 3-phase expansion, 12-phase expansion, 24-phase expansion, or the like may be supplied to the data lines of 24 lines or 24 lines. It should be noted that this number is preferably a multiple of 3 in view of the fact that the color image signal is composed of signals relating to three colors in order to simplify the control and the circuit.

The process of phase-expanding the image signal Vi as illustrated in FIG. 2 into the image signals VID1 to VID6 is shown in FIG.
The signal processing circuit 310 shown in FIG. 3 may be used, or a separate phase expansion circuit may be provided after the changeover switch 340 in the signal supply device 300.

Next, with reference to FIG. 3, a specific circuit configuration and operation of the shift register circuit included in the data line driving circuit 101 will be described. Note that FIG. 3A is a circuit diagram showing the shift register circuit together with the enable circuit, and FIG. 3B is a timing chart of various signals in the data line driving circuit 101.

First, in FIG. 3A, enable circuits 112 are provided corresponding to the outputs of the respective stages of the shift register circuit 101a. Shift register circuit 10
Each of the stages 1a includes a reference clock signal CLX having a predetermined cycle and its inverted signal CLX ′, so that a transfer signal is sequentially output from each stage in a transfer direction corresponding to the right direction (direction from left to right). It is configured to include two clocked inverters that feed back the transfer signal each time the value level changes and transfer to the next stage. Also, the enable circuit 11
2 indicates the pulse width of the transfer signal output from the odd-numbered stages of the shift register circuit 101a as the first enable signal ENB.
The transfer signal and the enable signal E are limited so that the pulse width of the transfer signal output from the even-numbered stages is limited to the pulse width of the second enable signal ENB2.
It is composed of a NAND circuit that takes an exclusive logical product with NB1 or ENB2, and an inverter circuit that inverts the result. A signal DX for starting the transfer of the transfer signal is input to the shift register circuit 101a from the left side in the drawing.

At the timing shown in the timing chart of FIG. 3B, this signal DX, the clock signal CLX and its inverted signal CLX ', and the first and second enable signals E.
When NB1 and ENB2 are input, the shift register circuit 101a configured as described above sequentially outputs transfer signals that are sequentially delayed by a half cycle of the clock signal CLX. Then, the pulse width of this transfer signal is limited to the pulse widths of the signals ENB1 and ENB2 by the enable circuit 112, and the sample and hold circuit drive signals Q1 and Q2, each of which has a width narrower than the pulse width of the clock signal CLX, are generated. Q3, ..., Qn (where n is an odd number)
Are sequentially supplied to the sampling circuit 301.

Next, the timing circuit 320 shown in FIG. 1 will be further described with reference to FIG.

In FIG. 4A, the timing generation circuit 320 includes two counters 321 and 322, and a transmission gate 324.

The vertical synchronizing signal Vsync of the image signal Vo supplied from the signal processing circuit 310 shown in FIG. 1 is input to the counter 321, and the timing generating circuit 320 is further supplied.
A clock signal CLY generated by dividing the reference oscillation signal OS1 is input therein. Then, by using the Vsync as a reference, the vertical count reference signal OFH having a frequency twice that of the clock signal CLY is counted.
The level changes between the display period and the vertical blanking period as shown in (b) (becomes high level during the vertical blanking period).
Generate a blanking signal BLK1 that is a binary signal,
It is output to the control terminal of the changeover switch 340 shown in FIG.

On the other hand, to the counter 322, as shown in FIG. 1, the vertical synchronizing signal Vsync is input from the signal processing circuit 310, and further the clock signal CLY generated by dividing the reference oscillation signal OS1 is input. . Then, by counting the vertical count reference signal OFH with Vsync as a reference, at least one cycle (period ΔT) of the clock signal CLY from the start point of the vertical blanking period as shown in FIG. 4B. After the signal BLK1, a blanking signal BLK2 which is a high level binary signal is generated and output to the control terminal of the transmission gate 324.

The transmission gate 324 has a clock signal C generated by dividing the reference oscillation signal OS1.
While LX is input and the signal BLK2 is at a low level, the clock signal CLX is supplied as it is to the data line driving circuit 101 shown in FIG. On the other hand, the signal BL
During the period when K2 is at high level (pause period),
The clock signal CLX is paused (stopped), and the clock signal CLX is not supplied to the data line driving circuit 101 shown in FIG.

Next, the operation of the liquid crystal display device 200 and the signal supply device 300 configured as described above will be described with reference to FIG.
Will be described with reference to the block diagram of FIG. 6 and the timing charts of FIGS.

First, the image signal V
When o is input from an external image signal source such as a player, a decoder, or a tuner, the signal processing circuit 310 processes the image signal Vo into a format corresponding to vertical scanning, and the polarity of the liquid crystal applied voltage is at least the scanning line. Every 31 (each line)
It is processed so as to be inverted. Then, the image signal Vi that has undergone these processes is supplied to the changeover switch 340 and the image signal line 400. This image signal Vi is, for example, as shown in the uppermost row of FIG. 5, an image signal Vi that constitutes one frame from 525 scanning lines, and in an odd field (scanning lines No. 1 to 263), Scan line No. 1 to 10 are components that are not displayed on the liquid crystal display unit 1a, and the scanning line No. 11 to 242 are components displayed on the liquid crystal display unit 1a. At the same time, the timing generation circuit 320 supplies the clock signal CLX to the data line drive circuit 101. When the image signal Vi and the clock signal CLX are thus supplied, the data line driving circuit 101 changes the image signal Vi to the clock signal CLX.
Are sampled according to the above, and are applied as data signals to the plurality of data lines 35, respectively. At the same time, the scanning line driving circuit 104 sequentially applies scanning signals to the plurality of scanning lines 31. As a result, in the plurality of pixel portions of the liquid crystal display unit 1a, the vertical scanning of the scanning line (row) inversion driving method is performed by the data signal and the scanning signal.

On the other hand, in the vertical blanking period, first, the changeover switch 340 is changed over by the signal BLK1 output from the timing generation circuit 320, and the constant potential source 330 is changed.
As a result, the voltage signal VOL having the predetermined potential is supplied to the image signal line 400 instead of the image signal Vi. And especially
The data line driving circuit 101 causes, for example, the scan line No. 243 period (period ΔT)
In addition, the image signal line 400 and the sampling switch 302
The voltage signal VOL is applied to the data line 35 via. After that, a pause period (image signal V that is defined according to the signal BLK2 generated in the timing generation circuit 320).
i scan line No. During the period corresponding to 244 to 268), the clock signal CLX is kept at the timing generation circuit 32.
Paused by 0.

Although not shown in FIG. 5, scanning line No. is similarly applied to even fields (scanning line Nos. 264 to 525). 264 to 268 are components of the image signal Vi that are not displayed on the liquid crystal display unit 1a, and the scanning line No. Two
69 to 500 are image signals V displayed on the liquid crystal display unit 1a.
It is a component of i. Then, the scanning line No. In the period of 501 (period ΔT), the voltage signal VOL is applied to the data line 35 through the image signal line 400 and the data line driving circuit 101, and thereafter, in the rest period (scanning line No. of the image signal Vi.
502 to No. of the next frame. During the period (corresponding to 10), the clock signal CLX is
Paused by 20.

As a result, the sampling of the data line driving circuit 101 according to the clock signal CLX is suspended during the suspension period within the vertical blanking period. Therefore, the power consumption consumed as the liquid crystal applied voltage is reduced to the clock signal CL.
Compared with the conventional case where X is not paused, it can be reduced by the ratio of the pause period to the total time.

Then, as shown in FIG. 6, the rest period is
Since it is set after the voltage signal VOL is applied within the vertical blanking period, for example, even in the case of the scanning line (row) inversion driving and the field inversion driving method, after the odd field scanning or after the even field scanning. Regardless of the presence, the potential on the data line 35 in each idle period is basically a predetermined potential (that is, the potential of the voltage signal VOL). That is, unlike in the case of FIG. 16 described above, the potentials on the data lines do not differ during the idle periods that are successive.
It is possible to reduce the occurrence of flicker having a cycle that is twice the cycle of the rest period.

In this embodiment, the constant potential source 330 and the changeover switch 340 constitute an example of voltage supply means. However, the signal processing circuit 310 may constitute an example of such a power supply means. That is, the signal processing circuit 310 supplies the image signal Vi to the image signal line during the display period and also supplies the dummy signal of the predetermined potential to the image signal line instead of the image signal Vi during the vertical blanking period. You may comprise.

Particularly in this embodiment, the predetermined potential of the constant potential source 330 is set to a potential corresponding to the minimum value of the liquid crystal applied voltage in the liquid crystal display section 1a. Therefore, as shown in the lower two stages of FIG. 5, during the rest period of the clock signal CLX, the potential on the data line 35 corresponds to the minimum value of the liquid crystal applied voltage, that is, white in the normally white mode. It is regarded as a potential. As a result, the flicker as shown in FIG. 16 does not occur.

Furthermore, in the present embodiment, as shown in FIG. During the period 242 (period ΔT), the changeover switch 340 performs the switching operation based on the signal BLK1 from the timing generation circuit 320, so that the clock signal CLX is obtained after the CLY1 cycle or more, that is, one horizontal scanning period or more has elapsed from the start of the vertical blanking period. Is paused. Therefore, the voltage signal VOL supplied instead of the image signal Vi for at least one horizontal scanning, that is, for all the data lines 35, before the clock signal CLX is paused during the vertical blanking period. Sampling is performed, and the potentials on all the data lines 35 are set to the predetermined potential VOL during this period. Then, even during the rest period after the sampling switch 302 of the data line driving circuit 101 is opened, the potentials on all the data lines 35 are basically the predetermined potential V.
Maintained at OL.

As described above, according to this embodiment, the power consumption is about 7% (that is, the vertical feedback for the entire time is shorter than that of the conventional example in which the clock signal CLX is not paused during the vertical flyback period). The ratio occupied by the line period) is small. Moreover, flicker does not occur unlike the comparative example in which the clock signal is simply stopped during the vertical blanking period shown in FIG. As a result, according to the present embodiment, it is possible to achieve both high quality display images and energy saving at the same time.

(Second Embodiment) Next, a second embodiment will be described with reference to FIGS. 7 to 9. FIG. 7 is an overall block diagram of a liquid crystal device as another example of an electro-optical device including a liquid crystal panel including a drive circuit and a signal supply device that supplies an image signal, a clock signal, and the like to the drive circuit. FIG. 8A is a timing chart showing the pause timing of the clock signal CLX in the comparative example, and FIG. 8B is a timing chart showing the pause timing of the clock signal CLX in the present embodiment. Further, FIG. 9 is a timing chart showing various specific examples of the method of setting the potential of the data line in the clock pause period in the present embodiment. In this embodiment, as in the case of the first embodiment, the present invention
This is applied to a liquid crystal device of an active matrix drive system by FT drive. In FIG. 7, the same components as those in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

In FIG. 1, the liquid crystal device 200 includes a liquid crystal display section 1a, a data line driving circuit 101, and a scanning line driving circuit 1.
04 and a sampling circuit 301.

On the other hand, the signal supply device 300 'is composed of a signal processing circuit 310' and a timing generation circuit 320 '.

In the present embodiment, particularly, the signal processing circuit 31
0'processes the image signal Vi into a format corresponding to odd and even field scanning, and the polarities of the liquid crystal applied voltages applied to the liquid crystal portions in the plurality of pixel portions constituting the liquid crystal display portion 1a are at least the scanning line. After being processed so as to be inverted for each 31 and for each field, the image signal line 400
Is configured to supply.

Further, the timing generation circuit 320 'supplies the clock signal CLX to the data line drive circuit 101,
In the vertical blanking period of vertical scanning, the clock signal CLX is paused during the pause period in which the lengths differ by one horizontal scanning period after the odd field scanning and after the even field scanning.

The operation of the second embodiment configured as above will be described with reference to the timing charts of FIGS. 8 and 9.

First, when the image signal Vi is input from an external image signal source, the signal processing circuit 310 'processes the image signal Vi into a format corresponding to vertical scanning, and the polarity of the liquid crystal applied voltage is at least scanned. It is processed so as to be inverted line by line 31 and field by field. Then, the image signal Vi that has undergone these processes is supplied to the image signal line 400. In parallel with this, the timing generation circuit 320 '
Accordingly, the clock signal CLX is supplied to the data line driving circuit 10
1 is supplied. When the image signal Vi and the clock signal CLX are supplied in this way, the data line driving circuit 101 samples the image signal Vi according to the clock signal CLX, and the data signal is supplied to the plurality of data lines 35 as a data signal. It is applied respectively. At the same time, the scanning line driving circuit 104 sequentially applies scanning signals to the plurality of scanning lines 31. As a result, in the plurality of pixel portions in the liquid crystal display portion 1a, vertical scanning by the scanning line (row) inversion driving and the field inversion driving method is performed by the data signal and the scanning signal.

On the other hand, during the rest period within the vertical blanking period,
This clock signal CLX is the timing generation circuit 320 '.
Be paused by. As a result, since the sampling of the data line driving circuit 101 according to the clock signal CLX is suspended during the suspension period, the power consumption consumed as the liquid crystal applied voltage is the same as that in the conventional case where the clock signal CLX is not suspended. By comparison, it can be reduced by the ratio of the rest period to the total time. Especially, in the idle period, after the odd field scanning (the idle period = scanning line No. 244 to 268) and after the even field scanning (the idle period = scanning line No. 503).
Scan line No. of the next frame Since the length is different from that in 10) by one horizontal scanning period, the potential on the data line 35 in the idle period after the odd field scanning and the data line 35 in the idle period after the even field scanning are performed while performing the field inversion drive. The electric potential of is at least the electric potential of the same polarity.

More specifically, as shown in the comparative example of FIG. 8A, if the pause period has the same length after the odd field scan and after the even field scan, that is, , Scan line No. in odd field scan. 11-2
42 after the display period of No. 42. Data line 3 to the potential of 243
5 is fixed and scanning line No. is set in even field scanning. 26
No. after the display period of 9 to 500. When the data line 35 is fixed to the potential of 501, if field inversion drive is performed, a rest period (scanning line No.
244 to 268) on the data line 35 (see FIG. 8).
In (a), −polarity) and the idle period (scan line No. 502 to scan line No. of the next frame) after the even field scanning.
The polarity is different from the potential on the data line 35 in 10) (+ polarity in FIG. 8A). Therefore,
As in the example of FIG. 16 described above, a flicker having a cycle that is twice the cycle of the rest period occurs.

However, in the present embodiment, as shown in FIG.
As shown in (b), the length of the idle period differs by one horizontal scanning period after the odd field scanning and after the even field scanning, that is, during the idle period after the odd field scanning, the scan line No. 244 to 268, the scan line No. is in the idle period after the even field scanning. 503 to the scanning line No. of the next frame. Since it is a period corresponding to 10, the potentials on the data lines 35 in the idle period after the odd and even field scanning are set to the same polarity potential (both negative polarity in FIG. 8B). Therefore, the potential curve 50 on the image signal line of FIG.
As illustrated in 1 to 504, it is possible to reduce the occurrence of flicker having a cycle that is twice the cycle of the rest period as in the example of FIG.

In FIG. 9, the potential curve 501 indicates the scanning line No. of the odd field. 243 and the scan line No. of the even field. In the period corresponding to 502, a case is shown in which a negative polarity dummy image signal corresponding to the maximum value of the liquid crystal applied voltage (black level in normally white mode) is supplied from the signal processing circuit 310. In this case, in the vertical blanking period, the potential of the data line 35 is basically (that is, when a minute voltage drop due to current leakage is excluded from the data line, the pixel section TFT, the sampling switch, etc.). , The potential of this dummy image signal is maintained.

The potential curve 502 is the scanning line No. of the odd field. 242 and the scan line No. of the even field. In the period corresponding to 501, the case where the dummy image signal of + polarity corresponding to the maximum value of the liquid crystal applied voltage (black level in the normally white mode) is supplied from the signal processing circuit 310 is shown. In this case,
In the vertical blanking period, the potential of the data line 35 is basically maintained at the potential of this dummy image signal.

Therefore, these potential curves 501 and 502
When the image signal, the dummy image signal, and the clock signal CLX are supplied from the signal processing circuit 310 ′ and the timing generation circuit 320 ′ to the liquid crystal device 200 as shown in FIG. 8A and FIG. As in the example, it is possible to almost completely prevent the occurrence of flicker having a cycle that is twice the cycle of the rest period.

Further, in FIG. 9, potential curves 503 and 5
In the case indicated by the potential curves 501 and 502, reference numeral 04 indicates the data of the potential of the image signal at the end of each display period without supplying the dummy image signal immediately after the display period of each of the odd and even field scans. The case where the potential of the line 35 is fixed is shown in each case.

Like the potential curves 503 and 504, the signal processing circuit 3 outputs the image signal and the clock signal CLX.
Liquid crystal device 2 from 10 'and timing generation circuit 320'
00, the potential polarity on the data line 35 is at least the same during each idle period, so that the potential on the data line 35 is the same as in the example of FIG. 8A or FIG. It is possible to reduce the occurrence of flicker having a cycle twice as long as the cycle of the rest period due to swinging to potentials having different polarities in successive rest periods.

(Third Embodiment) Next, a third embodiment will be described with reference to FIG. Figure 10 here
FIG. 10A is a block diagram of the data line driving circuit in the third embodiment, and FIG. 10B is a timing chart thereof. In this embodiment, as in the case of the first and second embodiments, the present invention is applied to a liquid crystal device of an active matrix driving system by TFT driving. It should be noted that this embodiment includes the signal supply device 300 ′ according to the second embodiment shown in FIG.
The data line driving circuit 101 of the above embodiment is slightly modified (the liquid crystal display portion 1a, the scanning line driving circuit 10).
4, the sampling circuit 301 and the like are similarly configured. Therefore, here, the data line driving circuit, which is a characteristic part of the third embodiment, will be described, and description of other devices, circuits, and the like will be omitted.

In FIG. 10A, a data line driving circuit 101 'has a shift register circuit 101a similar to those in the first and second embodiments and a sampling circuit 301 including a plurality of sampling switches 302. ,
The clock signal C is provided for each of the plurality of sampling switches 302 and according to the blanking signal BLK supplied from the signal supply device 300 ′ (see FIG. 7).
During the idle period of LX, a plurality of sampling switches 302
Are simultaneously closed (in a sampling state), and a plurality of OR circuits 420 constituting an example of sampling switch control means are provided.

Next, the operation of the third embodiment configured as described above will be described.

First, the image signal Vi processed by the signal processing circuit 310 '(see FIG. 7) into a format corresponding to vertical scanning and processed so that the polarity of the liquid crystal applied voltage is inverted at least every scanning line 31, It is supplied to the sampling circuit 301 via the image signal line 400. In parallel with this, the timing generation circuit 320 ′ supplies the clock signal CLX to the shift register circuit 101a.
When the clock signal CLX is supplied in this manner, the shift register circuit 101a sequentially generates transfer signals corresponding to the plurality of data lines 35 in synchronization with the clock signal CLX. Then, the image signals Vi are sampled for each data line 35 by the plurality of sampling switches 302 according to this transfer signal, and are applied to the data lines 35 as data signals, respectively. At the same time, the scanning line drive circuit 101 (not shown) (see FIG. 7) sequentially applies scanning signals to the plurality of scanning lines 31. As a result, in the plurality of pixel portions in the liquid crystal display unit 1a, vertical scanning by the scanning line (row) inversion driving method is performed by the data signal and the scanning signal.

On the other hand, during the rest period within the vertical blanking period,
This clock signal CLX is the timing generation circuit 320 '.
Be paused by. As a result, during the pause period, the high frequency liquid crystal voltage applying operation by the shift register circuit 101a and the sampling circuit 301 according to the clock signal CLX is paused. Therefore, the power consumption consumed as the liquid crystal applied voltage can be reduced by the ratio of the pause period to the entire time, as compared with the conventional case where the clock signal is not paused.

In particular, in the idle period, the timing generation circuit 3 is connected via the sampling switch drive signal line 410.
The blanking signal BLK supplied from 20 ′ is supplied to the sampling switches 302 via the respective OR circuits 420, so that the sampling switches 302 are closed all at once, and the image signals Vi are sent all at once to the plurality of data lines. As shown in FIG. 10B, the potential on the data line 35 during the rest periods T1 and T2 is a potential whose polarity is inverted every period equal to one horizontal scanning period. That is, unlike the example of FIG. 16 described above, the potentials on the data line 35 are not fixed to different values in successive idle periods, so that a flicker having a period twice the period of the idle period is generated. Occurrence can be reduced.

Particularly in the present embodiment, the signal processing circuit 31
0'is configured such that the polarity is inverted in one horizontal scanning period and a dummy image signal of a predetermined potential is supplied to the image signal line instead of the image signal Vi during the rest period. Therefore, during the rest period, the polarity is inverted in one horizontal scanning period and a dummy image signal of a predetermined potential is supplied to the image signal line instead of the image signal Vi, so that the data line 35 on each of the rest periods is stopped. Is set to a potential whose polarity is inverted every period equal to one horizontal scanning period, so that the occurrence of flicker described above can be reduced. As the dummy image signal in this case,
Since the potential is set to correspond to the maximum value of the liquid crystal applied voltage (that is, black display in the normally white mode), it is possible to effectively reduce the occurrence of flicker.

As described above, according to the third embodiment, it is possible to reduce flicker and power consumption.

In each of the above embodiments, the pixel electrode 1
An example of a pixel portion is configured from 1 and the TFT 30. However, the pixel portion is not limited to this example. For example, one of the data line 35 and the scanning line 31 is provided on the counter substrate as a counter electrode, and the other of the data line 35 and the scanning line 31 formed on the TFT array substrate 1 is disposed between the pixel electrode 11. By interposing two-terminal type non-linear elements such as TFD driving elements each having a bidirectional diode characteristic, another example of the pixel portion may be configured from the counter electrode, the pixel electrode 11 and the two-terminal type non-linear element. Good. In addition, the present embodiment can be applied to various switching elements, further various liquid crystal materials (liquid crystal phases), operation modes, liquid crystal alignments, driving methods, and the like.

(Electronic Device) Next, an embodiment of an electronic device including the liquid crystal device 200 described in detail above will be described with reference to FIGS. 11 to 15.

First, FIG. 11 shows the liquid crystal device 200 as described above.
1 shows a schematic configuration of an electronic device equipped with.

In FIG. 11, the electronic equipment includes a display information output source 1000 and the above-mentioned signal supply device 300 or 300 '.
Corresponding to the display information processing circuit 1002, the driving circuit 1004 including the scanning line driving circuit 104 and the data line driving circuit 101, the liquid crystal panel 10 constituting an example of the liquid crystal display unit 1a, the clock generating circuit 1008, and the power supply circuit. 1010 is provided. Display information output source 1
000 is a ROM (Read Only Memory), a RAM (Ra
ndom access memory), a memory such as an optical disk device, a tuning circuit, and the like, and outputs display information such as an image signal of a predetermined format to the display information processing circuit 1002 based on the clock signal from the clock generation circuit 1008. The display information processing circuit 1002 is configured to include various known processing circuits such as an amplification / polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and a display input based on a clock signal. Digital signals are sequentially generated from the information and output to the drive circuit 1004 together with the clock signal CLK. Drive circuit 1004
Drives the liquid crystal panel 10 by the driving method described above.
The power supply circuit 1010 supplies a predetermined power supply to each of the above circuits. The driving circuit 1004 may be mounted on the TFT array substrate that constitutes the liquid crystal panel 10, or the display information processing circuit 1002 may be mounted in addition to this.

Next, FIG. 12 to FIG. 15 show specific examples of the electronic apparatus configured as described above.

In FIG. 12, a liquid crystal projector 1100, which is an example of an electronic device, is provided with three liquid crystal display modules including the liquid crystal panel 10 in which the drive circuit 1004 described above is mounted on a TFT array substrate. The projection type projector is used as the valves 100R, 100G and 100B. In the liquid crystal projector 1100, the white light source lamp unit 110 is used.
When the projection light is emitted from 2, light is divided into light components R, G, and B corresponding to the three primary colors of RGB inside the light guide 1104 by the two dichroic mirrors 1108 via the plurality of mirrors 1106, The light valves 100R, 100G, and 100B corresponding to the respective colors are introduced. And the light valves 100R, 100G and 1
The light components respectively corresponding to the three primary colors modulated by 00B are combined again by the dichroic prism 1112 and then projected as a color image on a screen or the like via the projection lens 1114.

In FIG. 13, a laptop personal computer 1200 which is another example of an electronic apparatus includes the above-mentioned liquid crystal panel 10 in a top cover case, and further houses a CPU, a memory, a modem and the like. It has a main body 1204 in which a keyboard 1202 is incorporated.

In FIG. 14, another example of a pager 1300 of an electronic apparatus is a backlight 1306a in which a liquid crystal panel 10 which is a liquid crystal display module in which the above-mentioned drive circuit 1004 is mounted on a TFT array substrate in a metal frame 1302. Including light guide 1306, circuit board 13
08, first and second shield plates 1310 and 131
It is housed with two, two elastic conductors 1314 and 1316, and a film carrier tape 1318.
In the case of this example, the display information processing circuit 1002 (see FIG.
1) may be mounted on the circuit board 1308 or may be mounted on the TFT array substrate of the liquid crystal panel 10. Further, the above-mentioned drive circuit 1004 can be mounted on the circuit board 1308.

Since the example shown in FIG. 14 is a pager, a circuit board 1308 and the like are provided. However, the drive circuit 1004 and further the display information processing circuit 1002
In the case of a liquid crystal panel 10 which is mounted with a liquid crystal display module, a liquid crystal device in which the liquid crystal panel 10 is fixed in a metal frame 1302 is used as a liquid crystal device, or in addition, a light guide 1306 is incorporated in a backlight type liquid crystal. The device can be produced, sold, used, and so on.

Further, as shown in FIG. 15, the drive circuit 100
In the case of the liquid crystal panel 10 in which the display information processing circuit 1002 and the display information processing circuit 1002 are not mounted, the IC 1324 including the driving circuit 1004 and the display information processing circuit 1002 is the polyimide tape 132.
TCP (Tape Carrier Package) 1 mounted on 2
It is also possible to physically and electrically connect to 320 via an anisotropic conductive film provided in the peripheral portion of the TFT array substrate 1 to produce, sell, or use as a liquid crystal device.

In addition to the electronic devices described with reference to FIGS. 12 to 15, liquid crystal televisions, viewfinder type or monitor direct-view type video tape recorders, car navigation devices, electronic notebooks, calculators, word processors, workstations. , Mobile phones, videophones, POS terminals,
An example of the electronic device shown in FIG. 11 is a device equipped with a touch panel.

[0112]

As described in detail above, according to the drive circuit of the electro-optical device of the present invention, the power consumption can be reduced by suspending the clock signal during the vertical retrace period, and the field or frame inversion can be performed. Even when various inversion driving methods such as a driving method, a scanning line (row) inversion driving method, and a dot inversion method are adopted, the potential on the data line in each idle period can be set to a predetermined potential, or at least on the data line in each idle period. Since the polarities of the potentials can be unified to be positive or negative, it is possible to reduce the occurrence of flicker having a cycle twice the cycle of the rest period. As a result, energy saving of the device and high quality of image display can be achieved at the same time.

Further, according to the electronic device of the present invention, various electronic devices such as a liquid crystal projector, a personal computer, a pager, etc. capable of displaying high-quality images and saving energy can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of a first embodiment.

FIG. 2 is a block diagram of a liquid crystal device included in the first embodiment.

3 is a circuit diagram (FIG. 3A) of a shift register circuit and an enable circuit included in a data line driver circuit included in the liquid crystal device of FIG. 2 and a timing chart thereof (FIG. 3).
(B)).

FIG. 4 is a block diagram (FIG. 3A) of a main part of a timing generation circuit included in the first embodiment and its timing chart (FIG. 3B).

FIG. 5 is a timing chart of one of various signals according to the first embodiment.

FIG. 6 is another timing chart of various signals according to the first embodiment.

FIG. 7 is a block diagram showing an overall configuration of a second embodiment.

FIG. 8 is a timing chart (FIG. 8A) in a comparative example of the second embodiment and a timing chart (FIG. 8B) in a specific example.

FIG. 9 is a timing chart in the second embodiment.

FIG. 10 is a block diagram (FIG. 10A) of a data line driving circuit included in the third embodiment and a timing chart thereof (FIG. 10B).

FIG. 11 is a block diagram showing a schematic configuration of an electronic device according to an embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a liquid crystal projector as an example of an electronic device.

FIG. 13 is a front view showing a personal computer as another example of the electronic apparatus.

FIG. 14 is an exploded perspective view showing a pager as an example of an electronic device.

FIG. 15 is a perspective view showing a liquid crystal device using TCP as an example of an electronic device.

FIG. 16 is a timing chart for explaining problems in a conventional liquid crystal device.

[Explanation of symbols]

1 ... TFT array substrate 1a ... Liquid crystal display section 11 ... Pixel electrode 31 ... Scan line (gate electrode) 35 ... Data line (source electrode) 101, 101 '... Data line drive circuit 101a ... Shift register circuit 104 ... Scan line drive circuit 112 ... Enable circuit 200 ... Liquid crystal device 301 ... Sampling circuit 302 ... Sampling switch 300, 300 '... Signal supply device 310, 310 '... Signal processing circuit 320, 320 '... Timing generation circuit 330 ... Constant potential source 340 ... switch

Continuation of the front page (56) Reference JP-A-9-212138 (JP, A) JP-A-9-330061 (JP, A) JP-A-10-11032 (JP, A) JP-A-10-214064 (JP , A) JP-A-7-175454 (JP, A) JP-A-6-12035 (JP, A) JP-A-1-128098 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB) Name) G09G 3/00-3/38 G02F 1/133 505-580 H04N 5/66-5/74

Claims (10)

(57) [Claims] 1. A plurality of data lines and a plurality of scanning lines arranged in a matrix, switching means provided corresponding to intersections of the plurality of data lines and the plurality of scanning lines, and the switching means. A pixel electrode connected to the data line, data line driving means for sampling an image signal supplied via an image signal line in accordance with a clock signal and applying the data signal to the plurality of data lines, and a scanning signal for the plurality of scanning lines. Is a drive circuit of an electro-optical device including a scan line drive circuit that supplies the scan line drive circuit, the polarity of the applied voltage applied to the liquid crystal portion via the pixel electrode at every vertical scan period and at least every scan line. A signal processing means for supplying the image signal line after processing the image signal so as to invert, and a voltage signal having the same fixed potential in each vertical blanking period instead of the image signal. And a voltage supply means for supplying the clock signal to the data line driving means, and supplying the clock signal during a predetermined period within the vertical blanking period after the voltage signal is applied to the data line. A drive circuit for an electro-optical device, comprising: a clock supply control unit that pauses. 2. The voltage supply means comprises switch means for selectively connecting the constant potential source of the fixed potential and the signal processing means to the image signal line. Drive circuit of the electro-optical device of. 3. The signal processing means includes the voltage supply means, and supplies the dummy signal of the fixed potential to the image signal line instead of the image signal during the vertical blanking period. The drive circuit for the electro-optical device according to claim 1. 4. The electro-optical device according to claim 1, wherein the voltage supply unit supplies a potential corresponding to the minimum value of the applied voltage as the fixed potential. Drive circuit. 5. A plurality of data lines and a plurality of scanning lines arranged in a matrix, switching means provided corresponding to the intersections of the plurality of data lines and the plurality of scanning lines, and the switching means. A pixel electrode connected to the data line, data line driving means for sampling an image signal supplied via an image signal line in accordance with a clock signal and applying the data signal to the plurality of data lines, and a scanning signal for the plurality of scanning lines. A driving circuit for an electro-optical device, comprising: a scanning line driving circuit for supplying a scanning line driving circuit, wherein the polarities of the applied voltages respectively applied to the liquid crystal portions via the pixel electrodes are inverted at least every scanning line and every field. Signal processing means for supplying the image signal line to the image signal line after processing the image signal, and supplying the clock signal to the data line driving means, and an odd number of lines in the vertical blanking period. A clock supply control unit that suspends the clock signal during a predetermined period in which the lengths differ by one horizontal scanning period after the field scan and after the even field scan, and the signal processing unit includes the clock signal during the vertical blanking period. A drive circuit for an electro-optical device, characterized in that a fixed potential having the same polarity is supplied to an image signal line. 6. The electro-optical device according to claim 5, wherein the signal processing unit supplies the dummy signal of the fixed potential to the image signal line instead of the image signal during the vertical blanking period. Device drive circuit. 7. The drive circuit for an electro-optical device according to claim 6, wherein the signal processing unit supplies the dummy signal with the potential corresponding to the maximum value of the applied voltage as the fixed potential. 8. An electronic apparatus comprising the electro-optical device drive circuit according to claim 1 and the electro-optical device. 9. A plurality of data lines and a plurality of scanning lines arranged in a matrix, switching means provided corresponding to the intersections of the plurality of data lines and the plurality of scanning lines, and the switching means. A pixel electrode connected to the data line, data line driving means for sampling an image signal supplied via an image signal line in accordance with a clock signal and applying the data signal to the plurality of data lines, and a scanning signal for the plurality of scanning lines. And a scanning line driving circuit for supplying a scanning line driving circuit, wherein the polarities of the applied voltages respectively applied to the liquid crystal portions via the pixel electrodes are vertical scanning periods and at least for each scanning line. After the image signal is processed so as to be inverted, it is supplied to the image signal line, and after the voltage signal of the same fixed potential is supplied to the data line via the image signal line in each vertical blanking period, The method of driving an electro-optical device characterized in that it temporarily pause serial clock signal. 10. A plurality of data lines and a plurality of scanning lines arranged in a matrix, switching means provided corresponding to the intersections of the plurality of data lines and the plurality of scanning lines, and the switching means. A pixel electrode connected to the data line, data line driving means for sampling an image signal supplied via the image signal line in accordance with a clock signal and applying the data signal to the plurality of data lines, and a scanning signal for the plurality of scanning lines. A driving method of an electro-optical device, comprising: a scanning line driving circuit for supplying the scanning lines, wherein the polarities of applied voltages applied to the liquid crystal portions via the pixel electrodes are inverted at least every scanning line and every field. After the image signal is processed as described above, it is supplied to the image signal line, the clock signal is supplied to the data line driving means, and odd field scanning is performed in the vertical blanking period. And after the even field scanning, the clock signal is paused in a predetermined period having different horizontal scanning periods, and a fixed potential having the same polarity is supplied to the image signal line in the vertical blanking period. And a method for driving an electro-optical device.