JP3488826B2 - Multi-cavity board for wiring board - Google Patents

Multi-cavity board for wiring board

Info

Publication number
JP3488826B2
JP3488826B2 JP11758198A JP11758198A JP3488826B2 JP 3488826 B2 JP3488826 B2 JP 3488826B2 JP 11758198 A JP11758198 A JP 11758198A JP 11758198 A JP11758198 A JP 11758198A JP 3488826 B2 JP3488826 B2 JP 3488826B2
Authority
JP
Japan
Prior art keywords
insulating layer
wiring board
wiring
opening
electronic component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP11758198A
Other languages
Japanese (ja)
Other versions
JPH11312851A (en
Inventor
誠 橋元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP11758198A priority Critical patent/JP3488826B2/en
Publication of JPH11312851A publication Critical patent/JPH11312851A/en
Application granted granted Critical
Publication of JP3488826B2 publication Critical patent/JP3488826B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structure Of Printed Boards (AREA)

Description

【発明の詳細な説明】 【0001】 【発明の属する技術分野】本発明は、半導体素子や水晶
振動子等の電子部品を搭載するための配線基板領域が広
面積の母基板中に縦横に多数個配列形成された配線基板
用多数個取り基板に関するものである。 【0002】 【従来の技術】従来、半導体素子や水晶振動子等の電子
部品を搭載するための配線基板は、例えば、酸化アルミ
ニウム質焼結体等の電気絶縁材料から成る略平板状の絶
縁基体の上面中央部から下面にかけて、電子部品の電極
が接続されるタングステンやモリブデン等の高融点金属
粉末メタライズから成る配線導体が被着されるととも
に、この絶縁基体の上面に電子部品を収容する凹部を形
成するための開口を有する絶縁枠体が積層されて成り、
絶縁基体と絶縁枠体とで形成される凹部内に電子部品を
収容するとともに、この電子部品の電極をボンディング
ワイヤや半田等の電気的接続手段を介して配線導体に電
気的に接続し、しかる後、絶縁枠体の上面に凹部を塞ぐ
ようにして平板状の蓋体を接合し、凹部内の電子部品を
気密封止することによって製品としての電子装置とされ
ていた。 【0003】ところで、このような配線基板は、近時の
電子装置の小型化の要求に伴ってその大きさが数mm角
程度の極めて小さなものとなってきており、多数個の配
線基板の取り扱いを容易とするために、また配線基板お
よび電子装置の製作を効率よく行なうために、1枚の広
面積の母基板中から多数個の配線基板を同時集約的に得
るようになした、いわゆる多数個取り基板の形態で製作
される。 【0004】この配線基板用多数個取り基板は、配線基
板の絶縁基体を形成するための広面積の下絶縁層と配線
基板の絶縁枠体を形成するための広面積の上絶縁層とが
積層されることによりその母基板が形成されており、こ
の母基板の中央部に配線基板となる配線基板領域が多数
個縦横に配列形成されている。そして、各配線基板領域
における下絶縁層の上面から下面にかけては配線導体が
所定パターンに被着形成されており、また各配線基板領
域における上絶縁層には下絶縁層との間で電子部品を収
容するための凹部を形成する開口が形成されている。 【0005】そして、この配線基板用多数個取り基板
は、電子部品を各配線基板領域の下絶縁層上面に被着さ
れた配線導体に対して所定の位置関係となるように各配
線基板領域の凹部内に位置合わせして収容するととも
に、この各配線基板領域の凹部内に収容された電子部品
の電極と各配線基板領域の下絶縁層上面に被着された配
線導体とをボンディングワイヤや半田等の電気的接続手
段を介して電気的に接続し、しかる後、例えば金属から
成る蓋体を各配線基板領域の上絶縁層上面に、この上絶
縁層の各開口の周囲に所定の封止幅を有するようにして
位置合わせして接合し、最後に母基板を各配線基板領域
毎に分割することによって多数個の電子装置が同時集約
的に製作される。 【0006】ここで、この配線基板用多数個取り基板に
おいて各配線基板領域の凹部内に電子部品を位置合わせ
したり、各配線基板領域の上絶縁層上面に蓋体を位置合
わせするには、例えば母基板の外周部に捨て代領域を設
けるとともに、この捨て代領域における上絶縁層の上面
に、上絶縁層の各配線基板領域の開口に対して一定の位
置関係にあるタングステンやモリブデン等の高融点金属
粉末メタライズから成る位置合わせ用マークを印刷によ
り被着させておくとともに、この位置合わせ用マークを
基準として各配線基板領域の凹部の位置を算出し、これ
に基づいて電子部品と配線導体とを、および蓋体と開口
とを位置合わせする方法が採用されている。 【0007】なお、このような配線基板用多数個取り基
板は、従来周知のセラミックグリーンシート積層法によ
って製作される。 【0008】具体的には、まず、下絶縁層となるセラミ
ックグリーンシートおよび上絶縁層となるセラミックグ
リーンシートを準備する。 【0009】次に、下絶縁層となるセラミックグリーン
シートの各配線基板領域となる領域に配線導体の導出路
となる貫通孔を穿孔するとともに、上絶縁層となるセラ
ミックグリーンシートの各配線基板領域となる領域に凹
部を形成するための開口を打ち抜く。 【0010】次に、下絶縁層となるセラミックグリーン
シートの上下面および貫通孔内に配線導体となる金属ペ
ーストを従来周知のスクリーン印刷法により印刷すると
ともに、上絶縁層となるセラミックグリーンシート外周
部の捨て代領域となる領域上面に、位置合わせ用マーク
となる金属ペーストを各配線基板領域の凹部を形成する
ための開口と一定の位置関係になるように従来周知のス
クリーン印刷法により印刷塗布する。 【0011】そして最後に、下絶縁層となるセラミック
グリーンシートの上面に上絶縁層となるセラミックグリ
ーンシートを積層してセラミックグリーンシート積層体
となすとともに、このセラミックグリーンシート積層体
を約1600℃の高温で焼成することによって製作される。 【0012】 【発明が解決しようとする課題】しかしながら、この従
来の配線基板用多数個取り基板によれば、位置合わせ用
マークは、配線導体が被着されている下絶縁層とは異な
る上絶縁層の上面にスクリーン印刷により被着形成され
ていることから、下絶縁層上面に被着された配線導体と
の間に両者の印刷ずれや下絶縁層と上絶縁層との積層ず
れ等よる位置関係のばらつきが発生する。また、上絶縁
層の各開口に対しても印刷ずれによる位置関係のばらつ
きが発生する。 【0013】これらの位置関係のばらつきは200 〜500
μm程度であり、そのため、近時の小型高密度化した配
線基板用多数個取り基板においては、上絶縁層の上面に
被着された位置合わせ用マークを基準として電子部品を
各配線基板領域の凹部内に位置合わせすると、電子部品
の電極と下絶縁層の配線導体との位置がずれてしまい、
その結果、電子部品の電極と配線導体とを電気的に正確
に接続することができなくなるという問題点があった。
また、この上絶縁層に被着された位置合わせマークを基
準として蓋体を各配線基板領域の上絶縁層上面に位置合
わせすると、蓋体と上絶縁層の各開口との位置関係がず
れてしまい、その結果、上絶縁層の各開口の周囲に所定
の封止幅を設けることができずに、得られる電子装置の
気密信頼性が低いものとなってしまうという問題点があ
った。 【0014】本発明は、かかる従来の問題点に鑑み案出
されたものであり、その目的は、下絶縁層に被着された
配線導体に対して電子部品を正確に位置合わせすること
ができ電子部品の電極と配線基板とを電気的に正確に接
続することができるとともに、上絶縁層の開口に対して
蓋体を正確に位置合わせすることができ気密信頼性の高
い電子装置を製造可能な配線基板用多数個取り基板を提
供することにある。 【0015】 【課題を解決するための手段】本発明の配線基板用多数
個取り基板は、電子部品の電極が接続される配線導体が
被着された多数個の配線基板領域が上面中央部に配列さ
れ、前記配線導体と一定の位置関係を有する位置合わせ
用マークが上面外周部に配置された下絶縁層と、該下絶
縁層の上面に積層された、前記各配線基板領域に対応し
て前記電子部品を収容する凹部を形成するための第1の
開口および前記位置合わせ用マークを露出させる前記第
1の開口と同形の第2の開口を有する上絶縁層とから成
ることを特徴とするものである。 【0016】本発明の配線基板用多数個取り基板によれ
ば、電子部品の電極が接続される配線導体が被着された
多数個の配線基板領域が上面中央部に縦横に配列された
下絶縁層の上面外周部の前記配線基板領域の配列の中心
線の延長線上に配線導体と一定の位置関係を有する位置
合わせ用マークが配置されていることから、下絶縁層の
各配線基板領域に被着された配線導体と下絶縁層の上面
外周部に被着された位置合わせ用マークとの相互位置関
係のばらつきが極めて小さい。そして、上絶縁層にはこ
の位置合わせ用マークを露出させる第2の開口が形成さ
れていることから、この第2の開口から露出した位置合
わせ用マークを基準として、下絶縁層の各配線基板領域
に被着された配線導体と電子部品とを極めて高精度に位
置合わせすることができる。 【0017】さらに、本発明の配線基板用多数個取り基
板によれば、第1の開口と第2の開口とは、ともに上絶
縁層に形成されていることから互いの位置関係のばらつ
きを極めて小さいものとすることができる。そして、蓋
体を上絶縁層の第1の開口に位置合わせする際の基準と
して第2の開口を用いることにより、第1の開口に対し
て蓋体を極めて高精度に位置合わせすることができる。 【0018】 【発明の実施の形態】以下、本発明の配線基板用多数個
取り基板を添付の図面を基に詳細に説明する。 【0019】まず、本発明の配線基板用多数個取り基板
により製作される電子装置について説明する。 【0020】図4は本発明の配線基板用多数個取り基板
から得られる配線基板を用いて製作される電子装置の一
例を示す断面図である。 【0021】図4において、1は絶縁基体、2は絶縁枠
体であり、これらで電子部品4を搭載するための配線基
板3が構成される。 【0022】絶縁基体1は、例えば酸化アルミニウム質
焼結体や窒化アルミニウム質焼結体・ムライト質焼結体
・窒化珪素質焼結体・炭化珪素質焼結体・ガラスセラミ
ックス等の電気絶縁材料から成る略四角形状の平板であ
り、その上面中央部から下面にかけて、電子部品4の電
極が接続される配線導体5が被着されている。 【0023】配線導体5は、例えばタングステンやモリ
ブデン・モリブデン−マンガン、あるいは銅・銀・銀−
パラジウム等の金属粉末メタライズから成り、その絶縁
基体1の上面中央部位には、電子部品4の電極が例えば
ボンディングワイヤ6を介して電気的に接続される。 【0024】絶縁基体1の上面には、絶縁基体1の上面
中央部に被着された配線導体5を露出させるようにして
絶縁枠体2が積層されている。 【0025】絶縁枠体2は、例えば酸化アルミニウム質
焼結体や窒化アルミニウム質焼結体・ムライト質焼結体
・窒化珪素質焼結体・炭化珪素質焼結体・ガラスセラミ
ックス質焼結体等の電気絶縁材料から成る略四角形状の
枠体であり、その中央部に開口2aを有しており、この
開口2aの内壁面と絶縁基体1上面とで電子部品4を収
容するための凹部3aが形成される。 【0026】そして、この配線基板3は、絶縁基体1と
絶縁枠体2とで形成される凹部内に電子部品4を収容
し、電子部品4の電極と絶縁基体1の配線導体5とをボ
ンディングワイヤ6を介して電気的に接続し、しかる
後、絶縁枠体2上面に開口2aを塞ぐようにして例えば
鉄−ニッケル−コバルト合金等の金属から成る蓋体7を
接合させ、絶縁基体1と絶縁枠体2と蓋体7とから成る
容器の内部に電子部品4を気密に封止することによって
製品としての電子装置となる。 【0027】次に、上述の配線基板3を製作するための
本発明の配線基板用多数個取り基板について説明する。 【0028】図1は本発明の配線基板用多数個取り基板
の実施の形態の一例を示す断面図であり、図2は図1に
示す配線基板用多数個取り基板の上面図である。 【0029】図1および図2に示すように、本発明の配
線基板用多数個取り基板は、配線基板3の絶縁基体1を
形成するための下絶縁層11と、配線基板3の絶縁枠体2
を形成するための上絶縁層12とが積層された、縦横が数
cm〜数十cmの広面積の略四角平板状の母基板10から
成り、その中央部には配線基板3となる配線基板領域13
が縦横に多数配列されており、また母基板10の外周部に
はこの配線基板用多数個取り基板の取り扱いを容易とす
るための枠状の捨て代領域14が形成されている。 【0030】母基板10は、下絶縁層11および上絶縁層12
がともに酸化アルミニウム質焼結体や窒化アルミニウム
質焼結体・ムライト質焼結体・窒化珪素質焼結体・炭化
珪素質焼結体・ガラスセラミックス等の電気絶縁材料か
ら成り、下絶縁層11となるセラミックグリーンシートと
上絶縁層12となるセラミックグリーンシートとを積層し
て焼成することによって製作されている。 【0031】母基板10を構成する下絶縁層11は、その各
配線基板領域13の上面中央部から下面にかけてタングス
テンやモリブデン・モリブデン−マンガン・銅・銀・銀
−パラジウム等の金属粉末メタライズから成る配線導体
5が被着されている。 【0032】配線導体5は、下絶縁層11となるセラミッ
クグリーンシートに配線導体5の導出路となる貫通孔を
形成しておくとともにこのセラミックグリーンシートの
上面から貫通孔を介して下面にかけて配線導体5となる
金属ペーストを従来周知のスクリーン印刷法を採用して
所定のパターンに印刷塗布しておくことによって形成さ
れる。 【0033】また、下絶縁層11には、その捨て代領域14
の上面に、下絶縁層11の各配線基板領域13の上面に被着
された配線導体5と一定の位置関係にある位置合わせ用
マーク15が被着されている。 【0034】位置合わせ用マーク15は、例えば配線基板
領域13の配列の方向と一致する方向に延びる2つの直線
パターンが直交した十字形であり、配線基板領域13の配
列のうち最外周の並びの中心線の延長線上に位置合わせ
用マーク15の一方のパターンの中心線が一致するように
配置されている。 【0035】位置合わせマーク15は、配線導体5と同じ
くタングステンやモリブデン・モリブデン−マンガン・
銅・銀・銀−パラジウム等の金属粉末メタライズから成
り、下絶縁層11となるセラミックグリーンシートの上面
に配線導体5となる金属ペーストを印刷塗布するのと同
時に所定のパターンに印刷塗布しておくことによって形
成される。 【0036】位置合わせ用マーク15は、下絶縁層11とな
るセラミックグリーンシートの上面に位置合わせ用マー
ク15となる金属ペーストを配線導体5となる金属ペース
トと同時に印刷することにより形成されることから、下
絶縁層11上面に被着された配線導体5との位置関係のば
らつきが約50μm以下と極めて小さい。従って、この位
置合わせ用マーク15を基準にして電子部品4を下絶縁層
11の各配線基板領域13上面に被着された配線導体5に位
置合わせすると、電子部品4と配線導体5とを極めて高
精度に位置合わせすることができ、その結果、電子部品
4の電極と下絶縁層11の各配線基板領域13の上面に被着
された配線導体5とを電気的に正確に接続することが可
能となる。 【0037】また、母基板10を構成する上絶縁層12は、
その各配線基板領域13に下絶縁層11の配線基板領域13に
対応して電子部品4を収容する凹部3aを形成するため
の第1の開口12aが形成されている。 【0038】上絶縁層12に形成された第1の開口12a
は、下絶縁層11との間で電子部品4を収容するための凹
部3aを形成するとともに、下絶縁層11の各配線基板領
域13の上面中央部に被着された配線導体5を露出させて
いる。そして、各配線基板領域13の凹部3a内に電子部
品4を収容するとともに、この電子部品4の電極と各配
線基板領域13の配線導体5とをボンディングワイヤ6を
介して接続することにより電子部品4の電極と各配線基
板領域13の配線導体5とが電気的に接続され、上絶縁層
12の上面の各開口12a周辺に各凹部3aを覆うようにし
て蓋体7を接合させることにより凹部3a内に電子部品
4が気密に収容される。 【0039】さらに、上絶縁層12の捨て代領域14には、
第1の開口12aと一定の位置関係にあり、かつ下絶縁層
11の捨て代領域14上面に形成された位置合わせ用マーク
15を露出させる、例えば略四角形状の第2の開口12bが
形成されている。 【0040】上絶縁層12の捨て代領域14に形成された第
2の開口12bは、下絶縁層11の捨て代領域14上面に形成
された位置合わせ用マーク15を露出させることにより位
置合わせ用マーク15を外部から認識可能としている。ま
た、第1の開口12aと一定の位置関係を有していること
により、蓋体7を上絶縁層12の各配線基板領域13の第1
の開口12a周辺上面に接合する際に蓋体7を第1の開口
12aに対して位置合わせする際の基準として機能する。 【0041】なお、上絶縁層12に形成された第1の開口
12aおよび第2の開口12bは、ともに上絶縁層12となる
セラミックグリーンシートに従来周知の打ち抜き加工を
施すことにより同時に形成される。 【0042】上絶縁層12に形成された第1の開口12aと
第2の開口12bとは、ともに同じ層に打ち抜き加工によ
り同時に形成されていることから、両者間の位置関係の
ばらつきは約50μm以下と極めて小さい。従って、第2
の開口12bを基準とすることにより、蓋体7を第1の開
口12aに対して正確に位置合わせすることが可能とな
る。 【0043】次に、本発明の配線基板用多数個取り基板
を使用して電子装置を製造する方法について説明する。 【0044】まず、画像認識装置により、上絶縁層12の
第2の開口12b内に露出した位置合わせ用マーク15を認
識するとともに位置合わせ用マーク15の位置を検出す
る。そして、この検出した位置合わせ用マーク15の位置
を基準として、各配線基板領域13の下絶縁層11上面に被
着された配線導体5の位置を算出する。そして、この算
出された配線導体5の位置データを基に、自動機によ
り、電子部品4を各配線基板領域13の下絶縁層11上面に
被着された配線導体5に対して所定の位置関係となるよ
うに位置合わせして各配線基板領域13の凹部3a内に収
容するとともに、これらの電子部品4の電極と各配線基
板領域13の下絶縁層11上面に被着された配線導体5とを
ボンディングワイヤ6を介して電気的に接続する。 【0045】この場合、位置合わせ用マーク15は配線導
体5と同時に下絶縁層11の上面に被着形成されているこ
とから、下絶縁層11上面に被着された配線導体5との間
の位置関係のばらつきが極めて小さく、従って、この位
置合わせ用マーク15を基準として各配線基板領域13の下
絶縁層11上に被着された配線導体5に対して電子部品4
を正確に位置合わせすることができ、その結果、電子部
品4の電極と配線導体5とを電気的に正確に接続するこ
とができる。 【0046】次に、画像認識装置により、上絶縁層12に
形成された第2の開口12bを認識するとともに第2の開
口12bの位置を検出する。そして、この検出した第2の
開口12bの位置を基準として、各配線基板領域13の上絶
縁層12に形成された第1の開口12aの位置を算出する。
そして、この算出した第1の開口12aの位置データを基
に、各配線基板領域13の上絶縁層12上面に第1の開口12
aの周囲に所定の封止幅を有するように、自動機により
蓋体7を位置合わせするとともに接合する。 【0047】この場合、第2の開口12bは、第1の開口
12aと同時に上絶縁層12に打ち抜き形成されていること
から、第1の開口12aとの間の位置関係のばらつきが極
めて小さく、従って、この第2の開口12bを基準として
各配線基板領域13の上絶縁層12に形成された第1の開口
12aに対して蓋体7を正確に位置合わせすることがで
き、その結果、各配線基板領域13の凹部3a内部に電子
部品4を気密性高く封止することができる。 【0048】そして最後に、母基板10を各配線基板領域
13毎に分割すれば、多数の電子装置が同時集約的に製作
される。 【0049】なお、母基板10を各配線基板領域13毎に分
割するには、母基板10の上下面に各配線基板領域13の境
界に沿って所定深さの分割溝を予め形成しておき、この
分割溝に沿って母基板10をいわゆるチョコレートブレー
クする方法や、母基板10を各配線基板領域13の境界に沿
ってレーザやダイヤモンドカッターにより切断して分割
する方法が採用される。 【0050】かくして、本発明の配線基板用多数個取り
基板によれば、各配線基板領域13の下絶縁層11上面に被
着された配線導体5に対して電子部品4を正確に位置合
わせして電子部品4の電極と各配線基板領域13の配線導
体5とを電気的に正確に接続することができるととも
に、各配線基板領域13の上絶縁層12に形成された第1の
開口12aに対して蓋体7を正確に位置合わせして各配線
基板領域13の凹部3a内に電子部品4を気密性高く収容
することができ、配線導体5と電子部品4の電極が電気
的に正確に接続され、かつ電子部品4が気密信頼性高く
封止された電子装置を多数個同時集約的に製作すること
ができる。 【0051】なお、本発明は上述の実施の形態の一例に
限定されるものではなく、本発明の要旨を逸脱しない範
囲であれば種々の変更は可能である。例えば、上述の実
施の形態の例では位置合わせ用マーク15は配線基板領域
13の配列のうち最外周の並びに対応して配置されていた
が、図3に図2と同様の上面図で示すように、配線基板
領域13の配列の全ての並びに対応して配置されてもよ
い。さらに、位置合わせ用マーク15の形状は十字形に限
らず、円形や四角・三角等の他の形であってもよい。 【0052】 【発明の効果】以上説明したように、本発明の配線基板
用多数個取り基板によれば、電子部品の電極が接続され
る配線導体が被着された下絶縁層の上面外周部に配線導
体と一定の位置関係を有する位置合わせ用マークが配線
基板領域の配列の中心線の延長線上に配置されているこ
とから、下絶縁層の各配線基板領域に被着された配線導
体と下絶縁層の上面外周部に被着された位置合わせ用マ
ークとの相互位置関係のばらつきが極めて小さい。従っ
て、この位置合わせ用マークを基準として電子部品と配
線導体とを極めて高精度に位置合わせすることができ、
その結果、電子部品の電極と配線導体とを電気的に正確
に接続することが可能である。 【0053】また、本発明の配線基板用多数個取り基板
によれば、第1の開口と第2の開口とは、ともに上絶縁
層に形成されていることから互いの位置関係のばらつき
が極めて小さい。従って、第2の開口を基準として蓋体
と第1の開口とを高精度に位置合わせすることができ、
その結果、蓋体を各配線基板領域の上絶縁層上面に各第
1の開口周辺に所定の封止幅を設けて気密性高く接合す
ることができ、気密信頼性の高い電子装置を提供するこ
とができる。 【0054】以上により、本発明によれば、下絶縁層に
被着された配線導体に対して電子部品を正確に位置合わ
せすることができ、電子部品の電極と配線基板とを電気
的に正確に接続することができるとともに、上絶縁層の
開口に対して蓋体を正確に位置合わせすることができ、
気密信頼性の高い電子装置を製造可能な配線基板用多数
個取り基板を提供することができた。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board region for mounting electronic components such as semiconductor elements and quartz oscillators, which is provided on a large-sized mother board in a matrix. The present invention relates to a multi-cavity substrate for a wiring board, which is individually formed. 2. Description of the Related Art Conventionally, a wiring board for mounting electronic components such as a semiconductor element and a quartz oscillator has been used as a substantially flat insulating base made of an electrically insulating material such as an aluminum oxide sintered body. A wiring conductor made of a metal powder of a refractory metal such as tungsten or molybdenum to which the electrodes of the electronic component are connected is attached from the center to the lower surface of the upper surface of the substrate, and a concave portion for housing the electronic component is formed on the upper surface of the insulating base. An insulating frame having an opening for forming is formed by lamination,
An electronic component is accommodated in a concave portion formed by the insulating base and the insulating frame, and electrodes of the electronic component are electrically connected to wiring conductors through electrical connecting means such as a bonding wire or solder. Thereafter, a flat lid is joined to the upper surface of the insulating frame so as to cover the recess, and the electronic components in the recess are hermetically sealed, thereby providing an electronic device as a product. Incidentally, such a wiring board has recently become extremely small in size of about several mm square in accordance with the recent demand for miniaturization of electronic devices. In order to facilitate the production of the wiring board and the electronic device efficiently, a large number of wiring boards are simultaneously and intensively obtained from a single large-area mother board. It is manufactured in the form of an individual substrate. The multi-cavity substrate for a wiring board has a large-area lower insulating layer for forming an insulating base of the wiring board and a large-area upper insulating layer for forming an insulating frame of the wiring board. Thus, a mother board is formed, and a large number of wiring board regions to be a wiring board are vertically and horizontally arranged at the center of the mother board. Wiring conductors are formed in a predetermined pattern from the upper surface to the lower surface of the lower insulating layer in each wiring board region, and electronic components are formed between the lower insulating layer and the upper insulating layer in each wiring board region. An opening forming a recess for accommodating is formed. [0005] The multi-piece substrate for a wiring board has an electronic component in each wiring board area so that the electronic component has a predetermined positional relationship with respect to a wiring conductor attached to the upper surface of the lower insulating layer of each wiring board area. The electrodes of the electronic components housed in the recesses of the respective wiring board regions and the wiring conductors attached to the upper surface of the lower insulating layer of the respective wiring board regions are accommodated in the recesses while being aligned and housed in the recesses. After that, a lid made of, for example, a metal is sealed on the upper surface of the upper insulating layer of each wiring board region, and a predetermined sealing is formed around each opening of the upper insulating layer. A large number of electronic devices are manufactured simultaneously and intensively by aligning and joining them so as to have a width, and finally dividing the mother board into each wiring board area. Here, in order to align electronic components in the recesses of the respective wiring board regions and to position the lid on the upper surface of the upper insulating layer in the respective wiring board regions in the multi-cavity substrate for a wiring board, For example, while providing a waste margin area on the outer peripheral portion of the motherboard, tungsten, molybdenum, or the like having a fixed positional relationship with the opening of each wiring board area of the upper insulation layer is provided on the upper surface of the upper insulating layer in the waste margin area. Alignment marks made of high-melting metal powder metallization are applied by printing, and the positions of the recesses in each wiring board area are calculated based on the alignment marks. And the method of aligning the lid and the opening. [0007] Such a multi-cavity substrate for a wiring board is manufactured by a conventionally well-known ceramic green sheet laminating method. Specifically, first, a ceramic green sheet to be a lower insulating layer and a ceramic green sheet to be an upper insulating layer are prepared. Next, a through hole serving as a lead-out path for a wiring conductor is formed in a region serving as a wiring substrate region of the ceramic green sheet serving as a lower insulating layer, and a wiring substrate region of the ceramic green sheet serving as an upper insulating layer is provided. An opening for forming a concave portion is punched in a region to be formed. Next, a metal paste serving as a wiring conductor is printed on the upper and lower surfaces of the ceramic green sheet serving as the lower insulating layer and the inside of the through hole by a conventionally known screen printing method, and the outer peripheral portion of the ceramic green sheet serving as the upper insulating layer is provided. A metal paste serving as an alignment mark is printed and applied on the upper surface of the area serving as a disposal allowance area by a conventionally well-known screen printing method so as to have a fixed positional relationship with an opening for forming a concave portion of each wiring board area. . Finally, a ceramic green sheet serving as an upper insulating layer is laminated on an upper surface of the ceramic green sheet serving as a lower insulating layer to form a ceramic green sheet laminate. It is manufactured by firing at high temperature. However, according to the conventional multi-cavity substrate for a wiring board, the positioning mark has an upper insulating layer different from the lower insulating layer on which the wiring conductor is attached. Since it is formed by screen printing on the upper surface of the layer, the position due to printing misalignment between the wiring conductor and the lamination misalignment between the lower insulating layer and the upper insulating layer between the lower conductor and the wiring conductor adhered to the upper surface of the lower insulating layer Variations in the relationship occur. In addition, a positional deviation due to printing deviation occurs in each opening of the upper insulating layer. The variation in the positional relationship is 200 to 500
μm, so in recent recent multi-cavity circuit boards for miniaturized and high-density wiring boards, the electronic components are placed in each wiring board area with reference to the alignment mark attached on the upper surface of the upper insulating layer. If it is positioned in the recess, the position of the electrode of the electronic component and the wiring conductor of the lower insulating layer will shift,
As a result, there has been a problem that the electrodes of the electronic component and the wiring conductor cannot be electrically accurately connected.
When the lid is positioned on the upper surface of the upper insulating layer of each wiring board region with reference to the alignment mark attached to the upper insulating layer, the positional relationship between the lid and each opening of the upper insulating layer is shifted. As a result, a predetermined sealing width cannot be provided around each opening of the upper insulating layer, and there is a problem that the airtight reliability of the obtained electronic device is low. The present invention has been devised in view of such a conventional problem, and has as its object to accurately align an electronic component with a wiring conductor attached to a lower insulating layer. The electrodes of the electronic components can be electrically connected accurately to the wiring board, and the lid can be accurately positioned with respect to the opening in the upper insulating layer, making it possible to manufacture highly reliable electronic devices. It is an object of the present invention to provide a multi-cavity substrate for a wiring board. According to the present invention, there is provided a multi-piece board for a wiring board, wherein a plurality of wiring board areas on which wiring conductors to which electrodes of electronic components are connected are attached at a central portion of an upper surface. A lower insulating layer in which alignment marks having a certain positional relationship with the wiring conductors are arranged on the outer peripheral portion of the upper surface, and which are stacked on the upper surface of the lower insulating layer, correspond to the respective wiring board regions. A first opening for forming a recess for accommodating the electronic component, and an upper insulating layer having a second opening having the same shape as the first opening for exposing the alignment mark. Things. According to the multi-cavity substrate for a wiring board of the present invention, the lower insulating board in which a large number of wiring board regions on which wiring conductors to which electrodes of electronic parts are connected are attached is arranged vertically and horizontally at the center of the upper surface. Since alignment marks having a fixed positional relationship with the wiring conductors are arranged on the extension of the center line of the arrangement of the wiring board regions on the outer peripheral portion of the upper surface of the layer, each wiring board region of the lower insulating layer is covered. The variation in the mutual positional relationship between the attached wiring conductor and the alignment mark attached to the outer peripheral portion of the upper surface of the lower insulating layer is extremely small. Since the upper insulating layer has a second opening for exposing the alignment mark, each wiring board of the lower insulating layer is based on the alignment mark exposed from the second opening. The wiring conductor and the electronic component attached to the region can be positioned with extremely high precision. Further, according to the multi-cavity substrate for a wiring board of the present invention, since both the first opening and the second opening are formed in the upper insulating layer, the positional relationship between them is extremely small. It can be small. Then, by using the second opening as a reference when aligning the lid with the first opening of the upper insulating layer, the lid can be extremely accurately positioned with respect to the first opening. . DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a multi-piece substrate for a wiring board according to the present invention will be described in detail with reference to the accompanying drawings. First, an electronic device manufactured by using the multi-piece substrate for a wiring board of the present invention will be described. FIG. 4 is a sectional view showing an example of an electronic device manufactured using a wiring board obtained from the multi-piece wiring board for a wiring board according to the present invention. In FIG. 4, reference numeral 1 denotes an insulating base, 2 denotes an insulating frame, and these constitute a wiring board 3 on which electronic components 4 are mounted. The insulating base 1 is made of an electrically insulating material such as a sintered body of aluminum oxide, a sintered body of aluminum nitride, a sintered body of mullite, a sintered body of silicon nitride, a sintered body of silicon carbide, and a glass ceramic. And a wiring conductor 5 to which the electrode of the electronic component 4 is connected is attached from the center of the upper surface to the lower surface. The wiring conductor 5 is made of, for example, tungsten, molybdenum / molybdenum-manganese, or copper / silver / silver-
An electrode of the electronic component 4 is electrically connected to a central portion of the upper surface of the insulating base 1 through, for example, a bonding wire 6. An insulating frame 2 is laminated on the upper surface of the insulating substrate 1 so as to expose the wiring conductor 5 attached to the center of the upper surface of the insulating substrate 1. The insulating frame 2 is made of, for example, an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body, a silicon nitride sintered body, a silicon carbide sintered body, or a glass ceramic sintered body. A substantially rectangular frame made of an electrically insulating material such as that described above, has an opening 2a at the center thereof, and a recess for housing the electronic component 4 on the inner wall surface of the opening 2a and the upper surface of the insulating base 1. 3a is formed. The wiring board 3 accommodates the electronic component 4 in a recess formed by the insulating base 1 and the insulating frame 2, and bonds the electrodes of the electronic component 4 to the wiring conductors 5 of the insulating base 1. It is electrically connected via wires 6, and thereafter, a lid 7 made of a metal such as an iron-nickel-cobalt alloy is joined to the upper surface of the insulating frame 2 so as to cover the opening 2a. An electronic device as a product is obtained by hermetically sealing the electronic component 4 inside a container including the insulating frame 2 and the lid 7. Next, a multi-cavity substrate for a wiring board of the present invention for manufacturing the above-described wiring board 3 will be described. FIG. 1 is a sectional view showing an example of an embodiment of a multi-piece board for a wiring board according to the present invention, and FIG. 2 is a top view of the multi-piece board for a wiring board shown in FIG. As shown in FIGS. 1 and 2, the multi-piece substrate for a wiring board according to the present invention comprises a lower insulating layer 11 for forming the insulating base 1 of the wiring board 3, and an insulating frame of the wiring board 3. 2
Is formed of a substantially rectangular flat mother board 10 having a large area of several cm to several tens cm in length and width, and a wiring board 3 serving as a wiring board 3 in the center thereof. Region 13
Are arranged vertically and horizontally, and a frame-shaped throwaway area 14 is formed in the outer peripheral portion of the mother board 10 to facilitate handling of the multi-piece wiring board. The mother substrate 10 includes a lower insulating layer 11 and an upper insulating layer 12.
Are made of an electrically insulating material such as an aluminum oxide-based sintered body, an aluminum nitride-based sintered body, a mullite-based sintered body, a silicon nitride-based sintered body, a silicon carbide-based sintered body, or a glass ceramic, and the lower insulating layer 11 It is manufactured by laminating and firing a ceramic green sheet to be an upper insulating layer 12 and a ceramic green sheet to be an upper insulating layer 12. The lower insulating layer 11 constituting the mother substrate 10 is formed of a metal powder of metal such as tungsten or molybdenum / molybdenum-manganese / copper / silver / silver / palladium from the center of the upper surface to the lower surface of each wiring substrate region 13. The wiring conductor 5 is attached. The wiring conductor 5 has a through hole that is a lead-out path for the wiring conductor 5 formed in the ceramic green sheet that is to be the lower insulating layer 11 and extends from the upper surface of the ceramic green sheet to the lower surface through the through hole. The metal paste 5 is formed by printing and applying a predetermined pattern using a conventionally known screen printing method. Further, the lower insulating layer 11 has a waste margin region 14.
Is positioned on the upper surface of the lower insulating layer 11, a positioning mark 15 having a fixed positional relationship with the wiring conductor 5 provided on the upper surface of each wiring substrate region 13. The alignment mark 15 is, for example, a cross in which two linear patterns extending in a direction coinciding with the direction of the arrangement of the wiring board regions 13 are cross-shaped. The alignment mark 15 is arranged so that the center line of one of the patterns of the alignment mark 15 coincides with the extension of the center line. The alignment mark 15 is made of tungsten, molybdenum, molybdenum-manganese,
It is made of metal powder such as copper, silver, silver-palladium and the like, and a metal paste to be the wiring conductor 5 is printed and applied to the upper surface of the ceramic green sheet to be the lower insulating layer 11 in a predetermined pattern at the same time. Formed by The alignment marks 15 are formed by printing a metal paste for the alignment marks 15 on the upper surface of the ceramic green sheet for the lower insulating layer 11 at the same time as the metal paste for the wiring conductors 5. The variation in the positional relationship with the wiring conductor 5 attached to the upper surface of the lower insulating layer 11 is extremely small at about 50 μm or less. Therefore, the electronic component 4 is placed on the lower insulating layer with reference to the positioning mark 15.
When the electronic component 4 and the wiring conductor 5 are aligned with the wiring conductor 5 attached to the upper surface of each wiring substrate region 13 of the electronic component 11, the electronic component 4 and the wiring conductor 5 can be aligned with extremely high precision. It is possible to electrically and accurately connect the wiring conductor 5 attached to the upper surface of each wiring substrate region 13 of the lower insulating layer 11. The upper insulating layer 12 constituting the mother substrate 10 is
A first opening 12a for forming a recess 3a for accommodating the electronic component 4 is formed in each wiring board region 13 corresponding to the wiring board region 13 of the lower insulating layer 11. First opening 12a formed in upper insulating layer 12
Forms a recess 3 a for accommodating the electronic component 4 with the lower insulating layer 11, and exposes the wiring conductor 5 attached to the center of the upper surface of each wiring board region 13 of the lower insulating layer 11. ing. The electronic component 4 is accommodated in the recess 3 a of each wiring board region 13, and the electrodes of the electronic component 4 are connected to the wiring conductors 5 of each wiring board region 13 through the bonding wires 6, whereby the electronic components are connected. 4 and the wiring conductor 5 in each wiring board area 13 are electrically connected to each other, and the upper insulating layer
The electronic component 4 is hermetically accommodated in the concave portion 3a by joining the lid 7 so as to cover each concave portion 3a around each opening 12a on the upper surface of the 12. Further, in the disposal area 14 of the upper insulating layer 12,
A certain positional relationship with the first opening 12a, and a lower insulating layer
Positioning mark formed on the top surface of the discarding allowance area 14 of 11
For example, a second opening 12b having a substantially square shape is formed to expose the second opening 15b. The second opening 12b formed in the throw-away area 14 of the upper insulating layer 12 is used for exposing the alignment mark 15 formed on the upper surface of the throw-away area 14 of the lower insulating layer 11 so that the alignment mark 15 is formed. The mark 15 can be recognized from outside. Also, by having a fixed positional relationship with the first opening 12 a, the lid 7 can be placed in the first insulating substrate 12 in the first insulating substrate 12.
When the lid 7 is joined to the upper surface around the opening 12a of the
Functions as a reference when aligning with 12a. The first opening formed in the upper insulating layer 12
The second opening 12b and the second opening 12b are simultaneously formed by subjecting a ceramic green sheet serving as the upper insulating layer 12 to a conventionally known punching process. Since the first opening 12a and the second opening 12b formed in the upper insulating layer 12 are formed at the same time by punching in the same layer, the variation in the positional relationship between them is about 50 μm. The following is extremely small. Therefore, the second
By using the opening 12b as a reference, the lid 7 can be accurately positioned with respect to the first opening 12a. Next, a method of manufacturing an electronic device using the multi-piece substrate for a wiring board of the present invention will be described. First, the alignment mark 15 exposed in the second opening 12b of the upper insulating layer 12 is recognized by the image recognition device, and the position of the alignment mark 15 is detected. Then, the position of the wiring conductor 5 attached to the upper surface of the lower insulating layer 11 of each wiring board region 13 is calculated based on the detected position of the alignment mark 15. Then, based on the calculated position data of the wiring conductor 5, the electronic component 4 is moved by the automatic machine to a predetermined positional relationship with the wiring conductor 5 attached to the upper surface of the lower insulating layer 11 of each wiring board region 13. The electrodes of these electronic components 4 and the wiring conductors 5 attached to the upper surface of the lower insulating layer 11 of each of the wiring board regions 13 are accommodated in the concave portions 3a of each of the wiring board regions 13 so that Are electrically connected via bonding wires 6. In this case, since the positioning mark 15 is formed on the upper surface of the lower insulating layer 11 at the same time as the wiring conductor 5, the position between the positioning mark 15 and the wiring conductor 5 on the upper surface of the lower insulating layer 11 is reduced. Variations in the positional relationship are extremely small. Therefore, the electronic component 4 is mounted on the wiring conductor 5 attached on the lower insulating layer 11 of each wiring board region 13 with reference to the alignment mark 15.
Can be accurately aligned, and as a result, the electrodes of the electronic component 4 and the wiring conductors 5 can be electrically and accurately connected. Next, the image recognition device recognizes the second opening 12b formed in the upper insulating layer 12 and detects the position of the second opening 12b. Then, based on the detected position of the second opening 12b, the position of the first opening 12a formed in the upper insulating layer 12 of each wiring board region 13 is calculated.
Then, based on the calculated position data of the first opening 12a, the first opening 12a is formed on the upper surface of the upper insulating layer 12 of each wiring board region 13.
The lid 7 is positioned and joined by an automatic machine so as to have a predetermined sealing width around a. In this case, the second opening 12b is
Since the upper insulating layer 12 is stamped and formed at the same time as the first opening 12a, the variation in the positional relationship with the first opening 12a is extremely small. First opening formed in upper insulating layer 12
The lid 7 can be accurately positioned with respect to 12a, and as a result, the electronic component 4 can be hermetically sealed inside the recess 3a of each wiring board region 13. Finally, the mother board 10 is connected to each wiring board area.
If divided into 13 units, a large number of electronic devices can be manufactured simultaneously and intensively. In order to divide the mother board 10 into the respective wiring board areas 13, division grooves having a predetermined depth are formed in advance on the upper and lower surfaces of the mother board 10 along the boundaries of the respective wiring board areas 13. A method of so-called chocolate break of the mother substrate 10 along the dividing groove, or a method of cutting and dividing the mother substrate 10 along a boundary of each wiring substrate region 13 with a laser or a diamond cutter is adopted. Thus, according to the multi-piece substrate for wiring board of the present invention, the electronic component 4 is accurately positioned with respect to the wiring conductor 5 attached to the upper surface of the lower insulating layer 11 of each wiring board region 13. The electrode of the electronic component 4 and the wiring conductor 5 of each wiring board region 13 can be electrically and accurately connected to each other, and the first opening 12a formed in the upper insulating layer 12 of each wiring board region 13 On the other hand, the electronic component 4 can be housed with high airtightness in the concave portion 3a of each wiring board region 13 by accurately aligning the lid 7, and the wiring conductor 5 and the electrode of the electronic component 4 can be electrically accurately detected. A large number of electronic devices that are connected and in which the electronic components 4 are sealed with high hermetic reliability can be manufactured simultaneously and collectively. The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. For example, in the example of the above-described embodiment, the alignment mark 15 is
13 are arranged corresponding to the outermost row, but as shown in the top view similar to FIG. 2 in FIG. 3, even if all the rows of the wiring board area 13 are arranged corresponding to each other. Good. Further, the shape of the alignment mark 15 is not limited to the cross shape, but may be another shape such as a circle, a square, or a triangle. As described above, according to the multi-piece substrate for wiring board of the present invention, the outer peripheral portion of the upper surface of the lower insulating layer on which the wiring conductor to which the electrode of the electronic component is connected is attached. Since the alignment mark having a fixed positional relationship with the wiring conductor is arranged on an extension of the center line of the arrangement of the wiring board region, the wiring conductor attached to each wiring board region of the lower insulating layer and Variations in the mutual positional relationship between the lower insulating layer and the positioning mark attached to the outer peripheral portion of the upper surface are extremely small. Therefore, the electronic component and the wiring conductor can be aligned with extremely high accuracy based on the alignment mark.
As a result, it is possible to electrically accurately connect the electrode of the electronic component and the wiring conductor. According to the multi-cavity substrate for a wiring board of the present invention, since the first opening and the second opening are both formed in the upper insulating layer, the positional relationship between the first and second openings is extremely small. small. Therefore, the lid and the first opening can be positioned with high accuracy based on the second opening, and
As a result, the lid can be provided with a predetermined sealing width around each of the first openings on the upper insulating layer on the upper surface of each wiring board region and joined with high airtightness, thereby providing an electronic device with high airtight reliability. be able to. As described above, according to the present invention, the electronic component can be accurately positioned with respect to the wiring conductor adhered to the lower insulating layer, and the electrode of the electronic component and the wiring board can be electrically accurately positioned. And the lid can be accurately positioned with respect to the opening in the upper insulating layer,
A multi-cavity substrate for a wiring board capable of manufacturing an electronic device with high airtight reliability was provided.

【図面の簡単な説明】 【図1】本発明の配線基板用多数個取り基板の実施の形
態の一例を示す断面図である。 【図2】図1に示す配線基板用多数個取り基板の上面図
である。 【図3】本発明の配線基板用多数個取り基板の実施の形
態の他の例を示す上面図である。 【図4】本発明の配線基板用多数個取り基板により製作
される電子装置の断面図である。 【符号の説明】 3a・・凹部 4・・・電子部品 5・・・配線導体 11・・・下絶縁層 12・・・上絶縁層 12a・・第1の開口 12b・・第2の開口 13・・・配線基板領域 15・・・位置合わせ用マーク
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view showing an example of an embodiment of a multi-piece substrate for a wiring board according to the present invention. FIG. 2 is a top view of the multi-piece circuit board for a wiring board shown in FIG. 1; FIG. 3 is a top view showing another example of the embodiment of the multi-piece substrate for a wiring board of the present invention. FIG. 4 is a cross-sectional view of an electronic device manufactured using the multi-cavity substrate for a wiring board of the present invention. [Description of Symbols] 3a... Recesses 4... Electronic components 5... Wiring conductors 11... Lower insulating layer 12... Upper insulating layer 12a. ... Wiring board area 15 ... Positioning mark

───────────────────────────────────────────────────── フロントページの続き (58)調査した分野(Int.Cl.7,DB名) H05K 1/02 H05K 3/00 H05K 3/46 H01L 21/60 H01L 23/12 H01C 17/06 ──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. 7 , DB name) H05K 1/02 H05K 3/00 H05K 3/46 H01L 21/60 H01L 23/12 H01C 17/06

Claims (1)

(57)【特許請求の範囲】 【請求項1】 電子部品の電極が接続される配線導体が
被着された多数個の配線基板領域が上面中央部に縦横に
配列され、前記配線導体と一定の位置関係を有する位置
合わせ用マークが上面外周部の前記配線基板領域の配列
の中心線の延長線上に配置された下絶縁層と、該下絶縁
層の上面に積層された、前記各配線基板領域に対応して
前記電子部品を収容する凹部を形成するための第1の開
口および前記位置合わせ用マークを露出させる前記第1
の開口と同形の第2の開口を有する上絶縁層とから成る
ことを特徴とする配線基板用多数個取り基板。
(1) A plurality of wiring board regions on which wiring conductors to which electrodes of an electronic component are connected are arranged vertically and horizontally at the center of the upper surface, and are fixed to the wiring conductors. A lower insulating layer in which an alignment mark having the following positional relationship is disposed on an extension of the center line of the arrangement of the wiring substrate regions on the outer peripheral portion of the upper surface, and the respective wiring boards laminated on the upper surface of the lower insulating layer wherein exposing the first opening and the mark for the alignment to form a recess for accommodating the electronic component corresponds to a region first
And an upper insulating layer having a second opening of the same shape .
JP11758198A 1998-04-27 1998-04-27 Multi-cavity board for wiring board Expired - Fee Related JP3488826B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11758198A JP3488826B2 (en) 1998-04-27 1998-04-27 Multi-cavity board for wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11758198A JP3488826B2 (en) 1998-04-27 1998-04-27 Multi-cavity board for wiring board

Publications (2)

Publication Number Publication Date
JPH11312851A JPH11312851A (en) 1999-11-09
JP3488826B2 true JP3488826B2 (en) 2004-01-19

Family

ID=14715372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11758198A Expired - Fee Related JP3488826B2 (en) 1998-04-27 1998-04-27 Multi-cavity board for wiring board

Country Status (1)

Country Link
JP (1) JP3488826B2 (en)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002353573A (en) * 2001-05-28 2002-12-06 Kyocera Corp Ceramic wiring board of multiple allocation
JP4511336B2 (en) * 2004-12-24 2010-07-28 京セラ株式会社 Multi-cavity wiring board and method for manufacturing electronic device
JP4812516B2 (en) * 2006-05-29 2011-11-09 京セラ株式会社 Multiple wiring board
JP2012151509A (en) * 2012-05-01 2012-08-09 Shinko Electric Ind Co Ltd Wiring substrate, method of manufacturing the same, and semiconductor package
JP7391494B2 (en) * 2018-01-30 2023-12-05 京セラ株式会社 Motherboards for mounting electronic devices, substrates for mounting electronic devices, and electronic devices

Also Published As

Publication number Publication date
JPH11312851A (en) 1999-11-09

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