JP2002158306A - Batch wiring board - Google Patents

Batch wiring board

Info

Publication number
JP2002158306A
JP2002158306A JP2000353784A JP2000353784A JP2002158306A JP 2002158306 A JP2002158306 A JP 2002158306A JP 2000353784 A JP2000353784 A JP 2000353784A JP 2000353784 A JP2000353784 A JP 2000353784A JP 2002158306 A JP2002158306 A JP 2002158306A
Authority
JP
Japan
Prior art keywords
wiring board
wiring
conductor
plating
conductors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000353784A
Other languages
Japanese (ja)
Other versions
JP3404375B2 (en
Inventor
Kazuhiro Kajiya
和浩 加治屋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera Corp
Original Assignee
Kyocera Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera Corp filed Critical Kyocera Corp
Priority to JP2000353784A priority Critical patent/JP3404375B2/en
Publication of JP2002158306A publication Critical patent/JP2002158306A/en
Application granted granted Critical
Publication of JP3404375B2 publication Critical patent/JP3404375B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

PROBLEM TO BE SOLVED: To plate the whole wiring conductors with a metal layer for a prescribed thickness. SOLUTION: In this multicavity wiring board, a large number of wiring board regions 2 are arranged and formed in arrays of columns and rows in a central part of a mother board 1 constituted by laminating a plurality of insulating layers 1a, 1b. Each of the wiring board regions 2 has a recessed part 2a for accommodating an electronic component 4, and a plurality of wiring conductors 5 with which electrodes of the electronic component 4 are to be electrically connected on the upper surface side. In the outer peripheral part of the mother board 1, a frame type waste region 3 is formed which has conductor 8 for plating electric continuity with which the respective wiring conductors 5 are electrically connected in common between the insulating layers 1a, 1b. A plurality of dummy recessed parts 3a for exposing the conductor 8 are arranged on the upper surface side of the waste region 3.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、広面積の母基板中
に各々が半導体素子や水晶振動子等の電子部品を搭載す
るための小型の配線基板となる多数の配線基板領域を縦
横の並びに一体的に配列形成して成る多数個取り配線基
板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large-sized mother board, which has a large number of wiring board areas, each of which becomes a small-sized wiring board for mounting electronic components such as a semiconductor element and a crystal oscillator. The present invention relates to a multi-cavity wiring board integrally formed and arranged.

【0002】[0002]

【従来の技術】従来、例えば半導体素子や水晶振動子等
の電子部品を収容するための電子部品収納用パッケージ
に用いられる小型の配線基板は、酸化アルミニウム質焼
結体等のセラミックスから成る略四角平板状の絶縁基体
の上面に電子部品を収容するための凹部が形成されてい
るとともに、この凹部の内側から絶縁基体の下面にかけ
て複数の配線導体を配設して成る。そして、絶縁基体の
凹部の底面に電子部品を搭載固定するとともに電子部品
の電極をボンディングワイヤや半田等の電気的接続手段
を介して凹部内の配線導体に電気的に接続し、しかる
後、絶縁基体の上面に凹部を塞ぐようにして金属やガラ
ス等から成る蓋体やエポキシ樹脂等から成る樹脂製充填
材を接合させ、凹部の内部に電子部品を気密に収容する
ことによって製品としての電子装置となる。
2. Description of the Related Art Conventionally, a small-sized wiring board used for an electronic component housing package for housing electronic components such as a semiconductor element and a quartz oscillator is, for example, a substantially rectangular board made of ceramics such as an aluminum oxide sintered body. A recess for accommodating an electronic component is formed on the upper surface of a flat insulating substrate, and a plurality of wiring conductors are arranged from the inside of the recess to the lower surface of the insulating substrate. Then, the electronic component is mounted and fixed on the bottom surface of the concave portion of the insulating base, and the electrode of the electronic component is electrically connected to the wiring conductor in the concave portion via an electrical connection means such as a bonding wire or solder. An electronic device as a product by joining a lid made of metal, glass, or the like, or a resin filler made of epoxy resin, etc., so as to cover the recess on the upper surface of the base, and hermetically housing electronic components inside the recess. Becomes

【0003】ところで、このような配線基板は近時の電
子装置の小型化の要求に伴い、その大きさが数mm角程
度の極めて小さなものとなってきており、多数個の配線
基板の取り扱いを容易とするために、また配線基板およ
び電子装置の製作を効率よくするために1枚の広面積の
母基板中から多数個の配線基板を同時集約的に得るよう
になした、いわゆる多数個取り配線基板の形態で製作さ
れている。
[0003] In recent years, with the recent demand for miniaturization of electronic devices, the size of such a wiring board has become extremely small, on the order of several mm square, and a large number of wiring boards must be handled. In order to facilitate the manufacture of wiring boards and electronic devices, a so-called multi-cavity method is used in which a large number of wiring boards are simultaneously and intensively obtained from a single large-area mother board. It is manufactured in the form of a wiring board.

【0004】この多数個取り配線基板は、複数の絶縁層
を積層して成る略平板状の母基板の中央部に各々がその
上面側に電子部品を収容するための凹部およびこの凹部
内から下面にかけて複数の配線導体を有する略四角形の
多数の配線基板領域を縦横の並びに一体的に配列形成し
て成るとともに、この母基板の外周部にこれらの配線基
板領域を取り囲むようにして略四角枠状の捨て代領域を
形成して成る。そして、例えば各配線基板領域の凹部内
に電子部品を収容した後、母基板を各配線基板領域毎に
分割することによって多数個の電子装置が同時集約的に
製作される。
This multi-cavity wiring board has a concave portion for accommodating electronic components on its upper surface side and a lower surface from the inside of the concave portion in a central portion of a substantially flat mother substrate formed by laminating a plurality of insulating layers. A large number of substantially rectangular wiring board regions having a plurality of wiring conductors are formed vertically and horizontally and integrally arranged, and the outer peripheral portion of the mother board surrounds these wiring board regions so as to form a substantially rectangular frame shape. Formed by abandonment allowance area. Then, for example, after the electronic components are accommodated in the concave portions of the respective wiring board regions, a large number of electronic devices are simultaneously and intensively manufactured by dividing the mother board into the respective wiring board regions.

【0005】ところで一般的に、このような多数個取り
配線基板においては、配線導体が酸化腐食するのを防止
するとともに配線導体と電子部品の電極との電気的な接
続を良好なものとするために、各配線導体の露出表面に
は例えば厚みが1〜10μm程度のニッケルめっき層と厚
みが0.1〜3μm程度の金めっき層とが電解めっき法に
より順次被着されている。
Generally, in such a multi-cavity wiring board, in order to prevent the wiring conductor from being oxidized and corroded, and to improve the electrical connection between the wiring conductor and the electrode of the electronic component. On the exposed surface of each wiring conductor, for example, a nickel plating layer having a thickness of about 1 to 10 μm and a gold plating layer having a thickness of about 0.1 to 3 μm are sequentially applied by an electrolytic plating method.

【0006】従来、このような多数個取り配線基板にお
いて各配線導体に電解めっき法によりニッケルめっき層
や金めっき層を被着させるには、捨て代領域の内部に各
配線導体が電気的に共通に接続された枠状のめっき導通
用導体を設けておくとともに捨て代領域の外周側面にこ
のめっき導通用導体が電気的に接続された端子導体を被
着させておき、この多数個取り配線基板を電解めっき液
中に浸漬するとともに端子導体からめっき導通用導体を
介して各配線導体に電解めっきのための電荷を供給する
ことによって各配線導体の露出表面に電解めっきを行な
う方法が採用されていた。
Conventionally, in such a multi-cavity wiring board, to apply a nickel plating layer or a gold plating layer to each wiring conductor by an electrolytic plating method, the wiring conductors are electrically common inside the throwaway area. And a terminal conductor to which the plating conductor is electrically connected is provided on the outer peripheral side surface of the throw-away area, and the multi-cavity wiring board is provided. Is applied to the exposed surface of each wiring conductor by immersing the wiring conductor in an electrolytic plating solution and supplying a charge for electrolytic plating to each wiring conductor from a terminal conductor via a plating conduction conductor. Was.

【0007】[0007]

【発明が解決しようとする課題】しかしながら、この多
数個取り配線基板によると、これを電解めっき液中に浸
漬して各配線基板領域の配線導体に電解めっきのための
電荷を供給すると、電界中の電気力線は最外周に配列さ
れた配線基板領域の配線導体に大きく集中しやすいこ
と、およびこの最外周に配列された配線基板領域ではこ
れに隣接する捨て代領域の上面が平坦なために他の配線
基板領域と比較してめっき液が流動しやすく、そのため
新たなめっき金属源が供給されやすいこと等から最外周
に配列された配線基板領域の配線導体には他の配線基板
領域の配線導体に比べて極端に厚いめっき金属層が被着
されてしまい、その結果、各配線基板領域の配線導体に
被着されるめっき金属層の厚みのばらつきが大きなもの
となってしまい、全ての配線導体に所定の厚みのめっき
金属層を被着させることが困難であるという問題点を有
していた。
However, according to this multi-cavity wiring board, when it is immersed in an electrolytic plating solution to supply electric charges for electrolytic plating to the wiring conductors in each wiring board area, the electric field in the electric field is reduced. Lines of electric force are likely to be largely concentrated on the wiring conductors in the wiring board region arranged on the outermost periphery, and in the wiring board region arranged on the outermost periphery, the upper surface of the abandonment allowance region adjacent thereto is flat because The plating solution flows more easily than the other wiring board areas, so that a new plating metal source is easily supplied. An extremely thick plating metal layer is deposited as compared with the conductor, and as a result, the thickness variation of the plating metal layer deposited on the wiring conductor in each wiring board area becomes large, and The plated metal layer of a certain thickness on the wire conductor of had the problem that it is difficult to deposit.

【0008】本発明は、かかる従来の問題点に鑑み案出
されたものであり、その目的は、各配線基板領域の配線
導体に被着されるめっき金属層の厚みのばらつきを小さ
いものとして、全ての配線基板領域の配線導体に所定の
厚みのめっき金属層を電解めっき法により被着させるこ
とが可能な多数個取り配線基板を提供することにある。
The present invention has been devised in view of such a conventional problem, and an object of the present invention is to reduce variations in the thickness of a plating metal layer applied to a wiring conductor in each wiring board region. It is an object of the present invention to provide a multi-cavity wiring board in which a plating metal layer having a predetermined thickness can be applied to wiring conductors in all wiring board regions by electrolytic plating.

【0009】[0009]

【課題を解決するための手段】本発明の多数個取り配線
基板は、複数の絶縁層を積層して成る母基板の中央部
に、各々が上面側に電子部品を収容するための凹部およ
び電子部品の電極が電気的に接続される複数の配線導体
を有する多数の配線基板領域を縦横の並びに配列形成し
て成るとともに、この母基板の外周部に、各配線導体が
電気的に共通に接続されためっき導通用導体を絶縁層間
に有する枠状の捨て代領域を形成して成る多数個取り配
線基板であって、捨て代領域の上面側にめっき導通用導
体を露出させる複数のダミー凹部を設けたことを特徴と
するものである。
A multi-cavity wiring board according to the present invention has a concave portion for accommodating an electronic component on an upper surface side of a mother substrate formed by laminating a plurality of insulating layers. A large number of wiring board regions having a plurality of wiring conductors to which the electrodes of the component are electrically connected are formed in rows and columns, and the wiring conductors are electrically connected in common to the outer periphery of the mother board. A multi-cavity wiring board formed by forming a frame-shaped discard margin area having a plated conductor for conduction between insulating layers, and a plurality of dummy recesses that expose the plating conductor on the upper surface side of the discard margin area. It is characterized by having been provided.

【0010】本発明の多数個取り配線基板によれば、母
基板の外周部に形成された捨て代領域の上面側にめっき
導通用導体を露出させる複数のダミー凹部を設けたこと
から、この多数個取り配線基板を電解めっき液中に浸漬
するとともに各配線基板領域の配線導体にめっき導通用
導体を介して電荷を供給すると、電界中の電気力線は、
各配線基板領域よりも外周側に位置するダミー凹部内に
露出しためっき導通用導体に大きく集中し、母基板の中
央部に形成された各配線基板領域の配線導体には略均等
に分散される。また、ダミー凹部によって捨て代領域に
おけるめっき液の流動に対する抵抗が大きくなることか
ら、最外周に配列された配線基板領域と他の配線基板領
域とにおけるめっき液の流動が略均一となる。
According to the multi-cavity wiring board of the present invention, since a plurality of dummy recesses for exposing the conductor for plating conduction are provided on the upper surface side of the disposal margin area formed on the outer peripheral portion of the mother board, When the individual wiring board is immersed in the electrolytic plating solution and a charge is supplied to the wiring conductor in each wiring board area through the conductor for plating conduction, the lines of electric force in the electric field are:
It is largely concentrated on the plating conduction conductor exposed in the dummy recess located on the outer peripheral side of each wiring board area, and is substantially evenly distributed to the wiring conductors of each wiring board area formed in the center portion of the mother board. . In addition, since the resistance to the flow of the plating solution in the discarding allowance region is increased by the dummy concave portions, the flow of the plating solution in the wiring substrate region arranged on the outermost periphery and the other wiring substrate regions becomes substantially uniform.

【0011】[0011]

【発明の実施の形態】次に、本発明の多数個取り配線基
板について添付の図面を基に説明する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a multi-cavity wiring board according to the present invention will be described with reference to the accompanying drawings.

【0012】図1は本発明の多数個取り配線基板の実施
の形態の一例を示す上面図であり、図2は図1に示す多
数個取り配線基板のA−A線における断面図である。図
中、1は母基板、2は配線基板領域、3は捨て代領域で
ある。
FIG. 1 is a top view showing an example of an embodiment of a multi-piece wiring board of the present invention, and FIG. 2 is a sectional view of the multi-piece wiring board shown in FIG. In the figure, 1 is a mother board, 2 is a wiring board area, and 3 is a throwaway area.

【0013】母基板1は、例えば酸化アルミニウム質焼
結体や窒化アルミニウム質焼結体・ムライト質焼結体・
ガラス−セラミックス等のセラミックス材料から成る2
層の絶縁層1a・1bが積層されて成る略四角形の平板
であり、その中央部に縦横の並びに配列形成された多数
の配線基板領域2と、その外周部にこれらの配線基板領
域2を取り囲むようにして形成された略四角枠状の捨て
代領域3とで構成されている。そして、各配線基板領域
2の角部に対応して複数の貫通孔1cが形成されてお
り、また相対向する外周側面には2対の切り欠き1dが
形成されている。
The mother substrate 1 is made of, for example, an aluminum oxide sintered body, an aluminum nitride sintered body, a mullite sintered body,
2 consisting of ceramic materials such as glass-ceramics
A substantially rectangular flat plate formed by laminating a plurality of insulating layers 1a and 1b, a large number of wiring board regions 2 arranged vertically and horizontally in the center, and these wiring board regions 2 are surrounded on the outer periphery. It is composed of the substantially rectangular frame-shaped discard margin area 3 formed as described above. A plurality of through holes 1c are formed corresponding to the corners of each wiring board region 2, and two pairs of cutouts 1d are formed on opposing outer peripheral side surfaces.

【0014】このような母基板1は、セラミックグリー
ンシート積層法によって製作され、具体的には、絶縁層
1a・1b用のセラミックグリーンシートをそれぞれ準
備するとともに、これらのセラミックグリーンシートに
適当な打ち抜き加工を施した後に積層し、それを高温で
焼成することによって製作される。
Such a mother substrate 1 is manufactured by a ceramic green sheet laminating method. More specifically, ceramic green sheets for the insulating layers 1a and 1b are prepared, and the ceramic green sheets are appropriately punched. It is manufactured by laminating after processing and firing it at high temperature.

【0015】母基板1の中央部に配列形成された各配線
基板領域2は、それぞれが小型の配線基板となる領域で
あり、それぞれの上面中央部に電子部品4を収容するた
めの略四角形の凹部2aを有しており、凹部2aの底面
から貫通孔1cを介して下面にかけてはタングステンや
モリブデン・銅・銀等の金属粉末メタライズから成る配
線導体5を有している。そして、凹部2a内には半導体
素子や水晶振動子等の電子部品4が収容されるととも
に、配線導体5にはこの電子部品4の各電極が例えばボ
ンディングワイヤ6や半田バンプ等の電気的接続手段を
介して電気的に接続され、しかる後、各配線基板領域2
の上面に図示しない蓋体や樹脂充填材を電子部品4を覆
うようにして接合することによって電子部品4が封止さ
れる。なお、このような凹部2aは、絶縁層1b用のセ
ラミックグリーンシートに凹部2a用の略四角形の貫通
孔を打ち抜いておくことによって形成され、配線導体5
は、絶縁層1a用のセラミックグリーンシートに配線導
体5用のメタライズペーストを所定のパターンに印刷塗
布しておくことによって形成される。
Each of the wiring board regions 2 arranged in the center of the mother board 1 is a region to be a small wiring board, and has a substantially square shape for accommodating the electronic component 4 in the center of each upper surface. It has a concave portion 2a, and has a wiring conductor 5 made of metal powder of metal such as tungsten, molybdenum, copper, silver, etc. from the bottom surface of the concave portion 2a to the lower surface via the through hole 1c. An electronic component 4 such as a semiconductor element or a quartz oscillator is accommodated in the recess 2a, and each electrode of the electronic component 4 is connected to the wiring conductor 5 by an electrical connection means such as a bonding wire 6 or a solder bump. Are electrically connected to each other, and thereafter, each wiring board region 2
The electronic component 4 is sealed by joining a lid or a resin filler (not shown) so as to cover the electronic component 4. The recess 2a is formed by punching a substantially rectangular through hole for the recess 2a in the ceramic green sheet for the insulating layer 1b.
Is formed by printing and applying a metallized paste for the wiring conductor 5 in a predetermined pattern on a ceramic green sheet for the insulating layer 1a.

【0016】さらに、母基板1の上下面には、各配線基
板領域2を区切る分割溝7が縦横に形成されており、各
配線基板領域2の凹部2a内に電子部品4を収容した
後、母基板1を分割溝7に沿って分割することにより、
多数の電子装置が同時集約的に製造される。分割溝7
は、その断面形状が略V字状であり、母基板1の厚さや
材質などにより異なるが、その深さが0.05〜1.5mm程
度、その開口幅が0.01〜0.3mm程度である。このよう
な分割溝7は、絶縁層1a・1b用のセラミックグリー
ンシートを積層した後、この積層体の上下面にカッター
刃や金型により切り込みを入れておくことによって形成
される。
Further, on the upper and lower surfaces of the mother substrate 1, there are formed vertical and horizontal dividing grooves 7 for dividing the respective wiring board regions 2. After the electronic components 4 are accommodated in the recesses 2a of the respective wiring board regions 2, By dividing the mother board 1 along the dividing grooves 7,
Many electronic devices are manufactured simultaneously and intensively. Division groove 7
Has a substantially V-shaped cross-section and varies depending on the thickness and material of the mother substrate 1, but has a depth of about 0.05 to 1.5 mm and an opening width of about 0.01 to 0.3 mm. Such a dividing groove 7 is formed by laminating ceramic green sheets for the insulating layers 1a and 1b, and then cutting the upper and lower surfaces of the laminated body with a cutter blade or a mold.

【0017】また、母基板1の外周部に形成された捨て
代領域3は、母基板1の加工や取り扱いを容易とするた
めの領域である。そして、その絶縁層1a・1b間には
各配線基板領域2の配線導体5が電気的に共通に接続さ
れた略四角枠状のめっき導通用導体8が形成されてお
り、さらにその側面の各切り欠き1d内にはめっき導通
用導体8が電気的に接続された端子導体9が被着されて
いる。
The discard margin area 3 formed on the outer peripheral portion of the motherboard 1 is an area for facilitating processing and handling of the motherboard 1. Further, between the insulating layers 1a and 1b, there is formed a substantially square frame-shaped plating conducting conductor 8 to which the wiring conductors 5 of the respective wiring board regions 2 are electrically connected in common. In the notch 1d, a terminal conductor 9 to which the plating conducting conductor 8 is electrically connected is attached.

【0018】これらのめっき導通用導体8および端子導
体9は、タングステンやモリブデン・銀・銅等の金属粉
末メタライズから成り、各配線基板領域2の配線導体5
に電解めっきのための電荷を供給するための供給路とし
て機能する。そして、母基板1を電解めっき液中に浸漬
するとともに端子導体9からめっき導通用導体8を介し
て各配線基板領域2の配線導体5に電解めっきのための
電荷を供給することにより、各配線基板領域2の配線導
体5の露出表面にニッケルめっき層や金めっき層等のめ
っき金属層が被着される。このようなめっき導通用導体
8および端子導体9は絶縁層1a・1b用のセラミック
グリーンシートにめっき導通用導体8用および端子電極
9用のメタライズペーストを所定のパターンに印刷塗布
しておくことによって形成される。
The plating conductor 8 and the terminal conductor 9 are made of metal powder of metal such as tungsten, molybdenum, silver, or copper.
Functions as a supply path for supplying electric charges for electrolytic plating to the substrate. Then, by immersing the mother board 1 in the electrolytic plating solution and supplying electric charges for electrolytic plating from the terminal conductors 9 to the wiring conductors 5 of the respective wiring board areas 2 via the plating conducting conductors 8, each wiring A plating metal layer such as a nickel plating layer or a gold plating layer is applied to the exposed surface of the wiring conductor 5 in the substrate region 2. Such a conductor 8 for plating conduction and a terminal conductor 9 are obtained by printing and applying a metallized paste for the conductor 8 for plating conduction and the terminal electrode 9 in a predetermined pattern on ceramic green sheets for the insulating layers 1a and 1b. It is formed.

【0019】さらに、捨て代領域3の上面には、めっき
導通用導体8を露出させる略四角形の複数のダミー凹部
3aが配線基板領域2の並びの両端にそれぞれ一つずつ
対応するように設けられている。これらのダミー凹部3
aは、各配線基板領域2の配線導体5に略均一な厚みの
めっき金属層を被着させるためのものであり、母基板1
を電解めっき液中に浸漬するとともに端子導体9からめ
っき導通用導体8を介して各配線基板領域2の配線導体
5に電解めっきのための電荷を供給して各配線基板領域
2の配線導体5にめっき金属層を被着させる際、各配線
基板領域2の配線導体5よりも外周側に位置するめっき
導通用導体8を露出させることにより電界中の電気力線
をダミー凹部3a内に露出しためっき導通用導体8に大
きく集中させ、それにより各配線基板領域2の配線導体
5には電気力線を略均一に分散させるとともに、ダミー
凹部3aによる凹凸により捨て代領域3の上面側におけ
るめっき液の流れに対する抵抗を大きなものとすること
により、最外周に配列された配線基板領域2と他の配線
基板領域2とにおけるめっき液の流動を略均一なものと
し、それらにより各配線基板領域2の配線導体5に略均
一な厚みのめっき金属層を被着させることを可能とす
る。
Further, on the upper surface of the throw-away area 3, a plurality of substantially rectangular dummy recesses 3a for exposing the plating conducting conductors 8 are provided so as to correspond to both ends of the arrangement of the wiring board area 2, respectively. ing. These dummy recesses 3
a is for depositing a plating metal layer having a substantially uniform thickness on the wiring conductor 5 in each wiring board region 2;
Is immersed in the electrolytic plating solution, and a charge for electrolytic plating is supplied from the terminal conductor 9 to the wiring conductor 5 of each wiring board region 2 via the plating conducting conductor 8 so that the wiring conductor 5 of each wiring board region 2 is provided. When the plating metal layer is applied to the substrate, the lines of electric force in the electric field were exposed in the dummy recesses 3a by exposing the plating conducting conductors 8 located on the outer peripheral side of the wiring conductors 5 in the respective wiring board regions 2. The lines of electric force are substantially uniformly dispersed in the wiring conductors 5 of the respective wiring board regions 2 by substantially concentrating on the plating conducting conductors 8, and the plating solution on the upper surface side of the throw-away area 3 is formed by the unevenness due to the dummy recesses 3 a. The flow resistance of the plating solution in the wiring board area 2 arranged on the outermost periphery and the other wiring board areas 2 is made substantially uniform by increasing the resistance to the flow of the plating solution. It is possible to apply a plating metal layer having a substantially uniform thickness to the wiring conductor 5 in the wiring board region 2.

【0020】なお、各ダミー凹部3a内に露出するめっ
き導通用導体8の面積は、各配線基板領域2の上面側に
おける被めっき面積に対して20〜200%の範囲が好まし
い。各ダミー凹部3a内に露出するめっき導通用導体8
の面積が各配線基板領域2の上面側における被めっき面
積に対して20%未満であると、配線導体5に電解めっき
法によりめっき金属層を被着させる際に電界中の電気力
線をダミー凹部3a内に露出するめっき導通用導体8に
良好に集中させることができず、そのため各配線基板領
域2の配線導体5に略均一な厚みのめっき金属層を被着
させることが困難となる傾向にあり、他方、200%を超
えると、ダミー凹部3a内に露出しためっき導通用導体
8に不要なめっき金属層が多量に被着されてめっきの効
率が低下してしまう。
The area of the conductive conductor 8 exposed in each of the dummy recesses 3a is preferably in the range of 20 to 200% of the area to be plated on the upper surface side of each wiring board region 2. Plating conduction conductor 8 exposed in each dummy recess 3a
Is less than 20% of the area to be plated on the upper surface side of each wiring board region 2, the lines of electric force in the electric field are dummy when the plating metal layer is applied to the wiring conductor 5 by the electrolytic plating method. It is not possible to satisfactorily concentrate on the plating conduction conductors 8 exposed in the recesses 3a, so that it becomes difficult to apply a plating metal layer having a substantially uniform thickness to the wiring conductors 5 in each wiring board region 2. On the other hand, if it exceeds 200%, a large amount of an unnecessary plating metal layer is deposited on the plating conducting conductor 8 exposed in the dummy recess 3a, and the plating efficiency is reduced.

【0021】このようなダミー凹部3aは、絶縁層1b
用のセラミックグリーンシートにダミー凹部3a用の貫
通孔を打ち抜いておくことによって形成される。なお、
このように配線基板領域2の各並びの両端にそれぞれ対
応してダミー凹部3aが形成されていることによって、
絶縁層1a・1b用のセラミックグリーンシートの積層
体にカッター刃やプレス金型等により各配線基板領域2
を区切る分割溝7用の切り込みを形成する際に、最外周
の配線基板領域2と捨て代領域3との間に形成された分
割溝7が両側に略均等に開き、その結果、最外周の配線
基板領域2と捨て代領域3との間に形成された分割溝7
が癒着してしまうことを有効に防止することができる。
Such a dummy recess 3a is formed in the insulating layer 1b.
It is formed by punching a through hole for the dummy concave portion 3a in a ceramic green sheet. In addition,
Since the dummy recesses 3a are formed at both ends of each row of the wiring board region 2 in this manner,
Each of the wiring board regions 2 is formed on the laminate of the ceramic green sheets for the insulating layers 1a and 1b by using a cutter blade, a press die, or the like.
When forming the cuts for the dividing grooves 7 for separating the grooves, the dividing grooves 7 formed between the outermost wiring board region 2 and the disposal margin region 3 are almost equally opened on both sides, and as a result, Division groove 7 formed between wiring substrate area 2 and waste allowance area 3
Can effectively be prevented from adhering.

【0022】かくして、本発明の多数個取り配線基板に
よれば、母基板1をニッケルめっきや金めっきのための
電解めっき液中に浸漬するとともに、端子導体9からめ
っき導通用導体8を介して各配線基板領域2の配線導体
5に電解めっきのための電荷を供給することによって各
配線基板領域2の配線導体5に電解めっきによるめっき
金属層を略均一な厚みに被着させ、しかる後、各配線基
板領域2の凹部2a内に電子部品4を搭載固定するとと
もに、この電子部品4の電極と配線導体5とをボンディ
ングワイヤ6や半田等の電気的接続手段を介して接続
し、最後に、各配線基板領域2の上に金属やセラミック
スから成る蓋体やエポキシ樹脂等から成る樹脂製充填材
を接合するとともに、母基板1を分割溝7に沿って分割
することにより、多数個の電子装置が同時集約的に製作
される。
Thus, according to the multi-cavity wiring board of the present invention, the mother board 1 is immersed in the electrolytic plating solution for nickel plating or gold plating, and the mother board 1 is immersed in the plating conductor 8 from the terminal conductor 9. By supplying charges for electrolytic plating to the wiring conductors 5 in each wiring board region 2, a plating metal layer by electrolytic plating is applied to the wiring conductors 5 in each wiring board region 2 to a substantially uniform thickness. The electronic component 4 is mounted and fixed in the concave portion 2a of each wiring board region 2, and the electrodes of the electronic component 4 and the wiring conductors 5 are connected via electrical connection means such as bonding wires 6 and solder. By joining a lid made of metal or ceramics or a resin filler made of epoxy resin or the like onto each wiring board area 2 and dividing the mother board 1 along the dividing grooves 7, a large number of Electronic devices are manufactured simultaneously and intensively.

【0023】なお、本発明は上述の実施の形態の一例に
限定されるものではなく、本発明の要旨を逸脱しない範
囲であれば、種々の変更は可能であり、例えば上述の実
施の形態の一例では、母基板1は2層の絶縁層1a・1
bを積層して形成されていたが、母基板1は3層以上の
絶縁層を積層することにより形成されていてもよい。
It should be noted that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the present invention. In one example, the mother substrate 1 has two insulating layers 1a and 1a.
Although the base substrate 1 is formed by stacking the layers b, the mother substrate 1 may be formed by stacking three or more insulating layers.

【0024】また、上述の実施の形態の一例では、ダミ
ー凹部3aは凹部2aと実質的に同じ大きさに形成され
ていたが、ダミー凹部3aは凹部2aと異なる大きさで
あってもよい。この場合、ダミー凹部3aの幅および長
さおよび深さはそれぞれ凹部2aの幅および長さおよび
深さの20%以上であることが好ましい。ダミー凹部3a
の幅および長さおよび深さがそれぞれ凹部2aの幅およ
び長さおよび深さの20%未満であると、捨て代領域3に
おけるめっき液の流れに対する抵抗を適度に大きくする
ことが困難となる。
In the above embodiment, the dummy recess 3a is formed to have substantially the same size as the recess 2a. However, the dummy recess 3a may have a different size from the recess 2a. In this case, it is preferable that the width, length, and depth of the dummy recess 3a be 20% or more of the width, length, and depth of the recess 2a, respectively. Dummy recess 3a
Is less than 20% of the width, length, and depth of the concave portion 2a, respectively, it is difficult to appropriately increase the resistance to the flow of the plating solution in the waste allowance region 3.

【0025】なお、上述の実施の形態の一例では、ダミ
ー凹部3aは配線基板領域2の各並びの両端にそれぞれ
一つずつ対応して設けられていたが、ダミー凹部3aは
必ずしも配線基板領域2の各並びの両端にそれぞれ一つ
ずつ対応して設ける必要はない。
In the above-described embodiment, the dummy recesses 3a are provided one by one at both ends of each row of the wiring board region 2. However, the dummy recesses 3a are not necessarily provided in the wiring board region 2. It is not necessary to provide one at each end of each row.

【0026】[0026]

【発明の効果】本発明の多数個取り配線基板によれば、
母基板の外周部に形成された捨て代領域の上面側にめっ
き導通用導体を露出させる複数のダミー凹部を設けたこ
とから、この多数個取り配線基板を電解めっき液中に浸
漬するとともに各配線基板領域の配線導体にめっき導通
用導体を介して電荷を供給すると、電界中の電気力線は
各配線基板領域よりも外周側に位置するダミー凹部内に
露出しためっき導通用導体に大きく集中して母基板中央
部に形成された各配線基板領域の配線導体には略均等に
分散される。また、ダミー凹部によって捨て代領域にお
けるめっき液の流動に対する抵抗が大きくなることか
ら、最外周に配列された配線基板領域と他の配線基板領
域とにおけるめっき液の流動が略均一となる。そのた
め、各配線基板領域の配線導体に厚みばらつきの小さな
所定の厚みのめっき金属層を被着させることができる。
According to the multi-cavity wiring board of the present invention,
Since a plurality of dummy recesses for exposing the conductor for plating conduction are provided on the upper surface side of the disposal allowance area formed on the outer peripheral portion of the mother board, the multi-piece wiring board is immersed in the electrolytic plating solution and each wiring is formed. When electric charges are supplied to the wiring conductor in the substrate area via the conductor for plating conduction, the lines of electric force in the electric field are largely concentrated on the conductor for plating conduction exposed in the dummy recess located on the outer peripheral side of each wiring board area. Thus, the wiring conductors in the respective wiring board regions formed in the center portion of the mother board are substantially uniformly distributed. In addition, since the resistance to the flow of the plating solution in the discarding allowance region is increased by the dummy concave portions, the flow of the plating solution in the wiring substrate region arranged on the outermost periphery and the other wiring substrate regions becomes substantially uniform. Therefore, a plating metal layer having a predetermined thickness with a small thickness variation can be applied to the wiring conductor in each wiring board region.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の多数個取り配線基板の実施の形態の一
例を示す上面図である。
FIG. 1 is a top view showing an example of an embodiment of a multi-cavity wiring board according to the present invention.

【図2】図1に示した多数個取り配線基板のA−A線に
おける断面図である。
FIG. 2 is a sectional view of the multi-piece wiring board shown in FIG. 1 taken along line AA.

【符号の説明】[Explanation of symbols]

1・・・・・・・母基板 2・・・・・・・配線基板領域 2a・・・・・・電子部品を収容するための凹部 3・・・・・・・捨て代領域 3a・・・・・・ダミー凹部 4・・・・・・・電子部品 5・・・・・・・配線導体 8・・・・・・・めっき導通用導体 1... Mother board 2... Wiring board area 2a... Recesses for accommodating electronic components 3. ···································································· Conductor for plating conduction

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 複数の絶縁層を積層して成る母基板の中
央部に、各々が上面側に電子部品を収容するための凹部
および前記電子部品の電極が電気的に接続される複数の
配線導体を有する多数の配線基板領域を縦横の並びに配
列形成するとともに、前記母基板の外周部に、前記各配
線導体が電気的に共通に接続されためっき導通用導体を
前記絶縁層間に有する枠状の捨て代領域を形成して成る
多数個取り配線基板であって、前記捨て代領域の上面側
に前記めっき導通用導体を露出させる複数のダミー凹部
を設けたことを特徴とする多数個取り配線基板。
1. A central portion of a mother substrate formed by laminating a plurality of insulating layers, a concave portion for accommodating an electronic component on an upper surface side, and a plurality of wirings to which electrodes of the electronic component are electrically connected. A large number of wiring board regions having conductors are formed vertically and horizontally in an array, and a frame-like conductor having a plating conduction conductor to which each of the wiring conductors is electrically connected in common is provided on the outer peripheral portion of the mother board. A multi-cavity wiring board formed by forming a discarding allowance area, wherein a plurality of dummy recesses are provided on an upper surface side of the discarding allowance area to expose the plating conducting conductor. substrate.
JP2000353784A 2000-11-21 2000-11-21 Multi-cavity wiring board Expired - Fee Related JP3404375B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000353784A JP3404375B2 (en) 2000-11-21 2000-11-21 Multi-cavity wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000353784A JP3404375B2 (en) 2000-11-21 2000-11-21 Multi-cavity wiring board

Publications (2)

Publication Number Publication Date
JP2002158306A true JP2002158306A (en) 2002-05-31
JP3404375B2 JP3404375B2 (en) 2003-05-06

Family

ID=18826487

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000353784A Expired - Fee Related JP3404375B2 (en) 2000-11-21 2000-11-21 Multi-cavity wiring board

Country Status (1)

Country Link
JP (1) JP3404375B2 (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310432A (en) * 2005-04-27 2006-11-09 Kyocera Corp Individually dividable multi-wiring board
JP2007207934A (en) * 2006-01-31 2007-08-16 Kyocera Kinseki Corp Sheet-like aggregate substrate
JP2007234657A (en) * 2006-02-27 2007-09-13 Kyocera Corp Multiple patterning wiring board
JP2007318034A (en) * 2006-05-29 2007-12-06 Kyocera Corp Multiple-formed wiring substrate, package for holding electronic component, and electronic device
JP2008187198A (en) * 2008-04-14 2008-08-14 Kyocera Corp Multi-piece wiring substrate and wiring substrate, and manufacturing method therefor
KR101007327B1 (en) 2009-05-08 2011-01-13 삼성전기주식회사 Printed circuit board panel
KR20130071878A (en) * 2011-12-21 2013-07-01 삼성전기주식회사 Printed circuit board
JP2020088348A (en) * 2018-11-30 2020-06-04 日本特殊陶業株式会社 Wiring board, and manufacturing method of wiring board

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006310432A (en) * 2005-04-27 2006-11-09 Kyocera Corp Individually dividable multi-wiring board
JP4557786B2 (en) * 2005-04-27 2010-10-06 京セラ株式会社 Multiple wiring board
JP2007207934A (en) * 2006-01-31 2007-08-16 Kyocera Kinseki Corp Sheet-like aggregate substrate
JP2007234657A (en) * 2006-02-27 2007-09-13 Kyocera Corp Multiple patterning wiring board
JP4594253B2 (en) * 2006-02-27 2010-12-08 京セラ株式会社 Multiple wiring board
JP2007318034A (en) * 2006-05-29 2007-12-06 Kyocera Corp Multiple-formed wiring substrate, package for holding electronic component, and electronic device
JP2008187198A (en) * 2008-04-14 2008-08-14 Kyocera Corp Multi-piece wiring substrate and wiring substrate, and manufacturing method therefor
JP4712065B2 (en) * 2008-04-14 2011-06-29 京セラ株式会社 Multi-cavity wiring board, wiring board, and multi-cavity wiring board and method of manufacturing wiring board
KR101007327B1 (en) 2009-05-08 2011-01-13 삼성전기주식회사 Printed circuit board panel
KR20130071878A (en) * 2011-12-21 2013-07-01 삼성전기주식회사 Printed circuit board
KR101903554B1 (en) * 2011-12-21 2018-10-04 삼성전기주식회사 Printed circuit board
JP2020088348A (en) * 2018-11-30 2020-06-04 日本特殊陶業株式会社 Wiring board, and manufacturing method of wiring board

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