JP3473590B2 - Test program creation apparatus and method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test program creating apparatus and method for creating a test program to be used for testing a large scale integrated circuit (LSI) mounted on an LSI tester or the like.

[0002]

2. Description of the Related Art A test program used for testing a large-scale integrated circuit (LSI) is usually composed of grouping information of pins to be tested and a processing order of test items. As a method of creating the data, for example, Japanese Patent Laid-Open No.
In the "individual test program creation method" described in Japanese Patent Publication No. 48300-, by inputting individual data of an LSI,
Grouping of pins to be tested and other LSI individual information are embedded in a test program template to create an LSI individual test program.

Further, "Test group creating apparatus and its creating method" described in Japanese Patent Laid-Open No. 2000-187064.
Defines the pin grouping conditions in advance for the pin grouping method of the test target, and makes sure that the test group can correspond to more complicated conditions such as the semiconductor integrated circuit becoming complicated and the number of pins increasing.
The method of creating in a short time is disclosed.

[0004]

However, the above-mentioned prior art has the following problems. The first is L
In a situation where the failure analysis is becoming difficult due to the complexity of SI, the increase in scale, and the increase in the number of pins, there is a problem that the cooperation between the LSI test and the failure analysis generated as a result thereof is poor. The reason is that failure analysis is not taken into consideration, even though the test program has the information necessary when the test result becomes an error, when the test program is created.

The second problem is that, while the test items are becoming more complicated as in the case of the LSIs, if the test items are different for each LSI, it is necessary to create the test program for each individual LSI. At the same time, it takes time. The reason is that the conventional technique only considers embedding individual information of the LSI in the model test program.

The third problem is that if the number of pins that can be tested differs between the test on the wafer and the test mounted on the LSI case, it is necessary to create a test program for each test case. Therefore, it takes time and effort to create a program.
The reason is that, in the test phase, the case where the number of pins to be tested is different is not considered at all.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a test program creating apparatus and method in consideration of failure analysis of an LSI after a test.

Another object of the present invention is to provide a test program creating apparatus and method capable of coping with different test target pins depending on the test phase and different test items for each LSI. .

[0009]

To achieve the above object, the present invention provides a test program creating apparatus for creating a test program for a semiconductor integrated circuit, based on information about logic pins of the semiconductor integrated circuit. Means for creating pin correspondence information, means for creating grouping information for the logical pins that match the conditions for dividing a predetermined test group with reference to the pin correspondence information, and the pin correspondence information and grouping information From the semiconductor integrated circuit and the pins of the test device thereof are edited as analysis information and output ,
A program that contains common and individual information about semiconductor integrated circuits.
The means for storing the program and the above grouping information
Control to output a test program based on the above program
Means and the analysis information creating means is the correspondence information.
The specified test phase by classifying the
Group combined output format, the analysis information, the saw including correspondence information for all pins of the semiconductor integrated circuit and the test device, the control means, based on the above conditions
Depending on the number of pins that belong to the above-mentioned divided test group
Provided is a test program creating device for controlling the output of a test program.

The test program creating apparatus according to the present invention further comprises means for storing the test target flag for each test phase and means for reflecting the pin information to which the test target flag is added in the pin correspondence information. The control means determines the test target pin of the semiconductor integrated circuit based on the reflected pin correspondence information, and controls the output of the test program according to the determination result.

Another aspect of the present invention is a method of creating a test program used for testing a semiconductor integrated circuit, the step of creating pin correspondence information based on the information about the logic pin of the semiconductor integrated circuit, and the pin correspondence. Referring to the information, a step of creating grouping information about the logic pin that matches a predetermined test group division condition, and the semiconductor integrated circuit and its test based on the pin correspondence information and the grouping information. Regarding the step of editing and outputting information including correspondence information about all pins of the device as analysis information, and the above semiconductor integrated circuit.
For storing programs that include common information and individual information for
And the above grouping information and the above program
And the step of outputting a test program to
Correspondence information is categorized according to the specified items and a predetermined test is performed.
Output in the format suitable for the phase, and output step above
Then, the above test group divided into groups based on the above conditions.
Depending on the number of pins that belong to the loop,
The output is controlled.

A method according to another invention further includes a step of storing a test target flag for each test phase, and a step of reflecting the pin information with the test target flag attached to the pin correspondence information. In the output step, the pin to be tested of the semiconductor integrated circuit is judged based on the reflected pin correspondence information, and the output of the test program is controlled according to the judgment result.

[0013]

DETAILED DESCRIPTION OF THE INVENTION Referring to the accompanying drawings,
Embodiments of the present invention will be described in detail. [First Embodiment] FIG. 1 is a block diagram showing a configuration of a test program creating apparatus according to a first embodiment of the present invention. The "test program" is used when testing an LSI.
Order of test items (DC test, function test, macro test, etc.), test target (pin, test pattern, etc.), test condition (current, voltage, test rate, timing condition)
Is a program for inputting to the LSI tester (test device).

Test program creating apparatus 4 shown in FIG.
Is a pin correspondence information creating means 31 for creating the LSI pin correspondence information 5 from the LSI pin assignment information 1 and the netlist 2 which will be described later, the grouping condition 3 and the LSI pin correspondence information 5 indicating the conditions for dividing the test group. Group creating means 32 for creating grouping information 6 from L
From the SI pin correspondence information 5 and the grouping information 6, logic pins, tester pins, LSI case pins, package pins, functions, attributes, LSI coordinate positions, clock distribution source signal names, interfaces used, It is configured by an analysis information output unit 33 that outputs analysis information 7 that summarizes the buffer name, the group name grouped by the test program, and the pin correspondence information of the test target flag.

The LSI pin assignment information 1 is a collection of all information about LSI pins. The information includes logic pins, LSI pad numbers, functions, attributes, tester pin numbers, and package pin names. Coordinate, area, signal name used in design, signal name of clock distribution source,
It can be positioned as a database showing the correspondence of the test target flags.

The netlist 2 is a file in which connection information of design logic is described, and the pin correspondence information creating means 31.
Extracts the correspondence between the logic pin and the interface buffer connected to it from this netlist 2, associates it with the LSI pin assignment information 1 (that is, integrates it), and stores it as the LSI pin correspondence information 5. Keep it.

The grouping condition 3 is a condition for directly specifying a logic pin name, a condition for grouping by a function,
It describes the conditions for grouping by attributes, the conditions for grouping by the interface buffer being used, and the conditions for grouping by logical operation between groups. Also, the group creating means 32
A pin that meets the condition shown in the grouping condition 3 is referred to from the LSI pin correspondence information 5 and extracted, and stored as grouping information 6.

That is, the group creating means 32 directly specifies a logical pin, a group that specifies a function, a group that specifies an attribute, a group that specifies an interface buffer being used, and an operation specification between groups ( A grouping condition 3 in which conditions such as a logical product, a logical difference, and a logical sum) are described is input, the pins are grouped, and the grouping information 6 is stored.

The analysis information output means 33, based on the LSI pin correspondence information 5 and the grouping information 6 described above, sets the logic pin, the LSI pad number, the function, the attribute, the tester pin number, for the pin to be tested. Pin name, coordinates, area, signal name used in design, signal name of clock distribution source, interface buffer used,
The group names to which they belong are collected, and all corresponding information is output as analysis information 7. At this time, the present device is configured to have a function of performing a sorting process for each item included in the analysis information 7 such as a logical pin name and a tester pin in accordance with the analysis phase.

Next, the operation of the entire test program creating apparatus according to the first embodiment will be described in detail. FIG. 2 is a flowchart showing the operation of the test program creating apparatus. In this apparatus, first, steps A1 to A4 in FIG.
At, the LSI pin assignment information 1 and the netlist 2 are input to the pin correspondence information creating means 31.

Specifically, the pin correspondence information creating means 31
Traces the netlist 2 from the logical pin to the interface buffer, and stores the correspondence information between the logical pin and the interface buffer (reading the netlist in step A1). Subsequently, the pin correspondence information creating means 31 reads the LSI pin assignment information 1 (step A2) and compares the information with the correspondence information of the logic pin and the interface buffer obtained in step A1 (the logic pin in step A3). Match judgment).

If the logic pins match, in step A4, the above-mentioned logic pin, LSI pad number, function,
Attribute, tester pin number, pin name of package to be mounted,
The coordinates, the area, the signal name used in the design, the signal name of the clock distribution source, and the correspondence information of the used interface buffer are stored as the LSI pin correspondence information 5.

However, if the logic pin described in the LSI pin assignment information 1 is not in the correspondence information of the logic pin obtained in step A1 and the interface buffer (NO in step A3), it matches with the netlist 2. Assuming that there is a problem with the above, this processing is interrupted (error processing in step A8).

In step A5, the grouping condition 3 is input to the group creating means 32 as a grouping condition extracting process. That is, the group creating means 32
While reading the grouping condition 3, the LSI pin correspondence information 5 created in step A4 is compared. If the logical pin name is directly specified, the function is grouped by the function, the attribute is grouped by the interface buffer, and the interface buffer being used is grouped by the interface, the grouping information 6 indicates that the group belongs to the group. , LSI pin correspondence information 5.

Further, when the grouping condition 3 includes a grouping condition by a logical operation between groups, in the subsequent step A6, a logical operation between groups in the grouping information 6 is performed, and the result is
It is added to the LSI pin correspondence information 5 together with the grouping information 6.

Finally, in step A7, as analysis information output processing, the LSI pin correspondence information 5 is sorted by tester pins according to the analysis phase (test on wafer, test placed in LSI case, etc.), Logic pin, tester pin, LSI case pin, package pin, function, attribute, LSI coordinate position, clock distribution source signal name, interface buffer name used, and group name grouped by the test program Output a list of.

FIG. 3 and FIG. 4 are diagrams for explaining the operation of the test program creating apparatus using concrete information. The pin correspondence information creating means 31 performs step B in FIG.
As shown in 1, the correspondence between the logic pin and the interface buffer is extracted from the netlist 2 and
Read pin assignment information 1. Then, the logic pins are compared, and if they match, as shown in step B2, the logic pin, the tester pin, the pin of the LSI case, the pin on the package, the function, the attribute, the coordinate position of the LSI, and the clock distribution source. The signal name of, and the interface buffer name being used are stored as LSI pin correspondence information 5.

The group creating means 32 performs grouping according to the grouping condition 3 shown in FIG. 3 according to the condition for directly specifying the logical pin name, the condition for grouping by the function, the condition for grouping by the attribute, and the interface buffer used. The conditions and the conditions for grouping by the logical operation of the groups are separately extracted (step B3).

Except for the grouping condition by the logical operation, the LSI pin correspondence information 5 is read for each pin, and if it is a pin that matches the condition, the grouping information 6
(The one created in step B3) is added to the LSI pin correspondence information 5 (the one created in step B2) (step B4).

Subsequently, the grouping condition 6 based on the logical operation (step B
4)), the obtained condition is added to the LSI pin correspondence information 5 (step B5 in FIG. 4).

Therefore, the analysis information output means 33 is used in addition to the logic pin, tester pin, LSI case pin, package pin, function, attribute, LSI coordinate position, and clock distribution source signal name. The LSI pin correspondence information 5 having the information of the interface buffer name and the group name to which it belongs is sorted based on the specified items, and is converted into a format that can be used by general spreadsheet software, and is used as analysis information 7. Output (step B6). Note that step B6 is an example of sorting by pins of the LSI case.

As described above, according to the present embodiment, the logic pin of the LSI, the tester pin, the pin of the LSI case, the pin on the package, the function, the attribute, the coordinate position of the LSI, the signal name of the clock distribution source. , Outputs all the corresponding information at the time of creating the test program such as the interface buffer name used and the group name grouped in the test program as analysis information, and for each item (for example, with tester pins) By sorting and outputting to, it becomes easy to test the semiconductor integrated circuit and analyze the failure when the result becomes an error.

Further, by outputting the analysis information in a format that can be used by so-called spreadsheet software on the general market, failure analysis can be made efficient when an error occurs.

Second Embodiment Hereinafter, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 5 is a block diagram showing the configuration of the test program creating apparatus according to the second embodiment. In the figure, the same components as those of the test program creating apparatus according to the first embodiment shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted here.

The test program creating apparatus 4 according to the second embodiment uses the grouping information 5 created by the group creating means 32 to output the test program output means 3
In terms of outputting the test program 9 by 4,
This is different from the test program creating apparatus according to the first embodiment. The test program output means 34 reads the template test program 8 while referring to the grouping information 6 for the group designated for insertion, and outputs the pin to which it belongs as the test program 9.

At this time, the test program output means 34
Has not only the function of outputting the pins belonging to the group, but also the function of controlling the output to the test program 9 at the designated location according to the number of pins belonging to the group.

The template test program 8 referred to here
Is a program in which information about pins and test items that differ for each LSI only describes insertion designation, and other common information such as settings and test flows is written.

Next, the operation of the entire test program creating apparatus according to the second embodiment will be described. FIG. 6 is a flowchart showing the operation of the test program creating apparatus. Note that, in FIG. 6, the processing of steps A1 to A6 is the same as the operation according to the above-described first embodiment shown in FIG. 2, so description thereof will be omitted here.

The test program output means 34 of the test program creating apparatus refers to the grouping information 6 in accordance with the description of the insertion-designated group while reading the template test program 8 described above, and all the pins to which it belongs belong to the test program 9 To (step C7).
Also, if the template test program 8 has output control designation by group name, depending on the number of pins belonging to the group,
Control the output / non-output of the test program at the specified location.

A specific example of the operation of the test program creating apparatus will be described below. FIG. 7 is a diagram showing the operation of the test program creating apparatus by specific information. As shown in the figure, the test program output means 34
Reads the template test program 8 and outputs it as it is, except for the processing targets such as / A, / B, and / IF.

Specifically, the group name specified by / A is processed into a definition format (a pin list is output with "=") (step D1) and is output to the test program 9 (step D4). ). In addition, the group name specified by / B is processed into an array format (step D
2) Output to test program 9 (step D)
4).

On the other hand, for the group specified by / IF, whether to output the program description between / IF and / END according to the conditional expression (0 in FIG. 7) indicated by IF. Is determined (step D3). Then, it outputs to the test program 9 based on the result of the judgment. For example, when the number of pins of the group GRP3 is not 0, the program between / IF and / END is output.

As described above, according to the present embodiment, by preparing the template test program for making the insertion designation description for the different pin information and test items for each LSI, the test items are different for each LSI. Even if LS
A test program for each I can be created, and the program creation becomes very efficient.

[Third Embodiment] Next, a third embodiment of the present invention will be described in detail.
FIG. 8 is a block diagram showing the configuration of the test program creating apparatus according to the third embodiment. In FIG.
The same components as those of the test program creating apparatus according to the second embodiment shown in FIG.
The description thereof will be omitted.

The test program creating apparatus 4 according to the third embodiment includes a test object selecting means 35 which considers a test object pin. This test target selection means 35
When the number of pins to be tested differs depending on the test phase (test on the wafer or mounted on the LSI case), the test target flag for each test phase is provided in the LSI pin assignment information 1 in advance. And
Only the pin information with this test target flag is
By reflecting in the pin correspondence information 5, the pin information of the test target is also output to the analysis information 7 and the test program 9.

Next, a specific example of the operation of the test program creating apparatus will be described. FIG. 9 shows the operation of the test program creating apparatus using specific information. As shown in the figure, the test target selection unit 35 stores a test target flag provided in advance when the pin correspondence information creation unit 31 stores the LSI pin correspondence information 5 while reading the LSI pin assignment information 1. It is determined whether to add to the LSI pin correspondence information 5 (step E1).

With the above configuration, only the pin information with the preset test target flag is stored in the LSI.
Even if the pins to be tested differ depending on the test phase by reflecting in the pin correspondence information, by preparing the template test program, the test program for each LSI can be created and the program can be created efficiently.

That is, even if the number of pins to be tested is different in the test phase, for example, the test on the wafer and the test mounted on the LSI case, the pins to be tested are automatically changed even if the number of pins to be tested is different. It is possible to create an efficient test program by making a decision based on the judgment.

[0049]

As described above, according to the present invention,
Pin correspondence information created based on the information about the logic pins of the semiconductor integrated circuit to be tested, and referring to the pin correspondence information, create the above-mentioned logic pins that match the conditions for dividing a predetermined test group. Even if the test result is an error, the failure analysis of the semiconductor integrated circuit can be performed by editing and outputting the information about the semiconductor integrated circuit and the pins of the test device as analysis information from the grouping information. Easy to do.

Further, by adopting a configuration in which a test program is output based on a program including common information and individual information about the semiconductor integrated circuit and the grouping information, it is possible to cope with the case where the test items differ for each semiconductor integrated circuit. A test program can be created easily.

Further, by controlling the output of the test program according to the number of pins belonging to the test group, that is, by creating the test program in consideration of the test phase and the test target pin at that time, the test target pin is determined. It is possible to make a judgment and efficiently create a test program.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a test program creating device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the test program creating device according to the first embodiment.

FIG. 3 is a diagram for explaining the operation of the test program creation device according to the first embodiment with specific information.

FIG. 4 is a diagram for explaining the operation of the test program creation device according to the first embodiment with specific information.

FIG. 5 is a block diagram showing a configuration of a test program creating device according to a second embodiment of the present invention.

FIG. 6 is a flowchart showing an operation of the test program creating device according to the second embodiment.

FIG. 7 is a diagram showing the operation of the test program creation device according to the second embodiment based on specific information.

FIG. 8 is a block diagram showing a configuration of a test program creating device according to a third embodiment of the present invention.

FIG. 9 is a diagram showing the operation of the test program creation device according to the third embodiment with specific information.

[Explanation of symbols]

1 LSI pin assignment information 2 Netlist 3 Grouping conditions 4 Test program creation device 5 LSI pin correspondence information 6 Grouping information 7 analysis information 8 Template test program 9 test program 31-pin correspondence information creation means 32 group creation means 33 Analysis information output means 34 Test program output means 35 Test target selection means

Claims (4)

(57) [Claims] 1. A test program creating apparatus for creating a test program for a semiconductor integrated circuit, which refers to the means for creating pin correspondence information based on information about a logic pin of the semiconductor integrated circuit, and the pin correspondence information. Means for creating grouping information about the logic pins that match the conditions for dividing a predetermined test group, and information about the pins of the semiconductor integrated circuit and its test device from the pin correspondence information and the grouping information. edit as analysis information, an analysis information generating means for outputting, including the common information and the individual information of the semiconductor integrated circuit
A means for storing a program, and a test based on the grouping information and the program
Control means for outputting a program, and the analysis information creating means specifies the correspondence information.
A format that classifies each item and matches the prescribed test phase
In output, said analysis information, said saw including correspondence information for all pins of the semiconductor integrated circuit and the test apparatus, wherein, before the grouped on the basis of the condition
Depending on the number of pins that belong to the test group,
A test program creation device characterized by controlling the output of a program. 2. The apparatus further comprises means for storing a test target flag for each test phase, and means for reflecting the pin information to which the test target flag has been added to the pin correspondence information, wherein the control means comprises: pins correspondence information to determine the pins under test of the semiconductor integrated circuit to the original after reflection, creating a test program according to claim 1, wherein the controlling the output of the test program in accordance with the determination result apparatus. 3. A method of creating a test program used for testing a semiconductor integrated circuit, the method comprising: creating pin correspondence information based on information about logical pins of the semiconductor integrated circuit; and referring to the pin correspondence information. Then, a step of creating grouping information about the logic pins that match a predetermined test group division condition, and based on the pin correspondence information and the grouping information, all of the semiconductor integrated circuit and its test device. a step of relating the pin edit information including correspondence information as analysis information, and outputs, including a common information and the individual information of the semiconductor integrated circuit
A step of storing the program, and a test based on the grouping information and the program.
And a step of outputting a program, wherein the correspondence information is categorized for each designated item, and a predetermined test is performed.
Output in a format that matches the
In the test, the
Test program according to the number of pins that belong to
The test program is characterized in that the output of the program is controlled.
How to create a system . 4. The method further comprises a step of storing a test target flag for each of the test phases, and a step of reflecting the pin information to which the test target flag is attached in the pin correspondence information. 4. The method according to claim 3 , wherein a pin to be tested of the semiconductor integrated circuit is judged based on the reflected pin correspondence information, and the output of the test program is controlled according to the judgment result.