CN112462243B - Automatic programming method of open-short circuit test system - Google Patents
Automatic programming method of open-short circuit test system Download PDFInfo
- Publication number
- CN112462243B CN112462243B CN202110135004.0A CN202110135004A CN112462243B CN 112462243 B CN112462243 B CN 112462243B CN 202110135004 A CN202110135004 A CN 202110135004A CN 112462243 B CN112462243 B CN 112462243B
- Authority
- CN
- China
- Prior art keywords
- pin
- pins
- chip
- charging time
- current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/52—Testing for short-circuits, leakage current or ground faults
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
- G01R31/54—Testing for continuity
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The embodiment of the invention discloses an automatic programming method of an open-short circuit test system in the technical field of integrated circuits. The method comprises the following steps: s1, selecting a good chip A as a reference standard, and setting the range of current applied by a current source in the device and the range value of charging time; connecting a current source to any one pin B of the chip A which is not tested, and connecting other pins of the chip with GND through a switch matrix; and S2, analyzing the relation between the voltage measured value of the pin B and the applied current value and the charging time. The invention realizes the self-learning and adjusting functions of the chip test program through simple configuration, and can realize the automatic programming processing of the alignment test program in a large-scale integrated circuit open-short circuit test system; through pin testing under different connection modes, classification judgment is combined, and the pins of unknown chips can be distinguished quickly and conveniently.
Description
Technical Field
The embodiment of the invention relates to the technical field of integrated circuits, in particular to an automatic programming method of an open-short circuit test system.
Background
An IC chip (integrated circuit) is an integrated circuit formed by a large number of microelectronic components (transistors, resistors, capacitors and the like) is placed on a plastic substrate to form a chip, almost all seen chips can be called IC chips, the integrated circuit is a miniature electronic device or part, elements such as transistors, diodes, resistors, capacitors, inductors and the like required in one circuit and wiring are interconnected together by adopting a certain process to manufacture the elements on a small or a plurality of small semiconductor wafers or medium substrates, and then the elements are packaged in a tube shell to form a miniature structure with the required circuit function; all the components are structurally integrated, and the miniaturization, low power consumption and high reliability of electronic components are greatly advanced. Most applications in the semiconductor industry today are silicon-based integrated circuits;
in the existing large-scale integrated circuit IC finished product testing process, because the testing time and the cost are very high, a tester usually uses an open short circuit testing system to carry out open short circuit testing on an IC firstly, and eliminates chips with abnormal IC pins, so that the testing time of finished products is saved.
Based on this, the invention designs an automatic programming method of an open-short circuit test system to solve the above problems.
Disclosure of Invention
The embodiment of the invention provides an automatic programming method of an open-short circuit test system, which aims to solve the technical problems mentioned in the background technology.
The embodiment of the invention provides an automatic programming method of an open-short circuit test system. In one possible embodiment, the method comprises the following steps:
s1, selecting a good chip A as a reference standard, and setting the range of current applied by a current source in the system and the range value of charging time; connecting a current source to any one pin B of the chip A which is not tested, and connecting other pins of the chip with GND through a switch matrix;
s2, analyzing the relation between the voltage measurement value of the pin B and the applied current value and the charging time, and calculating and confirming the optimal applied current and the optimal charging time; meanwhile, judging the pin type of the pin B of the chip A according to the voltage measurement value of the pin B; the pin types comprise independent pins, pin groups, capacitive load pins and open circuit pins;
s3, repeating S1-S2 to obtain the applied current values, the charging time and the pin types of all the pins;
s4, classifying according to the pin type characteristics, finishing the setting of judgment conditions of the independent pin, the capacitive load pin and the open circuit pin, and finishing the learning of test programs of the three pins by combining the finished applied current values and charging time of the three pins;
s5, selecting a good chip A as a chip to be tested, connecting a current source to any one of pins M which are pin groups, selecting one of the rest pins N in the pin groups to be connected with GND, suspending the rest pins, applying current to measure the voltage of the M pin, and judging whether the M and N are a group of pins of the same type according to the voltage measurement value of the M pin;
s6, repeating S5, judging to obtain the relation among all pins in the pin group, and obtaining a plurality of groups of subdivided pin groups of different types;
and S7, analyzing the test applied current, the charging time and the good product judgment conditions of each subdivided pin group according to the subdivided pin group obtained in the S6, completing the test program learning of the pin group, and finally combining the test program learning with the test programs of the independent pin, the capacitive load pin and the open circuit pin obtained in the S4 to complete the test program learning of all the pins of the chip A to generate the test program of the formal chip A.
The embodiment of the invention provides an automatic programming method of an open-short circuit test system, and in a feasible scheme, the measurement of the pin voltage in the S2 comprises the following steps:
and applying different currents one by one under the condition of different charging time according to the current application range and the charging time range value of the current source in the S1, and measuring the pin voltage data of the chip A one by one.
Based on the scheme, the self-learning and adjusting functions of the chip test program are realized through simple configuration, and the automatic programming processing of the positive test program can be completed in a large-scale integrated circuit open-short circuit test system; through pin testing under different connection modes, classification judgment is combined, and the pins of unknown chips can be distinguished quickly and conveniently.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a block flow diagram of an automated programming method of the present invention;
FIG. 2 is a pin diagram of a chip under test according to an embodiment of the present invention.
The list of components in the drawings is as follows:
component 1-quality control unit; component 2-adjustable current source; component 3-voltage measurement unit; component 4-matrix switches; component 5-chip under test.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "axial," "radial," "circumferential," and the like are used in the indicated orientations and positional relationships based on the drawings for convenience in describing and simplifying the description, but do not indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the invention.
In the present invention, unless otherwise specifically stated or limited, the terms "mounted," "connected," "fixed," and the like are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally formed; the connection can be mechanical connection, electrical connection or communication connection; either directly or indirectly through intervening media, either internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
Fig. 1 is an automatic programming method of an open/short circuit test system provided by the present invention, which includes the following steps:
s1, selecting a good chip A as a reference standard, and setting the range of current applied by a current source in the system and the range value of charging time; connecting a current source to any one pin B of the chip A which is not tested, and connecting other pins of the chip with GND through a switch matrix;
s2, analyzing the relation between the voltage measurement value of the pin B and the applied current value and the charging time, and calculating and confirming the optimal applied current and the optimal charging time; meanwhile, judging the pin type of the pin B of the chip A according to the voltage measurement value of the pin B; the pin types comprise independent pins, pin groups, capacitive load pins and open circuit pins;
s3, repeating S1-S2 to obtain the applied current values, the charging time and the pin types of all the pins;
s4, classifying according to the pin type characteristics, finishing the setting of judgment conditions of the independent pin, the capacitive load pin and the open circuit pin, and finishing the learning of test programs of the three pins by combining the finished applied current values and charging time of the three pins;
s5, selecting a good chip A as a chip to be tested, connecting a current source to any one of pins M which are pin groups, selecting one of the rest pins N in the pin groups to be connected with GND, suspending the rest pins, applying current to measure the voltage of the M pin, and judging whether the M and N are a group of pins of the same type according to the voltage measurement value of the M pin;
s6, repeating S5, judging to obtain the relation among all pins in the pin group, and obtaining a plurality of groups of subdivided pin groups of different types;
and S7, analyzing the test applied current, the charging time and the good product judgment conditions of each subdivided pin group according to the subdivided pin group obtained in the S6, completing the test program learning of the pin group, and finally combining the test program learning with the test programs of the independent pin, the capacitive load pin and the open circuit pin obtained in the S4 to complete the test program learning of all the pins of the chip A to generate the test program of the formal chip A.
It is not difficult to find that in the automatic programming learning process of the IC chip by using the automatic programming method of the open-short circuit test system of the invention, by using a chip A which is verified to be good as a reference, setting the current application range and the charging time range of a current source in the device, connecting the current source to any one pin of the chip to be tested, connecting other pins of the chip A to GND by using a switch matrix, applying different currents one by one under the condition of different charging times by the current source according to the set current range and the charging time range, measuring the voltage of the pin of the chip A, confirming the best applied current and charging time by judging the fluctuation condition of the measured value, and judging the classification of the chip pins according to the measured value, wherein the pin classification is preferably independent pin, pin group, capacitive load pin and open-circuit pin, in this way, the test conditions and judgment conditions of the independent pin, the capacitive load pin and the open circuit pin are obtained; and then automatically learning and testing the pin group type pins of the reference chip A, when independently learning the pin group type pins, connecting a current source to any one pin M in the pin group of the chip A to be tested, selecting one pin N of the remaining short-circuit pin group one by one to be connected with GND, suspending the remaining pins of the chip, applying current and measuring the voltage of the pin M of the chip, judging whether the pins M and N are of the same group type, further obtaining the test conditions and the judgment conditions of the pin group type pins and each pin group, and rapidly and conveniently distinguishing unknown type chip pins by testing the pins in different connection modes and combining classification judgment.
Optionally, the measuring of the pin voltage in S2 includes the following steps:
and applying different currents one by one under the condition of different charging time according to the current application range and the charging time range value of the current source in the S1, and measuring the pin voltage data of the chip A one by one. It should be noted that, in the present embodiment, in the pin voltage measurement process, the pins except the pins connected to the current source are connected to the GND one by one, and the voltage values after connection are measured, so as to determine the classification condition of all the pins of the chip a according to the measured values.
In addition, the pin classification information in S2 includes an independent pin, a pin group, a capacitive load pin, and an open pin; and the classification information of the pins is collected so as to perform subdivision test on the pins of the pin group type.
More specifically, the pin M in S5 is connected to the current source, and after the pin N is connected to GND, the remaining pin is suspended, so that interference caused by the remaining pin with automatic learning after the pin M and the pin N are connected respectively can be avoided.
Examples
As shown in fig. 2, the chip under test has 14 pins, which include special pins: VCC, GND (there may be capacitive load); standard individual input-output pins: 1A-4A, 1Y-4Y; two input and output pin groups: 5A, 5Y; in general, in a test factory, a test program developer does not know the pin type and the mutual relationship between pins of a tested chip, or because the number of pins is very large, the conventional method is very difficult to write a chip test program. By utilizing the automatic programming method of the open-short circuit test system, the work of S1-S7 is automatically completed through the control unit:
1. preparing a sample and testing conditions;
2. completing scanning measurement of pins 1-14, and respectively obtaining test conditions and judgment standards of special pins (capacitive load pins) VCC and GND, test conditions of single pins 1A-4A and 1Y-4Y, and judgment that 5A and 5Y are pin groups;
3. measuring the relations between the 11 feet and the 13, 10 and 12 feet from 5A (11 feet), and distinguishing the 11 feet and the 13 feet as a group;
4. measuring the relation between the 10 feet and the 12 feet from 5Y (10 feet), and distinguishing the 10 feet and the 12 feet as a group;
5. completing the test condition and judgment standard of the 5A pin group and the test condition and judgment standard of the 5Y pin group;
6. and combining the test conditions and qualified judgment conditions of VCC, GND, 1-4A and 1-4Y and the test conditions and qualified judgment conditions of the 5A and 5Y pin groups to finish the automatic learning of the test program of the chip.
In the present invention, unless otherwise explicitly specified or limited, the first feature "on" or "under" the second feature may be directly contacting the first feature and the second feature or indirectly contacting the first feature and the second feature through an intermediate.
Also, a first feature "on," "above," and "over" a second feature may mean that the first feature is directly above or obliquely above the second feature, or that only the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature may be directly under or obliquely under the first feature, or may simply mean that the first feature is at a lower level than the second feature.
In the description herein, reference to the description of the term "one embodiment," "some embodiments," "an example," "a specific example" or "some examples," or the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (2)
1. An automatic programming method of an open-short circuit test system is characterized by comprising the following steps:
s1, selecting a good chip A as a reference standard, and setting the range of current applied by a current source in the system and the range value of charging time; connecting a current source to any one pin B of the chip A which is not tested, and connecting other pins of the chip with GND through a switch matrix;
s2, analyzing the relation between the voltage measurement value of the pin B and the applied current value and the charging time, and calculating and confirming the optimal applied current and the optimal charging time; meanwhile, judging the pin type of the pin B of the chip A according to the voltage measurement value of the pin B; the pin types comprise independent pins, pin groups, capacitive load pins and open circuit pins;
s3, repeating S1-S2 to obtain the applied current values, the charging time and the pin types of all the pins;
s4, classifying according to the pin type characteristics, finishing the setting of judgment conditions of the independent pin, the capacitive load pin and the open circuit pin, and finishing the learning of test programs of the three pins by combining the finished applied current values and charging time of the three pins;
s5, selecting a good chip A as a chip to be tested, connecting a current source to any one of pins M which are pin groups, selecting one of the rest pins N in the pin groups to be connected with GND, suspending the rest pins, applying current to measure the voltage of the M pin, and judging whether the M and N are a group of pins of the same type according to the voltage measurement value of the M pin;
s6, repeating S5, judging to obtain the relation among all pins in the pin group, and obtaining a plurality of groups of subdivided pin groups of different types;
and S7, analyzing the test applied current, the charging time and the good product judgment conditions of each subdivided pin group according to the subdivided pin group obtained in the S6, completing the test program learning of the pin group, and finally combining the test program learning with the test programs of the independent pin, the capacitive load pin and the open circuit pin obtained in the S4 to complete the test program learning of all the pins of the chip A to generate the test program of the formal chip A.
2. The automatic programming method for open-short circuit test system of claim 1, wherein the step of measuring the pin voltage in S2 comprises the steps of:
and applying different currents one by one under the condition of different charging time according to the current application range and the charging time range value of the current source in the S1, and measuring the pin voltage data of the chip A one by one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110135004.0A CN112462243B (en) | 2021-02-01 | 2021-02-01 | Automatic programming method of open-short circuit test system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110135004.0A CN112462243B (en) | 2021-02-01 | 2021-02-01 | Automatic programming method of open-short circuit test system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112462243A CN112462243A (en) | 2021-03-09 |
| CN112462243B true CN112462243B (en) | 2021-04-27 |
Family
ID=74802396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110135004.0A Active CN112462243B (en) | 2021-02-01 | 2021-02-01 | Automatic programming method of open-short circuit test system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112462243B (en) |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002333991A (en) * | 2001-05-09 | 2002-11-22 | Nec Corp | Test program preparing device and its method |
| TW200424541A (en) * | 2003-05-13 | 2004-11-16 | Via Tech Inc | Auto grouping method for testing integrated circuit devices on burn-in board |
| US7047467B1 (en) * | 2002-01-09 | 2006-05-16 | Xilinx, Inc. | Structure and method for verifying data in a non-JTAG device from a JTAG device with microcontroller |
| CN101706540A (en) * | 2009-12-04 | 2010-05-12 | 首都师范大学 | Programmable integrated circuit automatic testing and sorting system |
| CN101949990A (en) * | 2010-09-25 | 2011-01-19 | 苏州华芯微电子股份有限公司 | IC pin open short circuit test method |
| CN103063975A (en) * | 2012-12-26 | 2013-04-24 | 成都市中州半导体科技有限公司 | Open circuit and short circuit testing system and method |
| CN104133172A (en) * | 2014-08-08 | 2014-11-05 | 上海华力微电子有限公司 | Novel test development method for improving simultaneous test number |
| CN106970311A (en) * | 2016-01-14 | 2017-07-21 | 北京君正集成电路股份有限公司 | A kind of chip detecting method |
| CN108226751A (en) * | 2017-12-14 | 2018-06-29 | 芯海科技（深圳）股份有限公司 | A kind of multiprocessor collaboration chip performance assessment system and method |
| US10067183B2 (en) * | 2016-06-21 | 2018-09-04 | International Business Machines Corporation | Portion isolation architecture for chip isolation test |
| CN110261757A (en) * | 2019-06-10 | 2019-09-20 | 南京宏泰半导体科技有限公司 | A kind of number isolating chip test method and system |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080104448A1 (en) * | 2006-10-30 | 2008-05-01 | Kenji Tamura | Testing apparatus for semiconductor device |
-
2021
- 2021-02-01 CN CN202110135004.0A patent/CN112462243B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002333991A (en) * | 2001-05-09 | 2002-11-22 | Nec Corp | Test program preparing device and its method |
| US7047467B1 (en) * | 2002-01-09 | 2006-05-16 | Xilinx, Inc. | Structure and method for verifying data in a non-JTAG device from a JTAG device with microcontroller |
| TW200424541A (en) * | 2003-05-13 | 2004-11-16 | Via Tech Inc | Auto grouping method for testing integrated circuit devices on burn-in board |
| CN101706540A (en) * | 2009-12-04 | 2010-05-12 | 首都师范大学 | Programmable integrated circuit automatic testing and sorting system |
| CN101949990A (en) * | 2010-09-25 | 2011-01-19 | 苏州华芯微电子股份有限公司 | IC pin open short circuit test method |
| CN103063975A (en) * | 2012-12-26 | 2013-04-24 | 成都市中州半导体科技有限公司 | Open circuit and short circuit testing system and method |
| CN104133172A (en) * | 2014-08-08 | 2014-11-05 | 上海华力微电子有限公司 | Novel test development method for improving simultaneous test number |
| CN106970311A (en) * | 2016-01-14 | 2017-07-21 | 北京君正集成电路股份有限公司 | A kind of chip detecting method |
| US10067183B2 (en) * | 2016-06-21 | 2018-09-04 | International Business Machines Corporation | Portion isolation architecture for chip isolation test |
| CN108226751A (en) * | 2017-12-14 | 2018-06-29 | 芯海科技（深圳）股份有限公司 | A kind of multiprocessor collaboration chip performance assessment system and method |
| CN110261757A (en) * | 2019-06-10 | 2019-09-20 | 南京宏泰半导体科技有限公司 | A kind of number isolating chip test method and system |
Non-Patent Citations (1)
| Title |
|---|
| FPGA/CPLD的管脚设置对信号完整性的影响分析研究;郭利文等;《现代电子技术》;20150901;第38卷(第17期);第61-64页 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112462243A (en) | 2021-03-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7519882B2 (en) | Intelligent binning for electrically repairable semiconductor chips | |
| US6756804B2 (en) | Semiconductor integrated circuit device | |
| US20030213953A1 (en) | Integrated circuit chips and wafers including on-chip test element group circuits, and methods of fabricating and testing same | |
| US5764650A (en) | Intelligent binning for electrically repairable semiconductor chips | |
| CN101510520B (en) | Test method for asynchronously repairing and adjusting silicon wafer with anti-interference | |
| US6653827B2 (en) | Analog signal test circuit and method | |
| US8036848B2 (en) | Semiconductor wafer testing apparatus and method of testing semiconductor wafer | |
| CN112462243B (en) | Automatic programming method of open-short circuit test system | |
| US6489799B1 (en) | Integrated circuit device having process parameter measuring circuit | |
| CN100511622C (en) | Method for emending output current by amending semiconductor pin test voltage | |
| CN117648892A (en) | Method and system for dynamically adjusting aging test parameters by using AI | |
| JP3784479B2 (en) | Circuit board inspection method | |
| CN208655575U (en) | A kind of multistation IC fuses trim test macro | |
| CN105510803A (en) | Integrated circuit testing device and method | |
| CN217689268U (en) | Chip detection circuit and test system | |
| JP4137082B2 (en) | Semiconductor device testing equipment | |
| JP3865185B2 (en) | Semiconductor device, test apparatus and test method thereof | |
| CN115097287A (en) | Chip pin open-short circuit testing device and method based on positive and negative voltages | |
| CN109270420B (en) | Method for testing wafer | |
| JP4909192B2 (en) | Capacitor capacity measuring device | |
| KR100231649B1 (en) | A test board having a capacitor charging circuit and a test method using the test board | |
| CN118130902A (en) | Structure and method for testing resistor and WAT testing device | |
| CN115421024A (en) | Circuit testing method and device and storage medium | |
| CN117491842A (en) | Method for optimizing DC parameter accuracy and shortening test time | |
| US8836355B2 (en) | Dynamic testing based on thermal and stress conditions |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 210000 floor 2, building 26, South Park, Jiangsu Kecheng science and Technology Industrial Park, No. 19, Lanhua Road, Pukou District, Nanjing, Jiangsu Province Patentee after: Nanjing Hongtai Semiconductor Technology Co.,Ltd. Address before: Room b2411, 24 / F, block B, Kechuang headquarters building, Kechuang Plaza, 320 pubin Avenue, Jiangpu street, Pukou District, Nanjing City, Jiangsu Province, 210000 Patentee before: Nanjing Hongtai Semiconductor Technology Co.,Ltd. |