JP3616212B2 - Megacell test support device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a megacell test support apparatus that supports a testability design of a megacell incorporated in an LSI (Large Scale Integrated circuit).
[0002]
[Prior art]
In recent years, large-scale cells called megacells have been used in LSI design. In designing LSIs using megacells, layout patterns for realizing relatively large functional blocks such as RAM, ROM, and multipliers are created in advance as hard macros, and the design specifications are based on the hard macros. The combined megacell is generated by a megacell generator. In this case, the megacell generator is given parameters such as the number of bits and the number of words determined by the design specifications, and generates a megacell based on the parameters.
[0003]
There is a built-in self test method (hereinafter referred to as “BIST method”) as a test method for checking that a megacell incorporated in an LSI operates functionally and correctly. In the BIST method, as shown in FIG. 10, a test pattern generation circuit 10 and a test result determination circuit 14 for testing a circuit block 12 in an LSI such as a megacell are incorporated in the LSI. As a technique for realizing the test pattern generation circuit 10 and the like, conventionally, (1) a technique of generating a megacell module including the test pattern generation circuit 10 and the like by a megacell generator, and (2) a test pattern generation circuit 10 A megacell generator or LSI designer creates data (hereinafter referred to as “HDL data”) that describes the configuration at the register transfer level in a hardware description language, and a logic synthesis tool from the HDL data. Is used to generate circuit data at the gate level of the test pattern generation circuit 10 and the like.
[0004]
In addition to the BIST, an external pin connected to the megacell inside the LSI is provided in addition to the BIST, and a test pattern is supplied from the outside of the LSI to the megacell by using the external pin. There is a system test method (hereinafter referred to as “MUX system test method”). In the MUX test method, as shown in FIG. 11, a test mode pin 20, a test pattern input pin 22 and a test result output pin 24 are provided as test external pins, and circuit blocks inside the LSI such as a megacell to be tested. A multiplexer (MUX) 28 is provided on the input side of 30. Then, by controlling the multiplexer 28 with a signal supplied from the test mode pin 20, in the test mode, instead of the signal output from the logic 26 inside the LSI, a test signal (test signal) input from the test pattern input pin 22 Pattern) is supplied to the circuit block 30 inside the LSI, the signal output from the circuit block 30 is taken out from the test result output pin 24, and the circuit block 30 is functioning correctly based on the extracted signal. Determine whether or not.
[0005]
[Problems to be solved by the invention]
The BIST method has the advantage that the load on the tester can be greatly reduced. However, when the BIST method is adopted in the test of the megacell, the test pattern obtained from the test pattern generation circuit automatically generated by the megacell generator is the megacell. The test pattern cannot be changed by the designer. On the other hand, if the designer himself wants to create HDL data such as a test pattern generation circuit, learning of a hardware description language (hereinafter referred to as “HDL”) is required.
[0006]
In order to avoid the above problem, it is conceivable to adopt the MUX test method, but the circuit configuration of the LSI differs greatly depending on which of the BIST method and the MUX test method is used (see FIGS. 10 and 11). . Therefore, it is desirable to determine which test method to adopt as early as possible in the design. For this purpose, information for selecting a test method such as an increase in chip area when the BIST method is adopted and a test load (test time) when the MUX method test method is adopted at an early stage of design. It is necessary to obtain.
[0007]
Therefore, in the present invention, it is possible to generate HDL data such as a test pattern generation circuit for a megacell without requiring acquisition of HDL, it is possible to change a test pattern by a designer, and a test method at an early stage of design An object of the present invention is to provide a megacell test support apparatus that can obtain information for selection.
[0008]
[Means for Solving the Problems]
A first megacell test support apparatus according to the present invention, which has been made to solve the above problems, is a megacell test support apparatus for facilitating a test of a megacell constituting an integrated circuit,
Storage means for storing a database formed by collecting graphical data expressed by a state transition diagram expanded so that various processing algorithms defining the test content of the megacell can be described in the processing state in an arbitrary state;
Reading means for reading a megacell generator parameter file including identification information specifying a bit width of the bus in the megacell and a test algorithm used for the test of the megacell;
Extraction means for extracting graphical data representing the test algorithm specified by the parameter file from the database;
In order to perform the built-in self-test on the megacell according to the test algorithm expressed by the graphic data while matching the content of the graphic data extracted by the extraction means with the bit width of the bus specified in the parameter file Hardware description generation means for generating hardware description data in which the configuration at the register transfer level of the test pattern generation circuit and the test result determination circuit is described in a hardware description language;
It is set as the structure provided.
[0009]
A second megacell test support apparatus according to the present invention is the first megacell test support apparatus,
A computer program for generating a test pattern for the megacell according to an algorithm represented by the graphical data while matching the content of the graphical data extracted by the extracting means with the bit width specified in the parameter file It further comprises code generation means for generating a code.
[0010]
【The invention's effect】
According to the first megacell test support apparatus of the present invention, graphic data representing the algorithm specified by the parameter file is extracted from the test algorithms collected in the database, and the graphic data and the parameter file are extracted. HDL data for the BIST test pattern generation circuit and test result determination circuit is generated based on the bit width of the bus specified in. Therefore, an LSI designer only needs to prepare a parameter file corresponding to a megacell to be incorporated into an LSI to be designed (hereinafter referred to as “target megacell”), and HDL is used for designing a test pattern generation circuit for the megacell. There is no need to learn. In addition, unlike the conventional case where HDL data such as a test pattern generation circuit is generated by a megacell generator, the test pattern can be changed by the designer by modifying the parameter file, and the degree of design freedom increases. In addition, since the data stored as the database is a graphical representation of the test algorithm using an extended state transition diagram, the test contents defined by the test algorithm can be easily understood. This makes it easy to accumulate test algorithms as a database, and also makes it easy to select an appropriate test algorithm to be used for megacell testing from the database, improving the work efficiency of test pattern creation. .
[0011]
According to the second megacell test support apparatus of the present invention, a test pattern generation code is generated together with the HDL data of the BIST test pattern generation circuit and the test result determination circuit for the algorithm selected from the database. Then, by compiling and executing this test pattern generation code, a test pattern can be generated and the test time when the MUX method test method is adopted can be estimated. On the other hand, the HDL data describes the configuration of a BIST test pattern generation circuit or the like at the register transfer level, and using this data, the number of gates after logic synthesis of the test pattern generation circuit or the like using an existing logic synthesis tool (This corresponds to an increase in the chip area due to the adoption of the BIST method). Therefore, based on the estimation of the test time and the number of gates after logic synthesis of the test pattern generation circuit or the like, which of the BIST method and the MUX method test method should be adopted in the megacell test at an early stage of LSI design. Can be determined.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
<Configuration of Embodiment>
FIG. 1 is a block diagram showing a hardware configuration of a megacell test support apparatus according to an embodiment of the present invention. The hardware of the megacell test support device is a computer such as an engineering workstation, and includes a CPU 101, a memory 102, an input / output control device 103, a display device 104 such as a CRT display, and an external storage device 105 such as a magnetic disk device. , And an input device 106 such as a mouse. The megacell test support apparatus functions as a test support apparatus for a megacell incorporated in an LSI when the CPU 101 executes a predetermined program stored in the memory 102.
[0013]
FIG. 2 is a diagram showing input data and output data in such a megacell test support apparatus, and these input / output data are stored in the external storage device 105. Megacell generator parameter file (hereinafter, also simply referred to as “parameter file”) 202 includes data input from the outside by megacell test support apparatus main body 200 (that is, a portion including CPU 101, memory 102, and input / output control apparatus 103). And data included in the test algorithm database 201. As data output from the megacell test support apparatus body 200, the configuration of the BIST test pattern generation circuit and the test result determination circuit is described at the register transfer level. There are HDL data (hereinafter referred to as “BIST HDL data”) 203, a computer program code (hereinafter referred to as “test pattern generation code”) 204 for generating a test pattern, and a bus width reference file 205.
[0014]
The parameter file 202 is originally a file that is read by the megacell generator 210 in order to obtain various parameters necessary for generating the design data 211 of the target megacell, and includes the type of megacell, various control pins, address bus, and data bus. Information for designating the bit width. In this embodiment, the megacell test support apparatus main body 200 also reads this parameter file 202, but the parameter file 202 in this embodiment is used for the test of the target megacell in addition to the above information, as shown in FIG. Contains identification information that specifies the test algorithm.
[0015]
The database 201 is a collection of various test algorithms that define the test contents of megacells. Many test algorithms for megacells can be expressed by an extended state transition diagram, as represented by a marching pattern for RAM verification (MARCHING PATTERN). In view of this, the database 201 in the present embodiment collects graphical data (hereinafter referred to as “algorithm data”) in which the test algorithm is expressed by an extended state transition diagram. Here, the “extended state transition diagram” is a state transition diagram expanded so that description of processing contents (description of assignment statements, arithmetic expressions, etc.) in an arbitrary state is possible. As such an extended state transition diagram, for example, an “open chart” can be used (Takamitsu Yamada, Takashi Yasui, Yoshiharu Oka, “Designing a sorting circuit using a function entry tool”, CQ publisher, magazine “Interface” "See March 1995, pp. 160-166). Such an extended state transition diagram can also be considered as a kind of flowchart.
[0016]
As a test algorithm for megacells to be collected in the database 201, for example, for a synchronous RAM megacell specified in the parameter file of FIG. 4, a marching pattern, a galloping pattern, a walking pattern (Walking) There are algorithms such as “pattern”, and these can be expressed by an extended state transition diagram. Among these algorithms, the marching pattern algorithm is as follows. That is, when the RAM as the target mega cell has N bits of memory cells, the test is performed by the following processes (1) to (4).
(1) Write “0” in order from the first bit to the Nth bit.
(2) Read “0” and write “1” sequentially from the 1st bit to the Nth bit.
(3) Read “1” and write “0” sequentially from the Nth bit to the first bit.
(4) The processes (1) to (3) are repeated by exchanging “0” and “1”.
[0017]
FIG. 5 shows the marching pattern algorithm input and edited using an editor for extended state transition diagrams that can be used in an LSI functional design support system or the like. In the expanded state transition diagram of FIG. 5, “CE, WE” represents a write command, “CE, RE” represents a read command, “DO” represents a variable name indicating the value of read data, “DIN” "Is a variable name indicating the value of the write data, and" ADD_BUS_WIDTH "indicates the bit width of the address bus.
[0018]
Algorithm data used for the test of the target megacell is extracted from the database 201 as described later. At this time, in order to enable the search of the database 201 by the name of the test algorithm, in this embodiment, as shown in FIG. 6, a structure having character string data indicating the names of the algorithms collected in the database 201 as members. A list in which bodies are connected by a pointer is created in advance and stored in the memory 102.
[0019]
The BIST HDL data 203 is HDL data in which the configuration of the test pattern generation circuit and the test result determination circuit to be incorporated in the LSI when the test of the target megacell is performed by the BIST method is described at the register transfer level.
[0020]
The test pattern generation code 204 is a code of a computer program that generates a test pattern used when a target megacell is tested by the MUX method.
[0021]
The bus width reference file 205 is a file that stores information for combining the BIST HDL data 203 and the test pattern generation code 204 with the bit width of the address bus or data bus included in the target megacell.
[0022]
<Operation of Embodiment>
FIG. 3 is a flowchart showing the operation of the megacell test support apparatus of this embodiment. The operation of the megacell test support apparatus will be described with reference to this flowchart.
[0023]
When the LSI designer creates the parameter file 201 for the megacell (target megacell) to be incorporated into the LSI to be designed (see FIG. 4), the megacell test support apparatus is based on a predetermined program stored in the memory 102 as follows. To work.
[0024]
First, in step S301, the parameter file 202 for the megacell generator is read. FIG. 4 shows an example of description contents of the parameter file 202. This example shows that the synchronous RAM is created as a megacell. In addition to specifying 32 as the bit width of the address bus and 16 as the bit width of the data bus, as a test algorithm for the megacell, “MARCHING PATTERN” is designated.
[0025]
In step S302, the expanded state transition diagram data (algorithm data) describing the algorithm used for the test of the target megacell is read from the test algorithm database 201. The algorithm used for the test of the target megacell is selected in advance by the LSI designer from the database 201, and the name of the selected test algorithm is described in the parameter file 202 as described above (see FIG. 4). In this step S302, the database 201 is searched based on the algorithm name designated here, and the algorithm data used for the test of the target megacell is extracted. For the search of the database 201 at this time, the above-described list (FIG. 6) stored in the memory 102 is used.
[0026]
After the algorithm data is extracted from the database 201 as described above, a bus width reference file 205 used for matching the bit widths of the address bus and the data bus is created in step S303. Two bus width reference files 205 are created using the bit widths of the address bus and data bus specified in the parameter file 202. One of the two files is referred to in the BIST HDL data 203 generated in the subsequent step S304, and the other is referred to in the test pattern generation code 204 generated in the subsequent step S305. 7 shows a bus width reference file 205 corresponding to the bit width specified in the parameter file of FIG. 4, and FIG. 7 (a) shows the contents of the file referred to by the BIST HDL data 20, FIG. 7B shows the contents of the file referred to by the test pattern generation code 204. These bus width reference files define macros for “ADD_BUS_WIDTH” indicating the bit width of the address bus and “DATA_BUS_WIDTH” indicating the bit width of the data bus.
[0027]
In the next step S304, the BIST HDL data 203 is generated from the algorithm data. That is, HDL data of a test pattern generation circuit and a test result determination circuit for performing a test by the BIST method is generated according to the algorithm expressed by the algorithm data extracted in step S302. The generation of the BIST HDL data 203 can be easily performed by a known technique for converting the register transfer level HDL data that can be logically synthesized from the extended state transition diagram data. That is, for example, in Japanese Patent Application Laid-Open No. 3-41567, state transition diagrams and function diagrams (a combination of both diagrams correspond to the above-mentioned extended state transition diagram) are registered in a database in an interactive format as CAD (Computer Aided Design) data. A state transition diagram design system that outputs a file by converting the database into a corresponding hardware description language is disclosed. By using the technology in this system, the BIST HDL data 203 can be generated.
[0028]
The BIST HDL data 203 generated in step S304 includes descriptive data referring to the bus width reference file shown in FIG. 7A, so that the bus bit width specified in the parameter file 202 can be obtained. The alignment of the BIST HDL data 203 is performed.
[0029]
If the parameter file 202 has the contents shown in FIG. 4, data as shown in FIG. 8 is generated as the BIST HDL data 203 in step S304. The HDL data in FIG. 8 uses Verilog-HDL as a hardware description language, and a test pattern generation circuit and a test result determination circuit for testing the target megacell by the BIST method according to the marching pattern algorithm shown in FIG. Is described at the register transfer level. The 'include instruction 801 on the first line in the HDL data in FIG. 8 is an instruction for referring to the bus reference file in FIG. 7A described above, and thus “ADD_BUS_WIDTH” and “DATA_BUS_WIDTH” in the BIST HDL data 203 4 is given the value specified in the parameter file of FIG. 4 (adjustment of the bus bit width).
[0030]
After generating the BIST HDL data 203 as described above, in step S305, a test pattern generation code 204 corresponding to the algorithm data extracted in step S302 is generated. The test pattern generation code 204 is generated by converting the format of the conversion destination in the above-described known technique (for example, see Japanese Patent Application Laid-Open No. 3-41567) for converting the register transfer level HDL data that can be logically synthesized from the extended state transition diagram data. This can be done by changing from HDL to a predetermined programming language. The test pattern generation code 204 generated in this way is a computer program written in a predetermined programming language, and a test pattern for the target megacell can be generated by compiling and executing the computer program on the computer.
[0031]
The test pattern generation code 204 generated in step S305 includes a code for referring to the bus width reference file shown in FIG. 7B, whereby the test for the bus bit width specified in the parameter file 202 is performed. The pattern generation code 204 is adjusted.
[0032]
If the parameter file has the contents shown in FIG. 4, a code as shown in FIG. 9 is generated as the test pattern generation code 204 in step S305. The code in FIG. 9 describes a computer program in C language that generates a test pattern for testing a target megacell by the MUX test method according to the marching pattern algorithm shown in FIG. The #include instruction 802 on the first line in the computer program of FIG. 9 is an instruction for referring to the bus reference file of FIG. (B) described above. The value specified in the parameter file of FIG. 4 is given (the bit width adjustment of the bus).
[0033]
When the test pattern generation code 204 as described above is generated, the operation of the megacell test support apparatus for one target megacell ends.
[0034]
<Effect of embodiment>
According to the embodiment, based on the designation in the parameter file 202, data indicating the test algorithm for the target megacell is extracted from the database 201 in which the test algorithms for megacell are collected (step S302 in FIG. 3), and A bus width reference file 205 indicating the bit width of the megacell address bus and data bus is generated. Then, using the extracted algorithm data and the generated bus width reference file 205, the BIST HDL data 203 corresponding to the designation in the parameter file 202 (the configuration of the test pattern generation circuit and the test result determination circuit is transferred by register) HDL data described by level) is generated (step S304 in FIG. 3). Therefore, the LSI designer only needs to prepare the parameter file 202 corresponding to the target megacell, and does not need to learn HDL for designing a test pattern generation circuit for the megacell. In addition, unlike the conventional case where HDL data such as a test pattern generation circuit is generated by a megacell generator, the test pattern can be changed by the designer by modifying the parameter file 202 and the degree of freedom of design is increased. To do.
[0035]
Further, according to the present embodiment, the test pattern generation code 204 is generated together with the BIST HDL data 203 for the algorithm selected from the database 201 (see S305 in FIGS. 2 and 3), and the test pattern generation code 204 is generated. Can be compiled and executed to generate a test pattern and estimate the test time when the MUX method test method is adopted. On the other hand, the BIST HDL data 203 is HDL data at the register transfer level. Using this data, the number of gates after logic synthesis such as a test pattern generation circuit using an existing logic synthesis tool (this is the chip area by adopting the BIST method). Corresponding to the increase amount). Therefore, based on the estimation of the test time and the number of gates after logic synthesis of the test pattern generation circuit or the like, it is determined at an early stage of the design whether the BIST method or the MUX method test method is adopted in the megacell test. be able to.
[0036]
Furthermore, according to the above embodiment, the data indicating the algorithm to be stored as the database 201 is a graphical representation of the test algorithm using the extended state transition diagram (see FIG. 5). Easy to understand. This makes it easy to accumulate test algorithms as a database and makes it easy to select an appropriate test algorithm to be used for testing the target megacell from the database, improving the work efficiency of test pattern creation. To do.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a hardware configuration of a megacell test support apparatus according to an embodiment of the present invention.
FIG. 2 is a diagram showing input data and output data in the megacell test support apparatus of the embodiment.
FIG. 3 is a flowchart showing the operation of the megacell test support apparatus of the embodiment.
FIG. 4 is a view showing an example of the contents of a parameter file read by the megacell test support apparatus of the embodiment.
FIG. 5 is an extended state transition diagram showing a marching pattern algorithm, which is an example of a megacell test algorithm.
FIG. 6 is a diagram showing a configuration of a list created in a memory in order to search for a test algorithm in the database according to the embodiment.
FIG. 7 is a view showing an example of the contents of a bus width reference file generated by the megacell test support apparatus of the embodiment.
FIG. 8 is a diagram showing an example of BIST HDL data generated by the megacell test support apparatus of the embodiment.
FIG. 9 is a diagram showing an example of a test pattern generation code generated by the megacell test support apparatus of the embodiment.
FIG. 10 is a block diagram showing a configuration of an LSI when a BIST method is employed.
FIG. 11 is a block diagram showing a configuration of an LSI when a MUX test method is employed.
[Explanation of symbols]
101 ... CPU
102 ... Memory
105 ... External storage device
200 ... Megacell test support device
201 ... Database of test algorithms
202 ... Parameter file for megacell generator
203 ... HDL data for BIST
204 ... Test pattern generation code
205 ... Bus width reference file

Claims (2)

A megacell test support apparatus for facilitating a test of a megacell constituting an integrated circuit,
Storage means for storing a database formed by collecting graphical data expressed by a state transition diagram expanded so that various processing algorithms for defining the test contents of the megacell can be described in processing contents in an arbitrary state;
Reading means for reading a megacell generator parameter file including identification information specifying a bit width of the bus in the megacell and a test algorithm used for the test of the megacell;
Extracting means for extracting graphical data representing the test algorithm specified by the parameter file from the database;
In order to perform the built-in self-test on the megacell according to the test algorithm expressed by the graphic data while matching the content of the graphic data extracted by the extraction means with the bit width of the bus specified in the parameter file Hardware description generation means for generating hardware description data in which the configuration at the register transfer level of the test pattern generation circuit and the test result determination circuit is described in a hardware description language;
A megacell test support device comprising: In the megacell test support device according to claim 1,
A computer program for generating a test pattern for the megacell according to an algorithm represented by the graphical data while matching the content of the graphical data extracted by the extracting means with the bit width specified by the parameter file A megacell test support apparatus, further comprising code generation means for generating a code.

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