JP3426271B2 - Address generation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device for generating a write address and a read address when a delay between write data and read data is determined. This is the address generation circuit to be used. 2. Description of the Related Art As shown in FIG. 6, when a memory cell array of a semiconductor memory device is accessed sequentially, a FIFO (First In First Ou) is used.
t) When the delay amount between the write data and the read data is determined in the memory, since the memory cells are arranged in a matrix, the memory operation is performed while the write address and the read address have the determined offset j. become. FIG. 7 shows the timing of this memory operation. FIG. 8 is a block diagram of a conventional address generation circuit. 8, 81 is a counter, 82 is a counter control circuit, 83 is a counter load value generation circuit, 84
Is an arithmetic unit, 85 is an arithmetic unit control circuit, 86 is a switch circuit, and 87 is a switch control circuit. FIG. 9 shows a specific example of the arithmetic unit 84 in FIG. 8, which is composed of 19 exclusive OR circuits and 9 AND circuits. Next, the operation of the address generating circuit shown in FIGS. 8 and 9 will be described with reference to FIG. 7 when the address is 10 bits. As a write address (A0 to A9) at timing T in FIG.
_i-1 occurs, and a memory write operation is performed on the address. At the same time, a read address (C0 to C9) having an address difference j from the write address must be generated in order to perform a memory read operation. Therefore, the write address is A0 to A in FIG.
9 and the offset amount j (B0 to B9) generated by the arithmetic unit control circuit 85 in FIG.
X _{i + j} as the read address (C0 to C9) offset by adding or subtracting
Occurs. The write address and read address generated as described above are input to the switch circuit 86 in FIG. 8, and the memory address is output according to the write / read operation of the memory as shown in FIG. However, according to the above-described method, as the number of bits of the address increases, the area of the arithmetic unit 84 increases, and as a result, the chip area increases. The above items will be described in detail with reference to FIG. FIG. 9 shows an example of the arithmetic unit 84, in which the address is 1
This is an adder in the case of being composed of 0 bits. If the arithmetic unit 84 in FIG. 8 has this circuit configuration, there is no problem.
However, when the number of bits of the address becomes 10 bits or more, there is a problem that the chip area increases with the number of bits. An object of the present invention is to provide an address generation circuit which does not increase the chip area even when the number of bits increases. An address generating circuit according to the present invention is an address generating circuit for generating an address for accessing a memory cell array in a semiconductor memory device which performs writing and reading in a predetermined order, A count pulse generating circuit for generating a count pulse corresponding to the offset value between the write address and the read address ;
Between the read and write operations.
Up-down card that counts up or counts down
And the output of the up / down counter is semiconductor
As write address and read address of storage device
It is characterized by using. According to the address generation circuit of the present invention, a count pulse generation circuit for generating a count pulse corresponding to an offset value between a write address and a read address is provided.
Between the read operation and the write operation by the count pulse.
To count up or count down
Up / down counter output with down counter
The write address and read address of the semiconductor memory device.
Since used as scan, the smaller the circuit scale of the address generating circuit will lead to reduction of the resulting chip area. An embodiment of the address generating circuit according to the present invention will be described with reference to FIGS. In FIG. 1, reference numeral 11 denotes a 10-bit up / down counter, reference numeral 12 denotes a counter control circuit, and reference numeral 13 denotes a counter load value generation circuit. A timing chart of the circuit operation is shown in FIG. In FIG. 3, reference numeral 31 denotes a 3-bit down counter, reference numeral 32 denotes a counter control circuit, reference numeral 33 denotes a counter load value generation circuit, and reference numeral 34 denotes a latch circuit. Timing charts of circuit operations are shown in FIGS. The operation of the address generation circuit of the semiconductor memory device thus configured will be described for the case where the offset amount Δj = 7. First, the circuit operation of FIG. 3 will be described with reference to FIGS. In FIG. 3, signals YR, CR
And signal 3a fixed to either "H" or "L"
To 3d, the counter load value generation circuit 33
At the timing shown in FIG.
To generate a load value. Note that Δj in FIG.
・ ・ ・ ・ ・ 、 7 ways are considered. Next, in the counter control circuit 32,
The control signals NL, CI, NE of the 3-bit down counter 31 and the set signal S of the latch circuit 34 are generated at the timings shown in FIG. And the signal ASC is generated by resetting the output of the latch circuit 34. The signals ASC, CLK, UCY, and MAL generated as described above ("H" when QL0 to QL9 are the maximum value) and MIL ("H" when QL0 to QL9 are the minimum value). ), The signals 1a to 1k fixed to either "H" or "L" are transmitted to the counter control circuit 1 shown in FIG.
2 and the control signal CI, NE, U of the 10-bit up / down counter 11
ND is generated at the timing shown in FIG. As a result, 1
UCY =
At the time of "H", an address N + 7 having an offset amount with respect to the address N is generated as shown in FIG. When UCY = “L”, an address N-7 having an offset amount with respect to the address N is generated as shown in FIG. The UCY timing is shown in FIG. As described above, the address generating circuit according to the present invention provides a count pulse for generating a count pulse corresponding to an offset value between a write address and a read address.
The read operation and the latch are performed by the generation circuit and the count pulse.
Count-up or count-down
And an up-down counter that performs
The output of the counter is written to the write address of the semiconductor memory device.
Since they are used as read addresses and read addresses, the ratio of the address generation circuit in the semiconductor memory device is smaller than in the conventional case, and the chip area is reduced.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of one embodiment of the present invention. FIG. 2 is a timing chart for explaining the operation of one embodiment of the present invention. FIG. 3 is a block diagram of a count pulse generation circuit in one embodiment of the present invention. FIG. 4 is a timing chart for explaining the operation of one embodiment of the present invention. FIG. 5 is a timing chart for explaining the operation of the count pulse generation circuit in one embodiment of the present invention. FIG. 6 is an explanatory diagram of a memory. FIG. 7 is a timing chart for explaining the operation of a conventional address circuit. FIG. 8 is a block diagram of a conventional address circuit. FIG. 9 is a circuit diagram of a computing unit in a conventional address circuit. [Description of Signs] 11 10-bit up / down counter 12 counter control circuit 13 counter load value generation circuit 31 3-bit down counter 32 counter control circuit 33 counter load value generation circuit 34 latch circuit 81 counter 82 counter control circuit 83 counter load value generation Circuit 84 Operation unit 85 Operation unit control circuit 86 Switch circuit 87 Switch control circuit

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-2-93825 (JP, A) JP-A-56-124935 (JP, A) JP-A-59-33687 (JP, A) JP-A-59-33687 100616 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 5/06 352 G06F 13/38 310 G11C 8/04

Claims (1)

Claims: 1. An address generating circuit for generating an address for accessing a memory cell array of a semiconductor memory device which performs writing and reading in a predetermined order, comprising: a write address and a read address. A count pulse generating circuit for generating a count pulse corresponding to the offset value ;
The read operation and the write operation are performed by the count pulse.
In between, count up or count down
And an up-down counter.
Of the semiconductor memory device and the output of the semiconductor memory device.
An address generation circuit for use as a code address.