JP3205074B2 - Address generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an address generating circuit for generating an address having a fixed offset with respect to a specific address in a semiconductor memory device.

[0002]

2. Description of the Related Art A semiconductor memory device is a FIFO (First).
In the case of an “In First Out” memory, when the delay amount between the write data and the read data is determined, the memory cells are usually arranged in a matrix as shown in FIG. Focusing on the row address to access the cell array, the write address and the read address are determined by the offset amount j.
While performing the memory operation.

A conventional address generating circuit for realizing the above-described memory operation will be described with reference to the drawings.

FIG. 8 shows the above-mentioned conventional address generating circuit 90. In FIG.
N-bit counter 91 for generating write address WA
, A counter control circuit 92, a counter load value generation circuit 93, an operation unit 94, an operation unit control circuit 95 for generating an offset amount j, and a switch for outputting a memory address MA including a write address WA and a read address RA. A circuit 96 and a switch control circuit 97 are provided.

[0005] Figure 9 is the shows the operation timing of the conventional address generating circuit 90, as shown in FIG. 9, the n-bit counter 91 at the timing of A address X _i is generated as a write address WA, the address write operation of the memory is performed on X _i. In order to perform the read operation together with the write operation of the memory, it is necessary to generate a read address RA having an offset amount j with respect to the write address WA.

[0006] Therefore, the offset amount j generated by the arithmetic unit control circuit 95 together with the address X _i as the write address WA is input to the arithmetic unit 94 is input to the arithmetic unit 94. By offset j is added to the address X _i, the address X _{i + j} having offset j with respect to the address X _i is generated as a read address RA.

The write address W generated in this manner is
And address X _{i + j} as an address X _i and the read address RA as A is inputted to the switch circuit 96, a memory address MA corresponding to the write and read operations of the memory is outputted.

[0008]

FIG. 10 shows an example of a computing unit 94 of the above-mentioned conventional address generating circuit 90.
As shown in FIG. 10, the arithmetic unit 94 outputs the write address W
A (A ₀ -A _n-1 ) and the offset amount j (B ₀ -B _n-1 ) are added to generate an _n- bit read address RA (C ₀ -C _n-1 ) as a result of the addition. It is an adder, and it is necessary to add one full adder composed of two exclusive OR elements, two AND elements and one OR element each time the number of bits of the address increases by one bit There is.

As described above, in the above-described conventional address generation circuit, the area of the arithmetic unit increases with an increase in the number of bits of the address. As a result, there is a problem that the chip area increases.

The present invention has been made in view of the above, and an object of the present invention is to suppress an increase in a circuit area due to an increase in the number of bits of an address and to reduce a chip area.

[0011]

In order to achieve the above object, the invention according to claim 1 uses an offset to an address X by a counter pulse which is a pulse number corresponding to an offset amount j without using an arithmetic unit. By using an n-bit up / down counter that generates an n-bit address Y having an amount j, an increase in circuit area due to an increase in the number of address bits is suppressed.

[0012] Specifically, the first aspect of the present invention is a counter pulse generating means for generating a counter pulse which is a pulse number corresponding to an offset amount j with respect to an address X; An n-bit up / down counter capable of generating an n-bit address Y having an offset amount j corresponding to the number of pulses of the pulse; and an n-bit up / down counter upon receiving the counter pulse from the counter pulse generating means And an up / down counter control means for generating an n-bit address Y having an offset amount j corresponding to the number of the counter pulses with respect to the address X.

According to a second aspect of the present invention, a load value corresponding to an address X is generated and an offset amount j
A counter pulse having a pulse number corresponding to the counter value is generated, and an n-bit up-down counter is used to generate an n-bit address Y having an offset amount j corresponding to the pulse number of the counter pulse with respect to the address X corresponding to the load value.
Specifically, an up / down counter load value generating means for generating a load value according to the address X, and a counter load value generating means for generating a load value according to the offset amount j with respect to the address X Means,
A counter capable of receiving a load value corresponding to the offset amount j from the counter load value generating means and outputting a carry-out corresponding to the load value; and a counter capable of receiving the load value from the counter load value generating means. Counter control means for outputting a carry-out corresponding to the load value to the counter upon receipt of the counter, a latch circuit for generating a counter pulse which is a pulse number corresponding to the carry-out when receiving the carry-out from the counter, It is possible to receive a load value from the up / down counter load value generating means and generate an n-bit address Y having an offset amount j corresponding to the number of the counter pulses with respect to an address X corresponding to the load value. An n-bit up / down counter,
When the counter pulse is received from the latch circuit and the n-bit up / down counter receives the load value from the up / down counter load value generating means,
A bit up / down counter comprising up / down counter control means for generating an n-bit address Y having an offset amount j corresponding to the number of pulses of the counter pulse with respect to an address X corresponding to the load value; Is what you do.

[0014]

According to the configuration of the first aspect, the counter pulse generating means generates a counter pulse which is a pulse number corresponding to the offset amount j. Thus, the n-bit up / down counter generates an address Y having an offset amount j corresponding to the number of the counter pulses with respect to the address X. Therefore, an n-bit up / down counter can be used instead of the arithmetic unit of the conventional address generation circuit. For this reason, the circuit scale of the address generation circuit can be reduced, and an increase in circuit area due to an increase in the number of address bits can be suppressed.

According to the second aspect of the present invention, the up / down counter load value generating means generates a load value corresponding to the address X and generates a counter pulse which is the number of pulses corresponding to the offset amount j by the counter. The up / down counter can generate an n-bit address Y having an offset amount j corresponding to the number of the counter pulses with respect to the address X corresponding to the load value.

Therefore, an n-bit up / down counter can be used in place of the arithmetic unit of the conventional address generation circuit, so that the circuit scale of the address generation circuit can be reduced, and the circuit accompanying the increase in the number of address bits can be used. An increase in area can be suppressed.

[0017]

An embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1, 2 and 3 show an address generation circuit 1 according to the above embodiment. In FIG. 1, the address generation circuit 1 includes a counter pulse generation circuit 10, a 10-bit up / down counter 20, and an up / down counter 20. A down counter control circuit 30 and an up / down counter load value generation circuit 40 are provided. The counter pulse generation circuit 10
It has a 3-bit down counter 11, a counter control circuit 12, a counter load value generation circuit 13, and a latch circuit 14.

The relationship between the memory operation of the semiconductor storage device and the circuit operation of the address generation circuit 1 when the address generation circuit 1 configured as described above is applied to a semiconductor storage device of an image processing system will be described with reference to the drawings. Will be explained. Here, in the image processing system, one field of an image is composed of 568 lines, and a memory operation requires 60 memory cycles (1 memory cycle = 16 clocks) for each line. .

FIG. 4 shows the relationship between the memory operation for one line in the image processing system and the signal of the address generation circuit 1. In FIG. 4, YR and CR are counter load value generation circuits of the counter pulse generation circuit 10. Reference numeral 13 denotes a control signal input to the counter 13, and MCY denotes a control signal input to the counter control circuit 12 of the counter pulse generation circuit 10. UCY indicates a control signal input to the UND terminal of the 10-bit up / down counter 20 through the up / down counter control circuit 30 and to the up / down counter load value generation circuit 40.

CLD is a counter pulse generating circuit 1
0 indicates a load value output from the counter load value generation circuit 13, where j is an offset amount, and 0, 1,.
2, ..., 6 or 7. In the memory operation, R indicates a read operation, W indicates a write operation, and MA indicates 10
2 shows a memory address output from the bit up / down counter 20.

The read operation R in the memory cycle mc57 is performed for the address X _ij is a memory address MA of the time. Similarly, memory operations in memory cycles mc41, mc33, mc26, and mc4 are performed on addresses X _{i + 1} , X _ij , X _i , and X _i-3 . Here, the address X _ij is an address having an offset amount j with respect to the address X _i .

Hereinafter, the memory cycles mc58 and mc5
7, address generation circuit 1 in mc56 and mc55
Will be described with reference to the drawings. Here, the case where the offset amount j = 7 will be described.

First, in the memory cycle mc58, the counter load value generation circuit 13 of the counter pulse generation circuit 10 receives the signals a _{0 to} a ₃ set to the high level or the low level by the control signals YR and CR, An offset amount j = 7 is generated as a load value CLD and output to the 3-bit down counter 11. Further, the counter control circuit 12 controls the clock CL as shown in FIG.
And K and the signal P ₀ to P ₃ inputs the control signal MCY, the control signal CC _0, CC _1, CC ₂ 3-bit down counter 11
And the control signal CC ₃ is output to the S terminal of the latch circuit 14.

The 3-bit down counter 11 is controlled by control signals CC _{0 to} CC ₃ from a counter control circuit 12, and receives a load value CL from a counter load value generation circuit 13.
Carry out C according to offset amount j = 7 which is D
O is output to the R terminal of the latch circuit 14. Then, the latch circuit 14 controls the control signal C from the counter control circuit 12.
The counter pulse ASC is generated by being set by C _{3 and} reset by the carry-out CO from the 3-bit down counter 11. The number of pulses of the counter pulse ASC is determined according to the carry-out CO from the 3-bit down counter 11, and is equal to the offset amount j = 7 (see FIG. 5).

Thus, the counter pulse ASC is generated in the counter pulse generation circuit 10.

Similarly, in the memory cycle mc58, the up / down counter load value generation circuit 40
Signal b ₀ set to high level or low level
To b ₆ , b ₈ and the control signal UCY, and inputs the address X _i
Is generated as a load value ULD and output to the 10-bit up / down counter 20. Further, the up / down counter control circuit 30 outputs the signals b _{7 to} b ₁₀ set to the high level or the low level and the memory address MA
A signal MAL which becomes a High level when is the maximum value;
A signal MIL which goes high when the memory address MA is at the minimum value, and a clock CLK as shown in FIG.
, The control signal UCY, and the counter pulse ASC generated by the counter pulse generation circuit 10,
₀ , U ₁ , U ₂ , and UCY are output to the CI, NL, NE, and UND terminals of the 10-bit up / down counter 20, respectively. At this time, as shown in FIG. 6, since the control signal UCY is at the low level, the memory addresses MA output from the 10-bit up / down counter 20 are the addresses X _i , X _i-1 , X _i-2 ,. And it gets smaller by one.

Then, in the memory cycle mc57, the 10-bit up / down counter 20 sets the address X _i −7 having the offset amount j = 7 with respect to the address X _i.
Cause.

Next, in the memory cycle mc56, the counter pulse generating circuit 10 operates the counter pulse A having the same number of pulses as the offset amount j = 7 by the same operation as that in the memory cycle mc58.
Generate SC.

At this time, as shown in FIG.
Since CY is at High level for one memory cycle, the up / down counter load value generation circuit 40 generates the address X _i-7 as the load value ULD, and the memory address MA output from the 10-bit up / down counter 20 is , Addresses X _i-7 , X _i-6 , X _i-5 ,...

Then, in the memory cycle mc55, the 10-bit up / down counter 20 sets the address X _i having the offset amount j = 7 with respect to the address X _i -7.
Occurs.

As described above, in the address generation circuit according to the above embodiment, the counter pulse generation circuit 10 generates a counter pulse having the number of pulses corresponding to the offset amount j. As a result, the 10-bit up / down counter has an offset amount j for a specific address.
A bit address can be generated.

Therefore, since the up-down counter can be used instead of the arithmetic unit of the conventional address generation circuit, the circuit scale of the address generation circuit can be reduced, and the circuit area with the increase in the number of address bits can be reduced. The increase can be suppressed.

[0034]

As described above, according to the address generating circuit according to the first aspect of the present invention, an n-bit up / down counter is provided by a counter pulse which is the number of pulses corresponding to the offset amount j without using an arithmetic unit. Can generate an n-bit address Y having an offset amount j with respect to the address X, thereby suppressing an increase in the circuit area due to an increase in the number of bits of the address. Is possible.

According to the address generation circuit of the second aspect of the present invention, a load value corresponding to the address X is generated and a counter generates a counter pulse corresponding to the offset amount j by the counter. The counter can generate an n-bit address Y having an offset amount j corresponding to the number of the counter pulses with respect to the address X corresponding to the load value.

Therefore, it is possible to suppress an increase in the circuit area due to an increase in the number of bits of the address, and it is possible to reduce the chip area.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an address generation circuit according to one embodiment of the present invention.

FIG. 2 is a wiring diagram showing a counter pulse generation circuit of the address generation circuit.

FIG. 3 is a wiring diagram showing a 10-bit up / down counter, an up / down counter control circuit, and an up / down counter load value generation circuit of the address generation circuit.

FIG. 4 is a time chart showing a relationship between an operation of the address generation circuit and a memory operation.

FIG. 5 is a time chart showing an operation of a counter pulse generation circuit of the address generation circuit.

FIG. 6 is a time chart showing an operation of a 10-bit up / down counter of the address generation circuit.

FIG. 7 is a time chart showing an operation of a 10-bit up / down counter of the address generation circuit.

FIG. 8 is a block diagram showing a conventional address generation circuit.

FIG. 9 is a time chart showing an operation of the conventional address generation circuit.

FIG. 10 is a logic circuit diagram showing an arithmetic unit of the conventional address generation circuit.

FIG. 11 is a diagram showing an arrangement of memory cells of a semiconductor memory device to which the above-mentioned conventional address generation circuit is applied.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Address generation circuit 10 Count pulse generation circuit (count pulse generation means) 11 3 bit down counter 12 Counter control circuit (counter control means) 13 Counter load value generation circuit (counter load value generation means) 14 Latch circuit 20 10 bit up / down Counter 30 Up / down counter control circuit (up / down counter control means) 40 Up / down counter load value generation circuit (up / down counter load value generation means)

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-243083 (JP, A) JP-A-3-182946 (JP, A) JP-A-62-67633 (JP, A) JP-A-56- 68994 (JP, A) Japanese Utility Model 63-63,798 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 7/00 318 G06F 5/06 G06F 12/02

Claims (2)

(57) [Claims] 1. A counter pulse generating means for generating a counter pulse having a pulse number corresponding to an offset amount j with respect to an address X, and an n having an offset amount j corresponding to the pulse number of the counter pulse with respect to the address X An n-bit up / down counter capable of generating a bit address Y; and a pulse number of the counter pulse for the address X when the counter pulse is received from the counter pulse generating means. And an up-down counter control means for generating an n-bit address Y having an offset amount j corresponding to the address generation circuit. 2. An up / down counter load value generating means for generating a load value corresponding to an address X, a counter load value generating means for generating a load value according to an offset amount j with respect to the address X, and the counter load value. A counter capable of receiving a load value corresponding to the offset amount j from the generation means and outputting a carry-out corresponding to the load value; and a counter capable of receiving the load value from the counter load value generation means. Counter control means for causing a counter to output a carry-out according to the load value; a latch circuit for generating a counter pulse corresponding to the carry-out upon receiving the carry-out from the counter; and an up-down counter Receives a load value from the load value generating means and responds to the load value. It is possible to generate an n-bit address Y having an offset amount j corresponding to the number of the counter pulses with respect to a corresponding address X.
When the counter pulse is received from the bit up / down counter and the latch circuit and the n bit up / down counter receives a load value from the up / down counter load value generating means, the n bit up / down counter corresponds to the load value. An address generation circuit, comprising: an up / down counter control means for generating an n-bit address Y having an offset amount j corresponding to the number of the counter pulses with respect to the address X.