SU1571679A1 - Buffer memory - Google Patents

Abstract

The invention relates to storage devices and can be used to build digital image input subsystems, (purpose of the invention) QI preprocessing devices, devices for converting coordinates of array elements with matrix organization. The purpose of the invention is to improve the reliability and speed of the buffer storage device by reducing the capacity of additional memory blocks and the number of accesses to them when redirecting image elements. The device contains blocks 1, 2, 3 of memory, counters 4, 5 addresses, multiplexers 6, 7, adders 8, 9 control block 10, registers 11, 12, counters 13, 14, multiplexers 15, 16. Achieving the goal is achieved using piecewise -linear approximation of geometric image conversion curves and recurrent formulas for calculating the transformed address when the components of the current transformed address are found by adding the components of the previous transformed address with the corresponding corrections that are constant for each l the inverse region of the approximating polygonal transformation. This allows reducing the number of corrections to the number of linear sections of broken transformations, and accessing additional memory blocks for corrections is made only during transitions from one linear section to another. 3 il.

Description

W

6

SP V4

cЈ

4 o

organization. The purpose of the invention is to increase the reliability and speed of the buffer storage device by reducing the capacity of additional memory blocks and the number of accesses to them when the image elements are redirected. The device contains blocks 1–3 of memory, counters 4 and 5 addresses, multiplexers 6 and 7, adders 8 and 9, control block 10, registers 11 and 12, counters 13 and 14, multiplexers 15 and 16. Achieving the goal is achieved using piecewise linear approximation of geometric image conversion curves and

The invention relates to computing and can be applied to construct digital image input devices in processing systems.

The purpose of the invention is to improve the reliability and speed of BZU.

FIG. 1 shows a block diagram of the device; in fig. 2 is a functional diagram of a mode control unit; in fig. 3 - the scheme of the additional memory block is functional.

The buffer memory contains the main memory block 1 (BOP), the first 2 (BDP1) and the second 3 (BDP2) additional memory blocks, the write address counter 4 (SchAzap), the read address counter 5 (ScAcht), the column address multiplexer 6 ( MXAx11), multiplexer 7 row address {MXAU), adder 8 row address (Ay) adder 9 column address (Ax), mode control block 10, register 11 transformed row address (PrAup), transformed column address register 12 (PrAxp), counter 13 pixels with the same corrections for the row coordinate (CpPue), tchik 14 image elements with the same corrections on the column coordinate (СЧПх, multiplexer 15 convertible row addresses (МХАуПр), multiplexer 16 convertible column addresses (), input 17 for the record (for the recording REC), input 18 for the reading (for the letter TH) ), input 19 of the transform recording mode (REC with Pr), input 20 of the read mode with conversion (THU with Pr), input 21 of the mode record (Record), input 22 of the load mode (LOAD), input 23 of the download order (For the installation ZARR), the initial installation input (LC) input 24, data inputs 25 (DWx), data outputs 26 (TWO), load address inputs 27 (Azagr.). 28 download data inputs (Dzagr.). Block 10

recurrent formulas for calculating the transformed address when the components of the current transformed address are found by adding the components of the previous transformed address with the corresponding corrections that are constant for each linear region of the approximating broken transformation. This allows reducing the number of corrections to the number of linear sections of broken transformations, and accessing additional memory blocks for corrections is made only when switching from one linear section to another, 3 sludge.

 contains the input 29 of the end of the cycle of the first additional memory block (CCPD1), the input 30 of the end of the cycle of the second additional memory block (CC DP2), the input 31 of the end of the cycle

the main memory block (CC OP), the output 32 of the main memory block mode (PAC OP) and the output 33 of the first additional memory block selector resolution (PB D1), the output 34 of the selection resolution of the second additional memory block (RC DUT2), output 35 enable the selection of the main memory block (RV OP), the output 36 of the mode of additional memory blocks (CMPT DP), the output 37 of the selection of multiplexers convertible

addresses (Selection MHA p), register write output 38 (Zap PrAp), outputs 39 and 40 of the modification of the pixel counters (+1 ScPu, +1 SchPh), outputs 41 and 42 of the transfers of the pixel counters of the picture elements (Transfer

SchPu), and (ShchPh transfer).

Block 10 contains a write conversion trigger 43 (TRPS), read conversion resolution trigger 44 (TRPC), block operation trigger 45

2 and 3 additional memory (TOPDP), counter transfer fixation trigger 46 (TP1), transfer transfer fixation trigger 47 (TP2), operation trigger 48 of the main memory block 1 (TOPOP), trigger 49 for selecting the first additional block 2 memory (ТРВ ДП1), trigger 50 for selecting the second additional block 3 of memory (ТРВ ДП2), trigger 51 for selecting the main block 1 of memory

(TPB OP), from the first to the fourth elements AND-OR 52-55, from the first to the elements And 56-58.

Blocks 2 and 3 contain a drive 59, a register 60 and an address multiplexer 61, an input 62 and an output data register 63, a synchronization node 64 including a shift register 65, a pulse generator 66, an AND-OR element 67, first to third elements Both 68-70 and first through fourth elements are NOT 71-74.

This goal is achieved by reducing the capacity of additional memory blocks by using a piecewise linear approximation of the image conversion curves and recurrent formulas to calculate the transformed address. When calculating the current address using a recurrent formula, it is defined as the sum of the previous transformed address and the correction. Piecewise linear approximation of the conversion curves allows, for a given accuracy of approximation, to select linear sections that are characterized by constant corrections to the transformed coordinates (addresses) of the previous pixels. Provided that the previous transformed address and the corrections are preserved, there is no need to refer to additional memory blocks for subsequent corrections. In this case, access to additional memory blocks for new corrections is made upon transitions from one linear section of a broken transformation to another.

The use of two registers of the previous transformed address in each of the coordinates makes it possible to avoid access to additional memory blocks as long as the image element is on the linear portion of the approximation polyline. Two counters of elements allow determining the end points of the linear sections and the need to apply for the next amendment. The multiplexers of the addresses being transformed select the inputs of the adders either of the original address address from the coordinate multiplexers or the previous converted address depending on the availability of the conversion mode when accessing the RAM. The functions of these elements are necessary to achieve the goal.

The device works as follows.

Before the work session, the shift register of blocks 2 and 3 is set to zero, and then additional blocks 2 and 3 of the memory are loaded with corrections y and x (along the coordinates of columns and rows). For this purpose, a signal is supplied to the input 22 of the FGR that sets the trigger 45 to the state corresponding to the entry in blocks 2 and 3.

At the same time, at the output 36, the PRCCDD is issued on a Vits signal corresponding to the operation of the zlisy. The cell address of the additional blocks 2 and 3 of the memory is fed to the inputs 27 Azagr, and the data to the inputs 28 Dzagr together with the signal at the input 23 of the ZAGR Application. The coincidence of the signals from the output of the trigger 45 and the REQUEST Zagr at the inputs of the AND-OR elements 52 and 54 ensures that the flip-flops 49 of the TP8 DP1 and 50 10 of the TPB DP2 are set to the enable state for selecting the first 2 and second 3 additional memory blocks. As a result, the outputs 33 RV DP 1 and 34 RV DP2 appear signals, providing a choice of blocks 2 and 3. These signals through the element AND-OR 67 arrive at the synchronization input of the register 65, because after setting the register to zero 65 at the output of the element NOT 71 there is a single signal. Shift register 65 is in write mode, since in the absence of a signal ne output 33 (34) and the first output of register 65, a single signal is present at the output of the element 70. As a result, one is written to the register 65 in the first bit,

5, whereupon the register 65 is switched from its first output to the shift mode with a single signal. At the same time, the same signal records data from inputs 28 to register 62 and addresses from inputs 27 to register 60, since

In the absence of a signal at output 37 in the load mode, the inputs 27 of the load address are selected. The appearance of a single signal at the first output of register 65 leads to the disappearance of a single signal at

5 output element And 70 and the appearance of a single signal at the output of the element HE 74, which, in addition to establishing the shift mode of the register 65, permits the generation of pulses from the generator 66 through the element

0 AND-OR 67 to the synchronization input of register 65. These pulses shift the unit from the first bit to the oldest. The loss of a single signal at the first output of the register 65 does not lead to the establishment of the recording mode, since this requires the absence of a signal at the output 33 (34). At the end of the recording, the word signals at the input 29 of the CC DP1 and the input 30 of the CC DP2 from the outputs of blocks 2 and 3 reset the triggers 49 and 50.

0 The specified sequence of signals is sent and formed until blocks 2 and 3 have finished loading. After loading, the device is put into a working state, for which the mode of operation and the initial state of the mode control block 10 are set. The settable mode of operation depends on the combination of signals at inputs 19, 20, and 21, and the signal at input 24 of NU triggers 46 and 47 are set to correspond to the presence of transfers of counters 13 and I.

Record mode with conversion and reading without conversion.

To set this mode, single signals are fed to inputs 19 and 21, and zero to input 20. At This, the TRPS trigger 43 is set to one state, the TRPCH trigger 44 is set to zero, and the TDPD trigger 45 is reset by a signal at input 21 Record, thereby setting a read operation for blocks 2 and 3 of additional memory,

The first application of the REC received at input 17 sets the trigger 48 of the TOPOP to the state corresponding to the record in the main memory 1, and, having passed through the first 52 and third 54 AND-OR elements, sets the triggers 49 TRV DP1 and BOD TRV DP2 in the state of Svext1, which are the choice of blocks 2 and 3. The signal at output 32 provides the choice of 4 Azap counter by multiplexers 6 MHAHI and 7 MHAui. As a result, the output registers 63 of blocks 2 and 3 of the cells defined by the coordinates Ahi and Aui, are corrected by the codes of the corrections to the coordinates of columns and rows and the codes of the number of image elements in the linear segments of the broken transformation, which are then entered into counters 13 and 14 along There are lambs of the end of the reference cycles at the inputs 2C of CCDP1 and 30 CCDP2, which also flushes the flip-flops 49 and 50 and install (via the second IL-53 element) flip-flop 51 TRV OP. At the output of the fourth element / -IL 55, the 37 MCHAPr signal appears, allowing the multiplexers 15 and 16 to select the registers 11 Pg Aup and 12 Pg Ax. As a result, the outputs of the converted coordinates AHP1 and AUP appear at the outputs of the adders 8 and 9 generating the write address of the data at the inputs 25 to the main memory unit 1. At the end of the cycle of accessing Block 1, the signal on the CC bus of the OP is reset by the trigger 51 of the TPV OP and at the same time this signal passes through the second element 57 and generates the signal 38 Zap Pg An, which sends the registers 11 and 12 codes from the outputs of adders 8 and 9 to registers 11 and 12 respectively. As triggers 46 and 47 are reset by signals at inputs 29 and 30, the signal at output 38 passes through the first 56 and third 58 elements A to outputs 39 and 40, modifying the counters 13 and 14.

When writing the next element of the image, access to the additional blocks 2 and 3 of the memory is blocked, since the triggers 46 and 47 are reset. In this case, the ZAP application on bus 17 passes through the fifth group of inputs of the second element AND-OR

52, since the trigger 43 of the TRPZ is set to one, and the triggers 46 and 47 to –y / b, and sets the trigger 51 to the opto-resetter OP and one, thereby permitting the memory of the single memory unit 1. The addresses of the memory cell of block 1 are formed by sumatrs l 8 and 9 from the terms stored in per / fear 11 and 12 and the registers of the additional blocks 2 and 3 of memory igchalich at input 31 trigger 51

0 OPT is reset and at the same time

 Worldwide Modification Signals

13 and 14 on tires 38 m 40. At the end

linear section on one of the broken lines

 transformation corresponding trigger

5 46 or 47 fixations transfer the set to a unit, allowing the installation of one of the triggers 49 or 50 in the unit, thereby calling one of the blocks 2 or 3 when there is a signal on

0 iin 17

When reading data from block 1 in this mode, multiplexers 6 and 7 select the counter 5 reading address, multiplexers 15 and 16 are connected to the inputs

5 adders 8 and 9 instead of outputs of registers 11 and 12 outputs of multiplexers b and 7, i.e. output of counter 5 of the reading address. The signal from 18 and 18 passes through the inputs of the second group of the AND-OR 53 element, so that the rep rep44 TRPCH is set to zero and sets the trigger 51 of the TRV OP to one, the reset is performed at the end of the cycle of access to block 1 by a signal at input 31 CCE

five

Record mode without conversion and reading with conversion

To set this mode, at the input 19 of the LAP with the Pr, a zero signal is given and

0 inputs 20 and 21 - single When writing data to block 1, the signal at input 1 7 SETA immediately sets the trigger 51 to the TRV OP in the unit, since the inputs of the first group of inputs of the second element are AND-OR 53

5, single signals of the Record v from the zero output of the trigger 43 of the TRPS coincide, while access to the additional blocks 1 and 3 of the memory is blocked by a zero signal from the first output of the trigger 43 of the TRPZ. At a turn of 32 select. MKHAI shows a single signal, and at the output of 37 Zyb MHA p - zero. With such a combination of signals, multiplexers 6 and 7, 15 and 16 zyoirayug counter outputs 4 Azap. The write address code is summed with zero codes from the outputs of blocks 2 and 3, since the zero signal at output 37 blocks the output of the output registers of blocks 2 and 3, that is, the address of the records from the outputs of counter 4 is present at the address inputs of the main memory block 1

When reading, the signal from input 18 of the request for THU at the first request for data to the block

I passes through the first 52 and third 54 AND-OR elements, since the flip-flops 46 and 47 are set to one state by a signal from the input 24 of the НУ and -figur 49 TRV ДП1, and also the trigger 50 ТРВ ДП2 are set to one state, allowing reading amendments from blocks 2 and 3. At exit 37 MCAP appears a single signal due to the coincidence of single signals from the first output of the 44HRLT trigger and from the second output of the trigger 48 TOPOP. Register Content

II and 12 (zero for the first reading) is summed up with amendments from the outputs of blocks 2 and 3 with accumulators 8 and 9. The signals on the tires 29 KC DP1 and 30 KC DP2 triggers 49 and 50 are reset, and the 51 AND TR 53 trigger is set per unit, allowing access to block 1. At the same time, counters 13 and 14 record the number of pixels in the current linear sections of the broken transformation, and triggers 46 and 47 are reset. During subsequent calls to the device by the country, the readings of the corrections are blocked and the old contents of the output registers of blocks 2 and 3 are used until at least one of the signals on the buses 41 and 42. The contents of the counters 13 and 14 are modified by sig on the bus 31 KTs OP, which, passing through the second element And 57 provides for writing the converted reading address to registers 11 and 12, will generate a signal on the bus 38 Hall Pr Ap, and this signal in turn passes through the elements And 56 and 58, forming signals at outputs 39 and 40.

In the write without conversion mode set for zero signals at inputs 19 and 20 and a single at input 21, the recording is performed similarly to recording in the non-converting mode and reading with conversion, the reading is similar to reading in the writing mode with conversion and reading without conversion.

Claims (1)

Claims A buffer storage device comprising a main storage unit, informational inputs and outputs of which are respectively inputs and outputs of device data, a write address counter and a read address counter whose counting inputs are inputs according to a write requirement and a read requirement of the device and are connected respectively to the input of the recording signal and the input of the reading signal of the mode control unit, the multiplexer of the column address and the multiplexer row addresses, first and second additional memory blocks, row address adder and adder column addresses, the first information inputs of which are connected to the first information outputs of the first and second additional memory blocks, the first address inputs and information inputs of which are combined and are 10, respectively, the addresses of the load address, the data inputs of the load of the device, the second address inputs of the first and second additional memory blocks are connected to the outputs, respectively, of the multiplexer 15 addr ca column and row address multiplexer, control inputs of which are connected to the input setting mode of the main unit memory and to the output mode of the control unit, inputs specifying 0 modes of the first and second additional memory blocks are combined and connected to the corresponding output of the mode control block, the first information inputs of the multiplexer column address and 5 row address multiplexers are connected to the first outputs of the write address counter and the read address counter, the second outputs of which are connected to the second information inputs of the row address multiplexer and the column address multiplexer, the output of the cycle end of the main memory block, the enable input of the main memory block selection podktyucheny with the corresponding input and output of the mode control block, the input of the initial installation, the input for loading, the input of the loading mode, the input of the recording mode, the input of the reading mode with p eobrazovaniem recording mode and input to the transformation 0 of the mode control unit are device inputs of the same name, the outputs of the adder of the row address of the row of the adder of the column address are connected to the first and second address inputs of the main memory block, 5 characterized in that, in order to increase reliability and speed, it contains the first and second registers, the first and second counters, the first and second multiplexers of the transformed addresses, 0 control inputs of which are connected to the data output inputs of the first and second additional memory blocks and to the corresponding output of the mode control block, the first information inputs The 5 first and second multiplexers of the transformed addresses are connected to the outputs of the corresponding first and second registers, the write entries of which are combined and connected to the corresponding flea output of the mode control, the information inputs of the first and second registers are connected to the outputs of the row address adder and the column adder respectively, the second inputs of which are connected to the outputs of the first and second multiplexers, respectively, of the transformed addresses, the second information inputs of which are connected to the outputs of the co correspondingly, the multiplexer of the row address and the multiplexer of the column address, information The input inputs of the first and second counters are connected to the second outputs of the first and second additional memory blocks, the output of the loop ends and the selection enable inputs of which are the corresponding inputs and outputs of the mode control unit, the counting inputs and transfer outputs of the first and second counters are the corresponding outputs and the inputs of the mode control unit. 1. 33 (34) Fig.z KB (9 KW) I