JP3392992B2 - Semiconductor package - Google Patents
Semiconductor packageInfo
- Publication number
- JP3392992B2 JP3392992B2 JP20552395A JP20552395A JP3392992B2 JP 3392992 B2 JP3392992 B2 JP 3392992B2 JP 20552395 A JP20552395 A JP 20552395A JP 20552395 A JP20552395 A JP 20552395A JP 3392992 B2 JP3392992 B2 JP 3392992B2
- Authority
- JP
- Japan
- Prior art keywords
- adhesive
- adhesive layer
- semiconductor package
- wiring pattern
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体パッケ−ジ
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package.
【０００２】[0002]
【従来の技術】半導体の集積度が向上するに従い、入出
力端子数が増加している。従って、多くの入出力端子数
を有する半導体パッケージが必要になった。一般に、入
出力端子はパッケージの周辺に一列配置するタイプと、
周辺だけでなく内部まで多列に配置するタイプがある。
前者は、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇ
ｅ）が代表的である。これを多端子化する場合は、端子
ピッチを縮小することが必要であるが、０．５ｍｍピッ
チ以下の領域では、配線板との接続に高度な技術が必要
になる。後者のアレイタイプは比較的大きなピッチで端
子配列が可能なため、多ピン化に適している。従来、ア
レイタイプは接続ピンを有するＰＧＡ （Ｐｉｎ Ｇｒ
ｉｄ Ａｒｒａｙ）が一般的であるが、配線板との接続
は挿入型となり、表面実装には適していない。このた
め、表面実装可能なＢＧＡ （ＢａｌｌＧｒｉｄ Ａｒ
ｒａｙ）と称するパッケージが開発されている。また、
パッケージの更なる小型・薄型化に対応するものとし
て、半導体チップとほぼ同等の外形を有する、いわゆる
チップサイズパッケージ（ＣＳＰ； Ｃｈｉｐ Ｓｉｚ
ｅＰａｃｋａｇｅ）も提案されている。こうした各種パ
ッケージを使用するベース基材で大別すると、（１）．
セラミックタイプ、（２）．プリント配線板タイプ及び
（３）．フィルムタイプなどに分類される。2. Description of the Related Art The number of input / output terminals has increased as the degree of integration of semiconductors has improved. Therefore, a semiconductor package having a large number of input / output terminals has been required. Generally, I / O terminals are arranged in a row around the package,
There is a type that arranges not only the periphery but also the interior in multiple rows.
The former is QFP (Quad Flat Packag)
e) is typical. When the number of terminals is increased, it is necessary to reduce the terminal pitch, but in the area of 0.5 mm pitch or less, a high level technique is required for connection with the wiring board. The latter array type is suitable for increasing the number of pins because the terminals can be arranged at a relatively large pitch. Conventionally, the array type has a PGA (Pin Gr) having a connection pin.
id Array) is generally used, but the connection with the wiring board is an insertion type and is not suitable for surface mounting. Therefore, surface mountable BGA (Ball Grid Ar)
A package called ray) has been developed. Also,
A so-called chip size package (CSP; Chip Siz) having an outer shape almost equal to that of a semiconductor chip is provided to support further miniaturization and thinning of the package.
ePackage) has also been proposed. Broadly classified by the base material that uses these various packages, (1).
Ceramic type, (2). Printed wiring board type and (3). It is classified into film type.
【０００３】このうち、セラミックタイプについては、
従来のＰＧＡに比べるとマザーボードとパッケージ間の
距離が短くなるために、マザーボードとパッケージ間の
熱応力差に起因するパッケージ反りが深刻な問題であ
る。また、プリント配線板タイプについても、基板の耐
熱性などに加えて基板厚さが厚いなどの問題があり、ポ
リイミドフィルムなどの薄くて耐熱性に優れたフィルム
基材をベース基材として適用したパッケージが望まれて
いる。Of these, for the ceramic type,
Since the distance between the motherboard and the package is shorter than that of the conventional PGA, the warpage of the package due to the difference in thermal stress between the motherboard and the package is a serious problem. In addition, the printed wiring board type also has the problem that the board thickness is thick in addition to the heat resistance of the board, and a package that uses a thin and excellent heat resistant film base material such as a polyimide film as the base material. Is desired.
【０００４】[0004]
【発明が解決しようとする課題】フィルム基材をパッケ
ージ用ベース基材として適用する場合、実装工程（チッ
プ接続、封止、はんだリフロー等）に耐える耐熱性を有
することと同時に、チップ実装前及びパッケージ化後で
の反りを極力小さくすることが重要な課題である。本発
明はパッケージの小型・薄型化に対応可能で、かつ、耐
熱性に優れたＢＧＡやＣＳＰなどの半導体パッケージを
提供するものである。When a film base material is used as a base material for a package, it has heat resistance to withstand a mounting process (chip connection, sealing, solder reflow, etc.) and at the same time before mounting the chip. An important issue is to minimize warpage after packaging. The present invention provides a semiconductor package such as BGA or CSP, which is adaptable to miniaturization and thinning of a package and has excellent heat resistance.
【０００５】[0005]
【課題を解決するための手段】本願の発明は、所定厚さ
の第１及び第２の接着材層を有する両面接着材付き絶縁
フィルムの第１の接着材面に形成された配線パターン
と、第２の接着材層側から配線パターンに達する外部接
続用非貫通孔とを有する基板と、その基板に搭載され、
基板の配線パターンと電気的に接続された半導体チップ
と、半導体チップを封止する封止材と、基板の外部接続
用非貫通孔に設けられた外部接続端子とにより構成され
る半導体パッケージである。The invention of the present application is a wiring pattern formed on a first adhesive surface of an insulating film with double-sided adhesive having first and second adhesive layers having a predetermined thickness, A substrate having a non-through hole for external connection reaching the wiring pattern from the second adhesive layer side, and mounted on the substrate,
A semiconductor chip electrically connected to the wiring pattern of the substrate, a sealing material for sealing the semiconductor chip , and an external connection terminal provided in a non-through hole for external connection of the substrate. It is a semiconductor package.
【０００６】[0006]
【発明の実施の形態】本願の発明の特徴は、絶縁フィル
ムの片面に形成する金属配線パターンの残存面積率や適
用する封止材の熱膨張係数などに応じて、第１及び第２
の接着材層の厚み比率及び接着材表面粗さ比率等を適宜
設定することにより、基板レベル及びパッケージレベル
での反り量を調整することができる点にある。この場
合、第１及び第２の接着材層厚さ（Ｔ１及びＴ２）は１
５μｍ以下で、かつ、厚み比率（Ｔ１／Ｔ２）は０．３
０〜１５．０の範囲にあることが好ましい。BEST MODE FOR CARRYING OUT THE INVENTION The features of the invention of the present application are that the first and second characteristics are determined in accordance with the remaining area ratio of a metal wiring pattern formed on one surface of an insulating film and the thermal expansion coefficient of a sealing material to be applied.
By appropriately setting the thickness ratio of the adhesive layer, the surface roughness ratio of the adhesive, and the like, it is possible to adjust the warpage amount at the substrate level and the package level. In this case, the first and second adhesive material layer thicknesses (T1 and T2) are 1
5 μm or less and the thickness ratio (T1 / T2) is 0.3
It is preferably in the range of 0 to 15.0.
【０００７】また、更に好ましくは、第１及び第２の接
着材層表面の最大粗さ（Ｒｔ１及びＲｔ２）が１０μｍ
以下で、かつ、粗さ比率（Ｒｔ１／Ｒｔ２）が０．２５
〜２０．０の範囲にあれば良い。接着材層の厚さは、例
えば、接着材ワニスを塗工する際のギャップや塗工速度
などを調整することにより制御可能である。また、第１
及び第２の接着材層の表面粗さは、それぞれ、接着材と
接する銅箔面や離型基材面の粗度によって調整できる。Further preferably, the maximum roughness (Rt1 and Rt2) of the surfaces of the first and second adhesive layers is 10 μm.
Below, and the roughness ratio (Rt1 / Rt2) is 0.25
It may be in the range of up to 20.0. The thickness of the adhesive layer can be controlled, for example, by adjusting the gap or the coating speed when the adhesive varnish is applied. Also, the first
The surface roughness of the second adhesive material layer can be adjusted by the roughness of the copper foil surface or the release base material surface that is in contact with the adhesive material.
【０００８】非貫通孔の形成方法は特に限定するもので
はなく、（１）．公知のドリルやパンチ加工などにより
予め接着材付き絶縁フィルムに貫通孔を設けた後、銅箔
を片面に加熱・加圧することにより貫通孔の片側を塞ぐ
方法、（２）．接着材付きフィルムの片面に銅箔を加熱
・加圧した後、例えば、炭酸ガスレーザ等で銅箔に達す
る非貫通孔を直接形成する方法、（３）．接着材付きフ
ィルムの両面に銅箔を加熱・加圧した後、一方の側の銅
箔をエッチング除去し、（２）．項と同様に直接非貫通
孔を形成する方法などが適用可能である。なお、（２）
及び（３）項においては、非貫通孔は配線パターンを形
成する側の銅箔を配線加工する前に形成しても良いし、
配線パターン形成後に形成しても良い。The method of forming the non-through holes is not particularly limited, and (1). A method in which a through hole is provided in advance in the insulating film with an adhesive by a known drill or punching process, and then one side of the through hole is closed by heating and pressurizing a copper foil on one side, (2). A method of directly forming non-through holes reaching the copper foil with a carbon dioxide gas laser or the like after heating and pressing the copper foil on one surface of the film with an adhesive, (3). After heating and pressurizing the copper foil on both sides of the adhesive film, the copper foil on one side is removed by etching (2). The method of directly forming the non-through holes and the like can be applied as in the above item. Note that (2)
In the item (3), the non-through holes may be formed before wiring the copper foil on the side where the wiring pattern is formed,
It may be formed after the wiring pattern is formed.
【０００９】配線パターンの形成方法についても特に限
定されるものではなく、通常の銅箔用エッチング液を適
用したサブトラクト法や金属箔上に配線パターンを予め
電気めっき法で形成しておき、配線パターンを接着材層
中に埋込んで転写した後、金属箔を選択的に除去する方
法などが適用可能である。The method for forming the wiring pattern is also not particularly limited, and the wiring pattern is formed in advance by a subtractive method using an ordinary copper foil etching solution or a metal foil by electroplating. It is possible to apply a method in which the metal foil is selectively removed after being embedded in the adhesive layer and transferred.
【００１０】一方、本願の発明に於ては、チップ電極と
配線との導通化方法として金ワイヤボンディングやフェ
ースダウンボンディングなどが適用可能である。前者の
場合は、配線パターン下部に存在する接着材層の耐熱性
及び硬さが重要な要因であり、ガラス転移点１８０℃以
上で、かつ、ワイヤボンディング温度に於ける弾性率が
１，０００ＭＰａ以上であることが好ましい。また、ボ
ンディング時の絶縁基材温度を熱硬化性接着材のガラス
転移点より低い温度で行なうことにより、よりいっそう
安定的なワイヤボンディングが可能になる。後者の場合
は、予め配線上に半導体チップ電極と接続する金属突起
部を形成し、半導体チップ電極を金属突起が設けられて
いる面に面して搭載し、半導体チップ電極と金属突起と
を接続する。この場合、予め配線領域の所望する部分を
熱可塑性ポリイミド接着材等で覆い、後工程で金属突起
部を形成する箇所に配線に達する非貫通凹部を設け、め
っき等で金属突起部を形成した後、半導体チップ電極と
金属突起部とを加熱・加圧により接続させると同時にチ
ップ電極面を封止しても良い。封止に適用する樹脂とし
ては、例えば、直径１０〜２０μｍ程度のシリカを５〜
８０ｗｔ％の範囲で含有したエポキシ樹脂等が適用可能
である。On the other hand, in the invention of the present application, gold wire bonding, face-down bonding, or the like can be applied as a method for making the chip electrode and the wiring conductive. In the former case, the heat resistance and hardness of the adhesive layer present under the wiring pattern are important factors, and the glass transition point is 180 ° C or higher and the elastic modulus at the wire bonding temperature is 1,000 MPa or higher. Is preferred. Further, by performing the temperature of the insulating base material at the time of bonding at a temperature lower than the glass transition point of the thermosetting adhesive, more stable wire bonding becomes possible. In the latter case, a metal protrusion is formed in advance on the wiring to connect to the semiconductor chip electrode, and the semiconductor chip electrode is mounted facing the surface on which the metal protrusion is provided to connect the semiconductor chip electrode and the metal protrusion. To do. In this case, after covering a desired portion of the wiring region with a thermoplastic polyimide adhesive or the like in advance, providing a non-penetrating recess reaching the wiring at a location where a metal protrusion is formed in a later step, and forming the metal protrusion by plating or the like. Alternatively, the chip electrode surface may be sealed at the same time when the semiconductor chip electrode and the metal protrusion are connected by heating and pressurization. As the resin applied for sealing, for example, silica having a diameter of about 10 to 20 μm is used.
Epoxy resin or the like containing 80 wt% is applicable.
【００１１】図１は、本発明の半導体パッケージを製造
する工程の一例を示す断面図であり、１はポリイミドフ
ィルム、２は第１の接着材層、３は第２の接着材層、４
は貫通孔、５は銅箔、６は非貫通孔、７は配線パター
ン、８はダイボンド材、９は半導体チップ、１０は金ワ
イヤ、１１は封止材、１２ははんだボール、１３は半導
体パッケージを示す。FIG. 1 is a cross-sectional view showing an example of a process for manufacturing the semiconductor package of the present invention, wherein 1 is a polyimide film, 2 is a first adhesive layer, 3 is a second adhesive layer, 4
Is a through hole, 5 is a copper foil, 6 is a non-through hole, 7 is a wiring pattern, 8 is a die bonding material, 9 is a semiconductor chip, 10 is a gold wire, 11 is a sealing material, 12 is a solder ball, and 13 is a semiconductor package. Indicates.
【００１２】[0012]
【発明の効果】本発明により、反りが小さく、かつ、耐
熱性に優れた薄型半導体パッケージが安定的に製造可能
になった。According to the present invention, it is possible to stably manufacture a thin semiconductor package having a small warpage and excellent heat resistance.
【図１】本発明の半導体パッケージを製造する工程の一
例を示す断面図。FIG. 1 is a cross-sectional view showing an example of a process of manufacturing a semiconductor package of the present invention.
１ ポリイミドフィルム ２ 第１の接着材層 ３ 第２の接着材層 ４ 貫通孔 ５ 銅 箔 ６ 非貫通孔 ７ 配線パターン ８ ダイボンド材 ９ 半導体チップ １０ 金ワイヤ １１ 封止材 １２ はんだボール １３ 半導体パッケージ 1 Polyimide film 2 First adhesive layer 3 Second adhesive layer 4 through holes 5 copper foil 6 Non-through hole 7 wiring pattern 8 Die bond material 9 Semiconductor chips 10 gold wire 11 Sealant 12 solder balls 13 Semiconductor package
フロントページの続き (72)発明者 大畑 洋人 茨城県つくば市和台48 日立化成工業株 式会社 筑波開発研究所内 (72)発明者 野村 宏 茨城県下館市大字五所宮1150番地 日立 化成工業株式会社 五所宮工場内 (72)発明者 田口 矩之 茨城県つくば市和台48 日立化成工業株 式会社 筑波開発研究所内 (56)参考文献 特開 平７−176572（ＪＰ，Ａ) 特開 平６−112354（ＪＰ，Ａ) 特開 平４−277636（ＪＰ，Ａ) 特開 平２−98154（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 Front page continued (72) Inventor Hiroto Ohata 48 Taiwa, Tsukuba-shi, Ibaraki Hitachi Chemical Co., Ltd. Tsukuba R & D Lab. Miya Factory (72) Inventor Noriyuki Taguchi 48 Wadai, Tsukuba City, Ibaraki Prefecture Hitachi Chemical Co., Ltd. Tsukuba Research Laboratory (56) Reference JP-A-7-176572 (JP, A) JP-A-6-112354 (JP, A) JP-A-4-277636 (JP, A) JP-A-2-98154 (JP, A) (58) Fields investigated (Int.Cl. 7 , DB name) H01L 23/12
Claims (3)
接着材付き絶縁フィルムの第１の接着材面に配線パター
ンが形成されており、第１の接着材層厚さ（Ｔ１）及び
第２の接着材層厚さ（Ｔ２）が１５μｍ以下で、かつ厚
み比率（Ｔ１／Ｔ２）が０．３０〜１５．０であり、第
２の接着材層側から配線パターンに達する外部接続用非
貫通孔が形成されている基板と、 Ｂ．その基板に搭載されその基板の配線パターンと電気
的に接続された半導体チップと、 Ｃ．半導体チップを封止する封止材と、 Ｄ．基板の外部接続用非貫通孔に設けられた外部接続端
子とにより構成される半導体パッケージ。1. A. The wiring pattern is formed on the first adhesive surface of the insulating film with the double-sided adhesive having the first and second adhesive layers, and the first adhesive layer thickness (T1) and
The second adhesive layer thickness (T2) is 15 μm or less and the thickness is
A substrate having a flatness ratio (T1 / T2) of 0.30 to 15.0 and having a non-penetrating hole for external connection reaching the wiring pattern from the second adhesive layer side, and B. A semiconductor chip mounted on the substrate and electrically connected to a wiring pattern on the substrate; An encapsulating material for encapsulating the semiconductor chip, and D. A semiconductor package including an external connection terminal provided in a non-through hole for external connection of a substrate.
で、かつ半導体チップ接続時の絶縁フィルム温度におけ
る接着材の弾性率が１，０００ＭＰａ以上である請求項
１記載の半導体パッケージ。2. The semiconductor package according to claim 1, wherein the glass transition point of the adhesive is 180 ° C. or higher, and the elastic modulus of the adhesive is 1,000 MPa or higher at the temperature of the insulating film when the semiconductor chip is connected.
１）及び第２の接着材層表面の最大粗さ（Ｒｔ２）が１
０μｍ以下で、かつ粗さ比率（Ｒｔ１／Ｒｔ２）が０．
２５〜２０．０である請求項１又は２記載の半導体パッ
ケージ。 3. The maximum roughness (Rt of the surface of the first adhesive layer)
1) and the maximum roughness (Rt2) of the surface of the second adhesive layer is 1
0 μm or less, and the roughness ratio (Rt1 / Rt2) is 0.
25 to 20.0. The semiconductor package according to claim 1 or 2,
cage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20552395A JP3392992B2 (en) | 1995-08-11 | 1995-08-11 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20552395A JP3392992B2 (en) | 1995-08-11 | 1995-08-11 | Semiconductor package |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002347629A Division JP3760913B2 (en) | 2002-11-29 | 2002-11-29 | Semiconductor package substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0955444A JPH0955444A (en) | 1997-02-25 |
| JP3392992B2 true JP3392992B2 (en) | 2003-03-31 |
Family
ID=16508298
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20552395A Expired - Fee Related JP3392992B2 (en) | 1995-08-11 | 1995-08-11 | Semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3392992B2 (en) |
Cited By (1)
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|---|---|---|---|---|
| US20140313683A1 (en) * | 2011-11-09 | 2014-10-23 | Lg Innotek Co., Ltd. | Tape carrier package and method of manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4484891B2 (en) * | 2007-03-08 | 2010-06-16 | 日本テキサス・インスツルメンツ株式会社 | Semiconductor device and manufacturing method thereof |
| KR100999918B1 (en) * | 2008-09-08 | 2010-12-13 | 삼성전기주식회사 | Printed circuit board and method of manufacturing the same |
| KR101897015B1 (en) * | 2012-04-16 | 2018-09-12 | 엘지이노텍 주식회사 | Manufacturing method of chip package member and manufacturing method of chip package |
| TW201318082A (en) * | 2011-09-02 | 2013-05-01 | Lg Innotek Co Ltd | Method of manufacturing substrate for chip packages and method of manufacturing chip package |
| KR101886423B1 (en) * | 2011-11-29 | 2018-09-11 | 엘지이노텍 주식회사 | Chip package member and manufacturing method thereof |
| KR101897069B1 (en) * | 2012-04-16 | 2018-09-12 | 엘지이노텍 주식회사 | Manufacturing method of chip package member and manufacturing method of chip package |
| KR101886346B1 (en) * | 2012-06-27 | 2018-08-09 | 엘지이노텍 주식회사 | Printed circuit board for smart ic and manufacturing method therefor |
| KR102119760B1 (en) * | 2012-12-17 | 2020-06-08 | 엘지이노텍 주식회사 | Printed circuit board for ic module and manufacturing method therefor |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0298154A (en) * | 1988-10-04 | 1990-04-10 | Mitsubishi Electric Corp | Carrier tape |
| JP2962586B2 (en) * | 1991-03-05 | 1999-10-12 | 新光電気工業株式会社 | Semiconductor device, method of manufacturing the same, and joined body used therefor |
| EP0582052A1 (en) * | 1992-08-06 | 1994-02-09 | Motorola, Inc. | Low profile overmolded semiconductor device and method for making the same |
| JPH07176572A (en) * | 1993-12-20 | 1995-07-14 | Hitachi Cable Ltd | Multilayer wiring tab tape carrier and semiconductor device using the same |
-
1995
- 1995-08-11 JP JP20552395A patent/JP3392992B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140313683A1 (en) * | 2011-11-09 | 2014-10-23 | Lg Innotek Co., Ltd. | Tape carrier package and method of manufacturing the same |
| US9674955B2 (en) * | 2011-11-09 | 2017-06-06 | Lg Innotek Co., Ltd. | Tape carrier package, method of manufacturing the same and chip package |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0955444A (en) | 1997-02-25 |
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