JP3760913B2 - Semiconductor package substrate - Google Patents

Semiconductor package substrate Download PDF

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Publication number
JP3760913B2
JP3760913B2 JP2002347629A JP2002347629A JP3760913B2 JP 3760913 B2 JP3760913 B2 JP 3760913B2 JP 2002347629 A JP2002347629 A JP 2002347629A JP 2002347629 A JP2002347629 A JP 2002347629A JP 3760913 B2 JP3760913 B2 JP 3760913B2
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Japan
Prior art keywords
adhesive
substrate
semiconductor package
package
adhesive layer
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Expired - Fee Related
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JP2002347629A
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Japanese (ja)
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JP2003179188A (en
Inventor
良明 坪松
文男 井上
聡夫 山崎
洋人 大畑
宏 野村
矩之 田口
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Showa Denko Materials Co Ltd
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Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体パッケ−ジ用基板に関する。
【０００２】
【従来の技術】
半導体の集積度が向上するに従い、入出力端子数が増加している。従って、多くの入出力端子数を有する半導体パッケージが必要になった。一般に、入出力端子はパッケージの周辺に一列配置するタイプと、周辺だけでなく内部まで多列に配置するタイプがある。前者は、ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）が代表的である。これを多端子化する場合は、端子ピッチを縮小することが必要であるが、０．５ｍｍピッチ以下の領域では、配線板との接続に高度な技術が必要になる。後者のアレイタイプは比較的大きなピッチで端子配列が可能なため、多ピン化に適している。従来、アレイタイプは接続ピンを有するＰＧＡ （Ｐｉｎ Ｇｒｉｄ Ａｒｒａｙ）が一般的であるが、配線板との接続は挿入型となり、表面実装には適していない。このため、表面実装可能なＢＧＡ （ＢａｌｌＧｒｉｄ Ａｒｒａｙ）と称するパッケージが開発されている。また、パッケージの更なる小型・薄型化に対応するものとして、半導体チップとほぼ同等の外形を有する、いわゆるチップサイズパッケージ（ＣＳＰ； Ｃｈｉｐ ＳｉｚｅＰａｃｋａｇｅ）も提案されている。こうした各種パッケージを使用するベース基材で大別すると、（１）．セラミックタイプ、（２）．プリント配線板タイプ及び（３）．フィルムタイプなどに分類される。
【０００３】
このうち、セラミックタイプについては、従来のＰＧＡに比べるとマザーボードとパッケージ間の距離が短くなるために、マザーボードとパッケージ間の熱応力差に起因するパッケージ反りが深刻な問題である。また、プリント配線板タイプについても、基板の耐熱性などに加えて基板厚さが厚いなどの問題があり、ポリイミドフィルムなどの薄くて耐熱性に優れたフィルム基材をベース基材として適用したパッケージが望まれている。
【０００４】
【発明が解決しようとする課題】
フィルム基材をパッケージ用ベース基材として適用する場合、実装工程（チップ接続、封止、はんだリフロー等）に耐える耐熱性を有することと同時に、チップ実装前及びパッケージ化後での反りを極力小さくすることが重要な課題である。
本発明はパッケージの小型・薄型化に対応可能で、かつ、耐熱性に優れたＢＧＡやＣＳＰなどの半導体パッケージの半導体パッケージ用基板を提供するものである。
【０００５】
【課題を解決するための手段】
本願の発明は、第１、第２の接着材層を有する両面接着材付き絶縁フィルムの第１の接着材面に配線パターンが形成されており、第１の接着材層厚さ（Ｔ１）及び第２の接着材層厚さ（Ｔ２）が１５μｍ以下で、かつ厚み比率（Ｔ１／Ｔ２）が０．３０〜１５．０であり、第２の接着材層側から配線パターンに達する外部接続用非貫通孔が形成されている半導体パッケージ用基板に関する。この基板に半導体チップを基板の配線パターンと電気的に接続させて搭載し、半導体チップを封止材で封止し、基板の外部接続用非貫通孔に外部接続端子を設けることにより半導体パッケージとなる。
【０００６】
【発明の実施の形態】
本願の発明の特徴は、絶縁フィルムの片面に形成する金属配線パターンの残存面積率や適用する封止材の熱膨張係数などに応じて、第１及び第２の接着材層の厚み比率及び接着材表面粗さ比率等を適宜設定することにより、基板レベル及びパッケージレベルでの反り量を調整することができる点にある。この場合、第１及び第２の接着材層厚さ（Ｔ１及びＴ２）は１５μｍ以下で、かつ、厚み比率（Ｔ１／Ｔ２）は０．３０〜１５．０の範囲にあることが好ましい。
【０００７】
また、更に好ましくは、第１及び第２の接着材層表面の最大粗さ（Ｒｔ１及びＲｔ２）が１０μｍ以下で、かつ、粗さ比率（Ｒｔ１／Ｒｔ２）が０．２５〜２０．０の範囲にあれば良い。接着材層の厚さは、例えば、接着材ワニスを塗工する際のギャップや塗工速度などを調整することにより制御可能である。また、第１及び第２の接着材層の表面粗さは、それぞれ、接着材と接する銅箔面や離型基材面の粗度によって調整できる。
【０００８】
非貫通孔の形成方法は特に限定するものではなく、（１）．公知のドリルやパンチ加工などにより予め接着材付き絶縁フィルムに貫通孔を設けた後、銅箔を片面に加熱・加圧することにより貫通孔の片側を塞ぐ方法、（２）．接着材付きフィルムの片面に銅箔を加熱・加圧した後、例えば、炭酸ガスレーザ等で銅箔に達する非貫通孔を直接形成する方法、（３）．接着材付きフィルムの両面に銅箔を加熱・加圧した後、一方の側の銅箔をエッチング除去し、（２）．項と同様に直接非貫通孔を形成する方法などが適用可能である。なお、（２）及び（３）項においては、非貫通孔は配線パターンを形成する側の銅箔を配線加工する前に形成しても良いし、配線パターン形成後に形成しても良い。
【０００９】
配線パターンの形成方法についても特に限定されるものではなく、通常の銅箔用エッチング液を適用したサブトラクト法や金属箔上に配線パターンを予め電気めっき法で形成しておき、配線パターンを接着材層中に埋込んで転写した後、金属箔を選択的に除去する方法などが適用可能である。
【００１０】
一方、チップ電極と配線との導通化方法として金ワイヤボンディングやフェースダウンボンディングなどが適用可能である。前者の場合は、配線パターン下部に存在する接着材層の耐熱性及び硬さが重要な要因であり、ガラス転移点１８０℃以上で、かつ、ワイヤボンディング温度に於ける弾性率が１，０００ＭＰａ以上であることが好ましい。また、ボンディング時の絶縁基材温度を熱硬化性接着材のガラス転移点より低い温度で行なうことにより、よりいっそう安定的なワイヤボンディングが可能になる。後者の場合は、予め配線上に半導体チップ電極と接続する金属突起部を形成し、半導体チップ電極を金属突起が設けられている面に面して搭載し、半導体チップ電極と金属突起とを接続する。この場合、予め配線領域の所望する部分を熱可塑性ポリイミド接着材等で覆い、後工程で金属突起部を形成する箇所に配線に達する非貫通凹部を設け、めっき等で金属突起部を形成した後、半導体チップ電極と金属突起部とを加熱・加圧により接続させると同時にチップ電極面を封止しても良い。封止に適用する樹脂としては、例えば、直径１０〜２０μｍ程度のシリカを５〜８０ｗｔ％の範囲で含有したエポキシ樹脂等が適用可能である。
【００１１】
図１は、本発明の半導体パッケージ用基板を用いて半導体パッケージを製造する工程の一例を示す断面図であり、１はポリイミドフィルム、２は第１の接着材層、３は第２の接着材層、４は貫通孔、５は銅箔、６は非貫通孔、７は配線パターン、８はダイボンド材、９は半導体チップ、１０は金ワイヤ、１１は封止材、１２ははんだボール、１３は半導体パッケージを示す。
【００１２】
【発明の効果】
本発明により、反りが小さく、かつ、耐熱性に優れた薄型半導体パッケージが安定的に製造可能になった。
【図面の簡単な説明】
【図１】本発明の半導体パッケージ用基板を用いて半導体パッケージを製造する工程の一例を示す断面図。
【符号の説明】
１ ポリイミドフィルム
２ 第１の接着材層
３ 第２の接着材層
４ 貫通孔
５ 銅 箔
６ 非貫通孔
７ 配線パターン
８ ダイボンド材
９ 半導体チップ
１０ 金ワイヤ
１１ 封止材
１２ はんだボール
１３ 半導体パッケージ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor package substrate.
[0002]
[Prior art]
As the degree of integration of semiconductors has improved, the number of input / output terminals has increased. Therefore, a semiconductor package having a large number of input / output terminals is required. Generally, there are a type in which input / output terminals are arranged in a row around the package and a type in which the input / output terminals are arranged in multiple rows not only in the periphery but also in the interior. The former is typically QFP (Quad Flat Package). In order to increase the number of terminals, it is necessary to reduce the terminal pitch. However, in a region having a pitch of 0.5 mm or less, advanced technology is required for connection to the wiring board. The latter array type is suitable for increasing the number of pins because terminals can be arranged with a relatively large pitch. Conventionally, the array type is generally a PGA (Pin Grid Array) having connection pins, but the connection to the wiring board is an insertion type and is not suitable for surface mounting. For this reason, a package called BGA (Ball Grid Array) that can be surface mounted has been developed. Also, a so-called chip size package (CSP; Chip Size Package) having an outer shape almost equivalent to that of a semiconductor chip has been proposed as a countermeasure for further downsizing and thinning of the package. The base substrate using these various packages can be broadly classified as (1). Ceramic type, (2). Printed wiring board type and (3). Classified as film type.
[0003]
Among these, the ceramic type has a serious problem of package warpage due to the difference in thermal stress between the mother board and the package because the distance between the mother board and the package is shorter than the conventional PGA. In addition, the printed wiring board type has a problem that the substrate thickness is large in addition to the heat resistance of the substrate, etc., and a package that uses a thin and excellent heat resistant film substrate such as a polyimide film as the base substrate Is desired.
[0004]
[Problems to be solved by the invention]
When applying a film substrate as a base substrate for a package, it has heat resistance to withstand mounting processes (chip connection, sealing, solder reflow, etc.), and at the same time minimizes warping before chip mounting and after packaging. This is an important issue.
The present invention provides a semiconductor package substrate for a semiconductor package such as a BGA or CSP that can cope with a reduction in the size and thickness of the package and has excellent heat resistance.
[0005]
[Means for Solving the Problems]
In the invention of the present application, a wiring pattern is formed on the first adhesive surface of the insulating film with double-sided adhesive having the first and second adhesive layers, and the first adhesive layer thickness (T1) and For external connection, the second adhesive layer thickness (T2) is 15 μm or less and the thickness ratio (T1 / T2) is 0.30 to 15.0, reaching the wiring pattern from the second adhesive layer side The present invention relates to a semiconductor package substrate in which a non-through hole is formed. A semiconductor chip is mounted on the substrate by being electrically connected to the wiring pattern of the substrate, the semiconductor chip is sealed with a sealing material, and an external connection terminal is provided in a non-through hole for external connection of the substrate. Become.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
The feature of the invention of the present application is that the thickness ratio and adhesion of the first and second adhesive layers depend on the remaining area ratio of the metal wiring pattern formed on one side of the insulating film and the thermal expansion coefficient of the sealing material to be applied. The amount of warpage at the board level and the package level can be adjusted by appropriately setting the material surface roughness ratio and the like. In this case, the first and second adhesive layer thicknesses (T1 and T2) are preferably 15 μm or less, and the thickness ratio (T1 / T2) is preferably in the range of 0.30 to 15.0.
[0007]
More preferably, the maximum roughness (Rt1 and Rt2) of the first and second adhesive layer surfaces is 10 μm or less, and the roughness ratio (Rt1 / Rt2) is in the range of 0.25 to 20.0. If it is in. The thickness of the adhesive layer can be controlled, for example, by adjusting a gap or a coating speed when the adhesive varnish is applied. Moreover, the surface roughness of the 1st and 2nd adhesive material layer can each be adjusted with the roughness of the copper foil surface which contacts an adhesive material, or a mold release base material surface.
[0008]
The method for forming the non-through hole is not particularly limited, and (1). A method in which a through hole is provided in an insulating film with an adhesive in advance by a known drill or punching process, and then one side of the through hole is closed by heating and pressing a copper foil on one side; (2). A method of directly forming a non-through hole reaching the copper foil with a carbon dioxide gas laser or the like after the copper foil is heated and pressurized on one side of the film with the adhesive, (3). After heating and pressurizing the copper foil on both sides of the adhesive-attached film, the copper foil on one side is removed by etching, (2). The method of forming a non-through-hole directly etc. is applicable similarly to a term. In the items (2) and (3), the non-through hole may be formed before the wiring pattern forming copper foil is processed or after the wiring pattern is formed.
[0009]
The method for forming the wiring pattern is not particularly limited, and a wiring pattern is formed in advance by an electroplating method on a subtract method or a metal foil to which a normal copper foil etching solution is applied. A method of selectively removing the metal foil after being embedded and transferred in the layer is applicable.
[0010]
On the other hand, gold wire bonding, face-down bonding, or the like is applicable as a method for conducting the chip electrode and the wiring. In the former case, the heat resistance and hardness of the adhesive layer present under the wiring pattern are important factors, the glass transition point is 180 ° C. or higher, and the elastic modulus at the wire bonding temperature is 1,000 MPa or higher. It is preferable that Further, by performing the insulating substrate temperature at the time of bonding at a temperature lower than the glass transition point of the thermosetting adhesive, it becomes possible to perform more stable wire bonding. In the latter case, a metal protrusion to be connected to the semiconductor chip electrode is formed on the wiring in advance, the semiconductor chip electrode is mounted facing the surface provided with the metal protrusion, and the semiconductor chip electrode and the metal protrusion are connected. To do. In this case, after covering the desired part of the wiring area in advance with a thermoplastic polyimide adhesive or the like, providing a non-penetrating recess that reaches the wiring at a location where the metal protrusion is to be formed in a later step, and forming the metal protrusion by plating or the like The chip electrode surface may be sealed at the same time that the semiconductor chip electrode and the metal protrusion are connected by heating and pressing. As a resin applied for sealing, for example, an epoxy resin containing silica having a diameter of about 10 to 20 μm in a range of 5 to 80 wt% is applicable.
[0011]
FIG. 1 is a cross-sectional view showing an example of a process for manufacturing a semiconductor package using the substrate for a semiconductor package of the present invention, wherein 1 is a polyimide film, 2 is a first adhesive layer, and 3 is a second adhesive. Layers, 4 through holes, 5 copper foil, 6 non-through holes, 7 wiring patterns, 8 die bond materials, 9 semiconductor chips, 10 gold wires, 11 encapsulants, 12 solder balls, 13 Indicates a semiconductor package.
[0012]
【The invention's effect】
According to the present invention, a thin semiconductor package having small warpage and excellent heat resistance can be stably manufactured.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing an example of a process for manufacturing a semiconductor package using a semiconductor package substrate of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Polyimide film 2 1st adhesive material layer 3 2nd adhesive material layer 4 Through-hole 5 Copper foil 6 Non-through-hole 7 Wiring pattern 8 Die-bonding material 9 Semiconductor chip 10 Gold wire 11 Sealing material 12 Solder ball 13 Semiconductor package

Claims (3)

第１、第２の接着材層を有する両面接着材付き絶縁フィルムの第１の接着材面に配線パターンが形成されており、第１の接着材層厚さ（Ｔ１）及び第２の接着材層厚さ（Ｔ２）が１５μｍ以下で、かつ厚み比率（Ｔ１／Ｔ２）が０．３０〜１５．０であり、第２の接着材層側から配線パターンに達する外部接続用非貫通孔が形成されている半導体パッケージ用基板。A wiring pattern is formed on the first adhesive surface of the insulating film with double-sided adhesive having the first and second adhesive layers, the first adhesive layer thickness (T1) and the second adhesive The layer thickness (T2) is 15 μm or less and the thickness ratio (T1 / T2) is 0.30 to 15.0, and a non-through hole for external connection reaching the wiring pattern from the second adhesive layer side is formed. Semiconductor package substrate. 接着材のガラス転移点が１８０℃以上で、かつ半導体チップ接続時の絶縁フィルム温度における接着材の弾性率が１，０００ＭＰａ以上である請求項１記載の半導体パッケージ用基板。The substrate for a semiconductor package according to claim 1, wherein the glass transition point of the adhesive is 180 ° C or higher, and the elastic modulus of the adhesive at the insulating film temperature when the semiconductor chip is connected is 1,000 MPa or higher. 第１の接着材層表面の最大粗さ（Ｒｔ１）及び第２の接着材層表面の最大粗さ（Ｒｔ２）が１０μｍ以下で、かつ粗さ比率（Ｒｔ１／Ｒｔ２）が０．２５〜２０．０である請求項１又は２記載の半導体パッケージ用基板。The maximum roughness (Rt1) of the first adhesive layer surface and the maximum roughness (Rt2) of the second adhesive layer surface are 10 μm or less, and the roughness ratio (Rt1 / Rt2) is 0.25 to 20. The substrate for a semiconductor package according to claim 1, wherein the substrate is 0.
JP2002347629A 2002-11-29 2002-11-29 Semiconductor package substrate Expired - Fee Related JP3760913B2 (en)

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JP20552395A Division JP3392992B2 (en) 1995-08-11 1995-08-11 Semiconductor package

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KR101776322B1 (en) * 2011-09-02 2017-09-07 엘지이노텍 주식회사 Method of manufacturing chip package member

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JPS62114286A (en) * 1985-11-14 1987-05-26 松下電工株式会社 Wiring board
JP2962586B2 (en) * 1991-03-05 1999-10-12 新光電気工業株式会社 Semiconductor device, method of manufacturing the same, and joined body used therefor
EP0582052A1 (en) * 1992-08-06 1994-02-09 Motorola, Inc. Low profile overmolded semiconductor device and method for making the same

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