KR101886423B1 - Chip package member and manufacturing method thereof - Google Patents

Chip package member and manufacturing method thereof Download PDF

Info

Publication number
KR101886423B1
KR101886423B1 KR1020110125656A KR20110125656A KR101886423B1 KR 101886423 B1 KR101886423 B1 KR 101886423B1 KR 1020110125656 A KR1020110125656 A KR 1020110125656A KR 20110125656 A KR20110125656 A KR 20110125656A KR 101886423 B1 KR101886423 B1 KR 101886423B1
Authority
KR
South Korea
Prior art keywords
layer
adhesive layer
circuit pattern
insulating film
adhesive
Prior art date
Application number
KR1020110125656A
Other languages
Korean (ko)
Other versions
KR20130059605A (en
Inventor
김홍일
Original Assignee
엘지이노텍 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 엘지이노텍 주식회사 filed Critical 엘지이노텍 주식회사
Priority to KR1020110125656A priority Critical patent/KR101886423B1/en
Priority to PCT/KR2012/009284 priority patent/WO2013069947A1/en
Priority to US14/357,450 priority patent/US9674955B2/en
Priority to TW101141822A priority patent/TW201328459A/en
Publication of KR20130059605A publication Critical patent/KR20130059605A/en
Application granted granted Critical
Publication of KR101886423B1 publication Critical patent/KR101886423B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45139—Silver (Ag) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Laminated Bodies (AREA)
  • Structure Of Printed Boards (AREA)
  • Wire Bonding (AREA)

Abstract

The present invention relates to a chip package member and a method of manufacturing the same, and more particularly, to a chip package member and a method of manufacturing the same, which comprises a flexible copper clad laminate (FCCL) having a structure in which an insulating film, an adhesive layer, and a copper foil layer are sequentially layered, A copper foil layer of the flexible copper-clad laminate film is etched and removed, and a lower adhesive layer is formed under the insulation layer to form a base material, a through hole is formed in the base material, Layer is formed to manufacture a chip package member, it is possible to improve the reliability of the chip package by improving the adhesive force between the molding resin and the insulating film in the later manufacturing of the package.

Description

[0001] CHIP PACKAGE MEMBER AND MANUFACTURING METHOD THEREOF [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to chip package technology, and more particularly to chip package member manufacturing technology.

Semiconductor or optical device package technology has been steadily developed in accordance with demands for high density, miniaturization, and high performance. However, since it is relatively inferior to semiconductor manufacturing technology, development of package technology is required to solve the demand for high performance, miniaturization and high density Have recently emerged.

Related to the semiconductor / optical device package, a silicon chip, an LED (Light Emitting Diode) chip, a smart IC chip and the like are bonded on a substrate through wire bonding or LOC (Lead On Chip) bonding.

1 is a sectional view of a general smart IC chip package.

1, a typical smart IC chip package includes an insulating layer 10 having a via hole formed therein, a circuit pattern layer 20 formed on one surface of the insulating layer 10, a circuit pattern layer 20 exposed through the via hole, And an IC chip (30) mounted on the exposed portion.

The IC chip 30 is electrically connected to the circuit pattern layer 20 by the wire 40. 1, the IC chip 30 and the wire 40 are molded by a molding part 50 made of epoxy resin or the like. The molding part 50 is composed of an insulating layer 10, As shown in FIG.

In this case, the insulating layer 10 has insufficient roughness on the surface thereof, which causes a problem that the adhesion power is lowered at the interface 52 contacting with the molding part 50. Accordingly, 50 is separated from the insulating layer 10, and as a result, the reliability and durability of the product deteriorate.

Particularly, when the insulating layer 10 is formed of a polyimide rather than an epoxy resin, the peeling phenomenon described above has been further exacerbated by the characteristics of the polyimide itself having a very low surface energy and poor surface adhesion.

Disclosure of Invention Technical Problem [8] The present invention has been proposed in order to solve the problems of the related art described above, and it is an object of the present invention to provide a chip package member by using a flexible copper clad laminate (FCCL) A chip package member capable of improving the adhesive force between the package member and the molding part, and a method of manufacturing the same.

According to another aspect of the present invention, there is provided a method of manufacturing a chip package member, the method comprising: forming a flexible copper clad laminate (FCCL) having an insulating film, an adhesive layer and a copper foil layer sequentially formed on the adhesive layer, A copper alloy layer of the flexible copper clad laminate film is etched and removed to form a lower adhesive layer under the insulating layer to form a base material, a through hole is formed in the base material, And forming a circuit pattern layer on the substrate.

In the method of manufacturing a chip package member of the present invention, the production of the flexible copper-clad laminate film may be performed by forming the adhesive layer on the insulating film, laminating the electrolytic copper foil layer on the adhesive layer, Or the like.

In the method of manufacturing a chip package member of the present invention, the roughness Rz of the surface roughness is preferably in the range of 3 to 10 micrometers, but is not limited thereto.

In the method of manufacturing a chip package member of the present invention, the insulating film may be formed of polyimide or polyethylene naphthalate.

In the method of manufacturing a chip package member of the present invention, the manufacturing of the base material may include applying an adhesive or bonding a bonding sheet to the bottom of the insulating film, and performing a laminating process.

In the method of manufacturing a chip package member of the present invention, the adhesive or the bonding sheet is preferably semi-curable type, but is not limited thereto.

In the method of manufacturing a chip package member of the present invention, the through hole may be formed by a punching process or a laser drilling process.

In the method of manufacturing a chip package member of the present invention, forming the circuit pattern layer may include forming a metal layer below the base material, and etching the metal layer to form a circuit pattern.

In the method of manufacturing a chip package member of the present invention, it is preferable that the material of the metal layer is formed of copper (Cu).

The method of manufacturing a chip package member of the present invention may further include forming a plating layer selectively on the circuit pattern layer after forming the circuit pattern layer.

At this time, the plating layer may include at least one of nickel (Ni and gold).

According to an aspect of the present invention, there is provided a chip package member comprising: an adhesive layer having a surface roughness formed thereon; An insulating film formed under the adhesive layer; A lower adhesive layer formed under the insulating film; And a circuit pattern layer formed under the lower adhesive layer. The roughness Rz of the surface roughness may be in the range of 3 to 10 micrometers.

In addition, the insulating film may be formed of polyimide or polyethylene naphthalate.

According to the present invention, it is possible to improve the roughness on one side of the insulating layer coated with the molding resin in the chip package, thereby improving the adhesive force between the insulating layer and the molding resin.

Further, according to the present invention, the bonding strength between the insulating layer and the molding resin is improved, thereby improving the reliability and durability of the chip package.

In addition, according to the present invention, since a chip package is manufactured using the flexible copper-clad laminated film, the effect of lightening the product, the miniaturization of the product, and the effect of reducing the size of the product can be achieved.

1 is a sectional view of a general smart IC chip package.
2 is a flowchart showing a flow of a method of manufacturing a chip package member according to the present invention.
FIGS. 3A and 3B are schematic diagrams showing process steps of a method of manufacturing a chip package member according to the present invention.
4 is a photograph of the surface of the insulating layer of the conventional chip package member and a photograph of the surface energy measurement.
5 is a photograph of the surface of the insulating layer of the chip package member according to the present invention and a photograph of the surface energy measurement.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be understood, however, that the embodiments described herein and the configurations shown in the drawings are only a preferred embodiment of the present invention, and that various equivalents and modifications may be made thereto at the time of the present application. DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following description, well-known functions or constructions are not described in detail to avoid obscuring the subject matter of the present invention. The following terms are defined in consideration of the functions of the present invention, and the meaning of each term should be interpreted based on the contents throughout this specification. The same reference numerals are used for portions having similar functions and functions throughout the drawings.

2 is a flowchart showing a flow of a method of manufacturing a chip package member according to the present invention.

2, a method of manufacturing a chip package member according to the present invention includes the steps of (S1) fabricating a flexible copper clad laminate (FCCL) having a structure in which an insulating film, an adhesive layer and a copper foil layer are sequentially layered, The copper foil layer of the copper foil laminated film is etched and removed (S3), and a lower adhesive layer is formed under the insulating layer to produce a base material (S5), a through hole is formed in the base material (S7) And forming a pattern layer (S9). Although not shown in the drawings, the method may further include a step of selectively forming a plating layer on the circuit pattern layer after step S9.

Specifically, step S1 may be performed as follows.

First, an insulating film is prepared. At this time, the material of the insulating film may be a polyimide resin film material or a polyethylene naphthalate resin film material, but it is preferably formed of a polyimide resin film material, but is not limited thereto.

Thereafter, an adhesive layer is formed on one surface of the insulating film. At this time, the material forming the adhesive layer may be formed of a material containing at least one of epoxy resin, acrylic resin and polyimide resin, and it is particularly preferable to use an epoxy resin or a polyimide resin. For the purpose of imparting flexibility to these adhesive layer-forming materials, various natural rubbers, plasticizers, hardeners, flame retardants such as phosphorus, and various other additives may be added. In addition, a thermoplastic polyimide resin may be used as the polyimide resin, although thermoplastic polyimide is often used. However, it is to be understood that this is only one example, and that the adhesive layer of the present invention can be formed with a resin having all the adhesives that have been developed, commercialized, or can be implemented according to future technological developments.

Then, an electrolytic copper foil is laminated on the adhesive layer to form a copper foil layer. At this time, the roughness formed on the surface of the electrolytic copper foil is reflected on the adhesive layer, and as a result, surface roughness is formed on the adhesive layer. At this time, the roughness (Rz) of the surface roughness formed on the adhesive layer can be controlled by adjusting conditions such as the thickness of the electrolytic copper foil and the laminating condition (e.g., temperature or pressure). The surface roughness (Rz) formed on the adhesive layer is preferably within a range of 3 to 10 micrometers, but is not limited thereto. When the roughness (Rz) is less than 3 micrometers, it is difficult to obtain the effect of improving adhesion with the molding part formed in the production of the finished product in the future. When the roughness (Rz) is formed to exceed 10 micrometers, So that there is a problem of causing contamination in the manufacturing process related to the chip package.

After the flexible copper-clad laminated film is produced, the above-described copper foil layer is removed through an etching process (S3). When the copper foil layer is thus removed, it becomes possible to obtain a structure comprising an insulating layer and an adhesive layer formed on the insulating layer and having a surface roughness. Accordingly, when the molding resin is coated on the insulating layer, the adhesion between the insulating layer and the molding resin is increased due to surface roughness formed on the insulating layer, and reliability and durability of the chip package are improved.

After removing the copper foil layer (S3), a lower adhesive layer is formed under the insulating layer among the structures obtained in the step S3. Hereinafter, a structure in which a lower adhesive layer, an insulating layer and an adhesive layer are sequentially layered is defined as a base material.

The lower adhesive layer may be formed by a method of performing a laminating process after application of an adhesive, or a method of attaching a bonding sheet to a lower portion of an insulating layer and then performing a laminating process.

When the lower adhesive layer is formed by applying an adhesive, the adhesive may be formed of a material including at least one of an epoxy resin, an acrylic resin and a polyimide resin in the same manner as the adhesive layer in the step S1, and an epoxy resin or a polyimide resin . For the purpose of imparting flexibility to these adhesives, various natural rubbers, plasticizers, hardeners, flame retardants such as phosphorus, and various other additives may be added. In addition, a thermoplastic polyimide resin may be used as the polyimide resin, although thermoplastic polyimide is often used.

Thereafter, at least one through hole is formed in the base material obtained in the step S5 (S7). These through holes may include via holes for mounting the chips, via holes for electrical connection between the respective layers, thermal via holes for facilitating thermal diffusion, and via holes for aligning the respective layers. The through hole may be formed by a method of punching, a method of performing a drilling process using a laser, or the like. In addition, A method of forming a through hole may be used.

After the through hole is formed in the base material in step S7, a circuit pattern layer is formed under the base material (S9). At this time, the formation of the circuit pattern layer can be performed as follows. First, a metal layer is formed under the base material. At this time, the metal layer is preferably made of copper (Cu), but is not limited thereto. Then, the metal layer is etched to form a circuit pattern. More specifically, after the surface of the metal layer is activated by various chemical treatments, a photoresist is applied, and exposure and development processes are performed. After the development process is completed, a necessary circuit is formed through an etching process and the photoresist is peeled off to form a circuit pattern layer.

On the other hand, although not shown in the figure, the plating process may be further performed after step S9. At this time, the plating process is preferably an electrolytic plating process, and at least one of nickel (Ni) and gold (Au) may be used as the material to be plated.

The chip package member produced by the above-described method can improve surface roughness and improve roughness on one surface of the insulating film to which the molding resin is applied, thereby improving the adhesion between the insulating film and the molding resin, The reliability and durability of the package (for example, COB type, etc.) can be improved. In addition, despite the use of polyimide as an insulating film, it has the effect of improving the adhesion with the molding resin and the effect of improving the heat resistance, mechanical properties, electrical properties and flame retardancy of the product due to the use of polyimide . In addition, since the chip package is manufactured using the flexible copper-clad laminated film, the effect of lightening the product, the miniaturization of the product, and the effect of reducing the thickness can be additionally obtained.

FIGS. 3A and 3B are schematic diagrams showing process steps of a method of manufacturing a chip package member according to the present invention.

Referring to FIGS. 2 to 3B, an adhesive layer 130 is formed on the insulating film 110, as shown in FIG. 3A. Then, the copper foil layer 150 is formed by laminating an electrolytic copper foil on the adhesive layer 130 as shown in FIG. 3A. At this time, roughness formed on the surface of the electrolytic copper foil is reflected on the adhesive layer 130 to form a surface roughness on the adhesive layer 130. By controlling the conditions such as the thickness of the electrolytic copper foil and the laminating condition (e.g., temperature or pressure) It is possible to control the roughness Rz of the surface roughness formed on the surface of the wafer W as described above in the description of FIG.

After the copper foil layer is removed through the etching process, a structure having surface roughness 131 is formed on the adhesive layer 130 as shown in FIG. 3A. At this time, the roughness Rz of the surface roughness 131 is preferably formed within a range of 3 to 10 micrometers in order to improve adhesion with the molding resin and to prevent normal contamination of the manufacturing process. However, As shown above.

After removing the copper foil layer, a lower adhesive layer 210 is formed on the lower part of the insulating film 110 as shown in (d) of FIG. At this time, the lower adhesive layer 210 may be formed by performing a laminating process after applying the adhesive, or by a method of performing a laminating process after attaching the bonding sheet.

3A, a through hole 230 is formed in the base material 200. At this time, a punching process, a laser drilling process, or the like is used for forming the through hole 230 . The through holes 230 may be formed by a photolithography process, such as a photolithography process, such as a photolithography process, such as a photolithography process, a photolithography process, and a photolithography process. As described above in the description of FIG.

After the formation of the through hole 230, a metal layer 310 is formed on the lower portion of the base material 200, more specifically, under the insulating film 110, as shown in FIG. The metal layer 310 may be formed by a laminating process. Copper (Cu) may be used as the metal layer 310, but the present invention is not limited thereto.

Thereafter, the surface of the metal layer 310 is activated through various chemical treatments, then the photoresist is applied, and the exposure and development processes are performed. After the development process is completed, a circuit pattern layer 330 as shown in FIG. 3B, g) is formed by forming a necessary circuit pattern through the etching process and peeling off the photoresist, thereby manufacturing a chip package member.

Meanwhile, the plating layer 400 may further be formed as shown in FIG. 3B (h) by further performing a plating process on the chip package member, and an electrolytic plating process may be used as such a plating process. More specifically, gold (Au) is plated on the lower portion (contact region) of the circuit pattern layer 330 to form a plating layer 430, based on the drawing shown in FIG. 3 (h). Nickel (Ni) is plated on the upper part of the circuit pattern layer 330 exposed by the through hole 230 to form a plating layer 410.

Although not shown in the drawing, a molding part is formed by applying a molding resin to the insulating film 110. In the insulating layer 110, an adhesive layer 120 having surface roughness is formed on the surface to which the molding resin is applied have. Accordingly, when the molding resin is coated on the insulating layer 110, the adhesion between the insulating layer 110 and the molding part is increased due to surface roughness, and as a result, a chip package having excellent reliability and durability can be manufactured .

FIG. 4 is a photograph of a surface of a conventional chip package member, and FIG. 5 is a photograph of a surface of a surface of an insulating layer of the chip package member according to the present invention and a photograph of surface energy measurement.

More specifically, FIG. 4A is an electron microscope (SEM) image obtained by enlarging the upper portion of the insulating layer formed of the epoxy resin in the chip package according to the prior art by 5,000 times, FIG. 5A is a cross- (SEM) image of the chip package of the present invention using an insulating film of 2000 times magnification. As a result, it can be seen from the naked eye that the roughness of the portion to which the molding resin is applied is remarkably improved as compared with the prior art.

FIG. 4 (b) is a photograph of the surface energy measured in forming the molding resin in the chip package according to the prior art, FIG. 5 (b) to be. As the surface energy increases, the attraction force decreases and the contact angle decreases. Conversely, as the surface energy decreases, the attraction force decreases and the contact angle increases. The contact angle? 1 of the molding resin of the prior art chip package (FIG. 4B) and the contact angle? 2 of the molding resin of the chip package of the present invention (FIG. 5B) The contact angle? 2 of the molding resin according to the present invention is smaller than that in the prior art (? 1). Therefore, in the present invention, the adhesion between the insulating film and the molding resin is improved due to an increase in surface energy. can confirm.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, Those skilled in the art will appreciate that many suitable modifications and variations are possible in light of the present invention. Accordingly, all such modifications and variations as fall within the scope of the present invention should be considered.

110: insulating film
130: Adhesive layer
131: Surface roughness
150: copper foil layer
200: base material
210: Lower adhesive layer
310: metal layer
330: circuit pattern layer
400: plated layer

Claims (13)

A flexible copper clad laminate (FCCL) having an insulating film, a first adhesive layer on the insulating film, a copper foil layer on the first adhesive layer, and a surface roughness is formed on the first adhesive layer,
The copper foil layer of the flexible copper clad laminated film is etched and removed,
Forming a second adhesive layer below the insulating layer to produce a base material,
A through hole is formed in the base material,
A circuit pattern layer is formed below the second adhesive layer of the base material,
Forming a first plating layer on the circuit pattern layer to fill a part of the through hole,
And forming a second plating layer below the circuit pattern layer,
The through-
The first adhesive layer, the insulating layer, and the second adhesive layer,
The lower surface of the first plating layer is in direct contact with the upper surface of the circuit pattern layer,
Wherein the thickness of the first plating layer is equal to the thickness of the second adhesive layer,
The width of the second plating layer is equal to the width of the circuit pattern layer,
Wherein the second plating layer has a width of the upper surface and a width of the lower surface of the second plating layer. The method according to claim 1,
To produce the flexible copper clad laminated film,
Forming the first adhesive layer on the insulating film,
And laminating an electrolytic copper foil layer on the first adhesive layer to form the surface roughness and the copper foil layer. The method of claim 2,
The roughness Rz of the surface roughness,
Wherein the thickness of the chip package member is in the range of 3 to 10 micrometers.
The method of claim 3,
Wherein the insulating film
A method of manufacturing a chip package member formed of polyimide or polyethylene naphthalate.
The method according to claim 1,
To manufacture the base material,
Applying an adhesive or attaching a bonding sheet constituting the second adhesive layer to the lower part of the insulating film,
And performing a laminating process. The method of claim 5,
Wherein the adhesive or the bonding sheet constituting the second adhesive layer is a semi-cured type. The method according to claim 1,
The formation of the through-
And forming a through hole penetrating from the upper surface of the first adhesive layer to the lower surface of the second adhesive layer by a punching process or a laser drilling process. The method according to claim 1,
The reason why the circuit pattern layer is formed is that,
A metal layer is formed on a lower portion of the second adhesive layer constituting the base material,
And etching the metal layer to form a circuit pattern layer. The method of claim 8,
The material of the metal layer is,
(Cu).
delete The method according to claim 1,
Wherein the first and second plating layers are formed on the substrate,
Nickel (Ni), and gold (Au). A base material including an insulating film, a first adhesive layer disposed on the insulating film, and a second adhesive layer disposed under the insulating film;
A circuit pattern layer laminated under the second adhesive layer of the base material;
A through hole penetrating from the upper surface of the first adhesive layer of the base material to the lower surface of the second adhesive layer;
A first plating layer disposed on the circuit pattern layer in the through hole; And
And a second plating layer disposed below the circuit pattern layer,

A surface roughness is formed on the upper surface of the first adhesive layer,
The roughness Rz of the surface roughness satisfies a range of 3 to 10 micrometers,
The through-
The first adhesive layer, the insulating layer, and the second adhesive layer,
The lower surface of the first plating layer is in direct contact with the upper surface of the circuit pattern layer,
Wherein the thickness of the first plating layer is equal to the thickness of the second adhesive layer,
The width of the second plating layer is equal to the width of the circuit pattern layer,
Wherein the second plating layer has a width of a top surface and a width of a bottom surface that are equal to each other. The method of claim 12,
Wherein the insulating film is formed of a polyimide-based film or a polyethylene naphthalate.
KR1020110125656A 2011-11-09 2011-11-29 Chip package member and manufacturing method thereof KR101886423B1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
KR1020110125656A KR101886423B1 (en) 2011-11-29 2011-11-29 Chip package member and manufacturing method thereof
PCT/KR2012/009284 WO2013069947A1 (en) 2011-11-09 2012-11-06 Tape carrier package and method of manufacturing the same
US14/357,450 US9674955B2 (en) 2011-11-09 2012-11-06 Tape carrier package, method of manufacturing the same and chip package
TW101141822A TW201328459A (en) 2011-11-09 2012-11-09 Tape carrier package and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110125656A KR101886423B1 (en) 2011-11-29 2011-11-29 Chip package member and manufacturing method thereof

Publications (2)

Publication Number Publication Date
KR20130059605A KR20130059605A (en) 2013-06-07
KR101886423B1 true KR101886423B1 (en) 2018-09-11

Family

ID=48858395

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110125656A KR101886423B1 (en) 2011-11-09 2011-11-29 Chip package member and manufacturing method thereof

Country Status (1)

Country Link
KR (1) KR101886423B1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100797708B1 (en) * 2006-10-24 2008-01-23 삼성전기주식회사 Fabricating method of printed circuit board
KR100951939B1 (en) * 2009-05-08 2010-04-09 (주)인터플렉스 Method of manufacturing flexible printed circuit board

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3392992B2 (en) * 1995-08-11 2003-03-31 日立化成工業株式会社 Semiconductor package

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100797708B1 (en) * 2006-10-24 2008-01-23 삼성전기주식회사 Fabricating method of printed circuit board
KR100951939B1 (en) * 2009-05-08 2010-04-09 (주)인터플렉스 Method of manufacturing flexible printed circuit board

Also Published As

Publication number Publication date
KR20130059605A (en) 2013-06-07

Similar Documents

Publication Publication Date Title
JP5306789B2 (en) Multilayer wiring board and manufacturing method thereof
US9226382B2 (en) Printed wiring board
JP4783843B2 (en) Electronic component built-in printed circuit board
JP2006049819A (en) Wiring substrate for mounting semiconductor, its manufacturing method, and semiconductor package
JP2015041773A (en) Interposer substrate and method of manufacturing the same
US8487192B2 (en) Printed wiring board and method for manufacturing the same
JP2008181977A (en) Package, manufacturing method thereof, semiconductor device using the same, and manufacturing method of semiconductor device using the same
US9466543B2 (en) Semiconductor package substrate, package system using the same and method for manufacturing thereof
KR101897069B1 (en) Manufacturing method of chip package member and manufacturing method of chip package
US9818714B2 (en) Method of manufacturing substrate for chip packages and method of manufacturing chip package
JP3841079B2 (en) Wiring substrate, semiconductor package, substrate insulating film, and method of manufacturing wiring substrate
KR102119760B1 (en) Printed circuit board for ic module and manufacturing method therefor
KR101886423B1 (en) Chip package member and manufacturing method thereof
JP2016100352A (en) Printed wiring board and manufacturing method of the same
JP2009004813A (en) Wiring substrate for mounting semiconductor
KR101886340B1 (en) Smart ic module and method of producing the same
KR101897102B1 (en) Manufacturing method of chip package member for smart ic and manufacturing method of chip package
JP2005268810A (en) Wiring board, semiconductor package, base insulating film, and manufacturing method of wiring board
WO2023189540A1 (en) Glass wiring board, manufacturing method therefor, and imaging device
KR101897015B1 (en) Manufacturing method of chip package member and manufacturing method of chip package
TWI420996B (en) Printed circuit board and method of manufacturing the same
TWI482249B (en) Substrate for chip packages and method of manufacturing substrate for chip packages
KR101956103B1 (en) Printed circuit board and for smart ic module having this board
KR101776322B1 (en) Method of manufacturing chip package member
KR101795054B1 (en) Chip package member and manufacturing method thereof

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right