JP3374504B2 - Method for manufacturing thin film transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor.

[0002]

2. Description of the Related Art Some thin film transistors are provided with a silicide wiring in order to reduce the sheet resistance and increase the on-current. In the case of manufacturing such a conventional thin film transistor, as an example, as shown in FIG. 2A, first, a gate electrode 2 is formed at a predetermined position on the upper surface of a glass substrate 1, and a gate insulating film is formed on the entire upper surface. A film 3 is formed, a semiconductor layer 4 made of a non-single crystal semiconductor such as amorphous silicon or polysilicon is formed on the upper surface of the film 3, and an ion implantation mask 5 made of a photoresist is formed on a predetermined portion of the upper surface. Next, ions such as phosphorus ions and boron ions are implanted using the ion implantation mask 5 as a mask,
Ion implantation regions 4a to be source / drain regions are formed in the semiconductor layer 4 in regions other than under the ion implantation mask 5. Next, as shown in FIG. 2B, when the silicide forming metal layer 6 made of chromium or the like is formed on the entire upper surface, the surface portion of the semiconductor layer 4 in a region not covered by the ion implantation mask 5, that is, the ion implantation is performed. The silicide layer 7 is formed on the surface of the region 4a. Next, the silicide layer 7
2C is obtained by removing the silicide forming metal layer 6 that does not contribute to the formation of Al by wet etching. After that, the ion implantation mask 5 is removed. In this case, since the upper layer portion of the ion implantation mask 5 made of a photoresist is denatured and hardened by the ion implantation,
It is difficult to remove it by wet etching using an organic alkaline etching solution such as TW solution, and therefore it is removed by dry etching using O ₂ plasma. Although not shown, a thin film transistor having the silicide layer 7, that is, the silicide wiring is completed after a predetermined process such as element isolation.

[0003]

However, in the conventional method of manufacturing such a thin film transistor, the surface of the silicide layer 7 is oxidized when the ion implantation mask 5 made of photoresist is removed by dry etching using O ₂ plasma. As a result, there is a problem that the resistance value of the silicide layer 7 increases and the effect of forming the silicide wiring is weakened. An object of the present invention is to provide a method of manufacturing a thin film transistor that can prevent the resistance value of a silicide layer from rising.

[0004]

According to the present invention, an ion implantation mask made of a photoresist is formed at a predetermined position on a non-single-crystal semiconductor layer, and the ion implantation mask is used as a mask to introduce ions into the non-single-crystal semiconductor layer. Then, the upper layer portion of the ion implantation mask is removed by dry etching, a silicide layer is formed on the surface of the ion implantation region of the non-single crystal semiconductor layer, and then the ion implantation mask is removed by wet etching. It is the one.

[0005]

According to the present invention, even if the upper layer portion of the ion implantation mask made of a photoresist is deteriorated by ion implantation and hardened, the upper layer portion is removed by dry etching, and then the non-single crystal. Since the silicide layer is formed on the surface of the ion implantation region of the semiconductor layer, the ion implantation mask can be easily removed by wet etching, and the surface of the silicide layer can be prevented from being oxidized. The resistance value of the layer can be prevented from increasing.

[0006]

1 (A) to 1 (E) show respective steps of manufacturing a thin film transistor according to an embodiment of the present invention. So, referring to these figures in order,
A method of manufacturing the thin film transistor of this example will be described.

First, as shown in FIG. 1A, a gate electrode 12 made of a conductive material such as chromium or aluminum is formed on a predetermined portion of the upper surface of a glass substrate 11 by sputtering or the like to a film thickness of about 1000 Å. After that, it is formed by patterning. Next, a gate insulating film 13 made of silicon oxide or nitride is formed on the entire upper surface of the glass substrate 11 including the gate electrode 12 by sputtering, plasma CVD, or the like to a film thickness of about 4000 Å. Next, a semiconductor layer 14 made of a non-single crystal semiconductor such as amorphous silicon or polysilicon is formed on the upper surface of the gate insulating film 13 by plasma C.
A film having a film thickness of about 500 Å is formed by VD or the like. Next, an ion implantation mask 15 made of photoresist is formed on the upper surface of the semiconductor layer 14 corresponding to the gate electrode 12 by spin coating or the like to a film thickness of about 10000Å, and then patterned. Next, ions such as phosphorus ions and boron ions are implanted using the ion implantation mask 15 as a mask to form the ion implantation regions 14a to be the source / drain regions in the semiconductor layer 14 in regions other than under the ion implantation mask 15.

In this state, the upper layer portion of the ion implantation mask 15 made of photoresist is altered and hardened by the ion implantation. Therefore, next, this alteration hardening portion, that is, the upper layer portion of the ion implantation mask 15 having a film thickness of about 2000 Å,
As shown in FIG. 1B, it is removed by dry etching using O ₂ plasma. Next, as shown in FIG. 1C, a silicide forming metal layer 16 made of chromium or the like is formed to a film thickness of about 100 Å on the entire upper surface of the semiconductor layer 14 including the ion implantation mask 15 by sputtering or the like. A silicide layer 17 having a film thickness of about 50Å is formed on the surface of the semiconductor layer 14 in the region not covered by the ion implantation mask 15, that is, the surface of the ion implantation region 14a. Next, the metal layer 16 for forming a silicide that does not contribute to the formation of the silicide layer 7 is removed by wet etching, and then the ion implantation mask 15 is removed. Since the upper layer portion has already been removed, it can be easily removed by wet etching with an organic alkaline etching solution such as a TW solution (see FIG. 1D). Moreover, in this case, since the dry etching is not performed by O ₂ plasma, the surface of the silicide layer 17 is not oxidized, so that the resistance value of the silicide layer 17 can be prevented from increasing.

Next, the semiconductor layer 1 including the silicide layer 17
4 is patterned, the semiconductor layer 14 having the channel region 14b made of the intrinsic region and the source / drain region 14c made of the ion-implanted region having the silicide layer 17 on the upper surface becomes the device region as shown in FIG. It is formed. Next, an interlayer insulating film 18 made of silicon oxide, nitride, etc. is formed on the entire upper surface by plasma CVD.
A film is formed to a film thickness of about 000Å, and at the same time, implanted ions are activated. The activation of implanted ions is 200
You may make it heat-process at the temperature of about -300 degreeC for 1 hour or more. Next, contact holes 19 are formed in the interlayer insulating film 18 at the portions corresponding to both silicide layers 17, and then a film thickness of 5000 Å made of a conductive material such as aluminum or chromium is formed on the interlayer insulating film 18 at the portions of these contact holes 19. Source / drain electrode 2
Form 0. Thus, the thin film transistor including the silicide layer 17, that is, the silicide wiring is completed.

Although the bottom gate type thin film transistor has been described in the above embodiment, the present invention is not limited to this.
It is possible to apply various modifications such as a top gate type thin film transistor.

[0011]

As described above, according to the present invention, even if the upper layer portion of the ion implantation mask made of a photoresist is deteriorated by ion implantation and hardened, the upper layer portion is removed by dry etching, and thereafter, Since the silicide layer is formed on the surface of the source / drain region of the non-single-crystal semiconductor layer and the ion implantation mask is removed by wet etching, the surface of the silicide layer is oxidized. Therefore, it is possible to prevent the resistance value of the silicide layer from increasing.

[Brief description of drawings]

1A to 1E are cross-sectional views showing respective manufacturing steps of a thin film transistor according to an embodiment of the present invention.

2A to 2C are cross-sectional views showing respective manufacturing steps of a conventional thin film transistor.

[Explanation of symbols]

14 Semiconductor layer 14a ion implantation region 14c Source / drain region 15 Ion implantation mask 17 Silicide layer 20 Source / drain electrodes

Claims (2)

(57) [Claims] 1. A photomask is formed at a predetermined position on the non-single crystal semiconductor layer.
An ion implantation mask made of a photoresist is formed, ions are implanted into the non-single-crystal semiconductor layer using the ion implantation mask as a mask, the upper layer of the ion implantation mask is removed by dry etching, and then the above-mentioned ion implantation mask is removed. Non-single
A method of manufacturing a thin film transistor, comprising forming a silicide layer on a surface of an ion implantation region of a crystalline semiconductor layer, and then removing the ion implantation mask by wet etching. 2. The method of manufacturing a thin film transistor according to claim 1, wherein the source / drain regions are formed by the ion-implanted regions of the non-single-crystal semiconductor layer, and the source / drain electrodes are formed on the silicide layer. .